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X-CSE-ConnectionGUID: 7AFuOB5WSrGfdTgTVO+lLg== X-CSE-MsgGUID: cIrqoMhWSaOnxCRgeiC8NA== X-IronPort-AV: E=McAfee;i="6700,10204,11228"; a="31600069" X-IronPort-AV: E=Sophos;i="6.11,212,1725346800"; d="scan'208";a="31600069" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Oct 2024 18:40:47 -0700 X-CSE-ConnectionGUID: z6JeZNnfTPie96BeQlwMoA== X-CSE-MsgGUID: CYi6Ge/mRDKNDUqFFnbDbA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,212,1725346800"; d="scan'208";a="83293289" Received: from yilunxu-optiplex-7050.sh.intel.com (HELO localhost) ([10.239.159.165]) by fmviesa005.fm.intel.com with ESMTP; 17 Oct 2024 18:40:43 -0700 Date: Fri, 18 Oct 2024 09:37:22 +0800 From: Xu Yilun To: iansdannapel@gmail.com Cc: mdf@kernel.org, hao.wu@intel.com, yilun.xu@intel.com, trix@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, heiko.stuebner@cherry.de, rafal@milecki.pl, linus.walleij@linaro.org, linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/3] fpga: Add Efinix Trion & Titanium serial SPI programming driver Message-ID: References: <20240927141445.157234-1-iansdannapel@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240927141445.157234-1-iansdannapel@gmail.com> On Fri, Sep 27, 2024 at 04:14:42PM +0200, iansdannapel@gmail.com wrote: > From: Ian Dannapel > > Add a new driver for loading binary firmware to volatile > configuration RAM using "SPI passive programming" on Efinix FPGAs. > > Signed-off-by: Ian Dannapel > --- > drivers/fpga/Kconfig | 10 ++ > drivers/fpga/Makefile | 1 + > drivers/fpga/efinix-trion-spi-passive.c | 211 ++++++++++++++++++++++++ > 3 files changed, 222 insertions(+) > create mode 100644 drivers/fpga/efinix-trion-spi-passive.c > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig > index 37b35f58f0df..eb1e44c4e3e0 100644 > --- a/drivers/fpga/Kconfig > +++ b/drivers/fpga/Kconfig > @@ -83,6 +83,16 @@ config FPGA_MGR_XILINX_SPI > FPGA manager driver support for Xilinx FPGA configuration > over slave serial interface. > > +config FPGA_MGR_EFINIX_SPI > + tristate "Efinix FPGA configuration over SPI passive" > + depends on SPI > + help > + This option enables support for the FPGA manager driver to > + configure Efinix Trion and Titanium Series FPGAs over SPI > + using passive serial mode. > + Warning: Do not activate this if there are other SPI devices > + on the same bus as it might interfere with the transmission. Sorry, this won't work. As you can see, the conflict usage of CS causes several concerns. Just a text here is far from enough. You need to actively work with SPI core/controller drivers to find a solution that coordinate the usage of this pin. Thanks Yilun