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AJvYcCXlvyq901aXECUet9SIkZCIMI8WKtmC4kebHgfWYfKcFsdvCFkv4hUmnCIoK7GwrWNaIALgMJxggmtb@vger.kernel.org X-Gm-Message-State: AOJu0YxLBdn/FLBfxel2NNlshotcqcM3XQAuuX1FVf9ig0txgONI4soE dRaZlHQvtuX9jsjscFB9vq0kl+9JXxN+x14JAuKKm1DSZs1vBoWvZzmHwYbwpfE= X-Google-Smtp-Source: AGHT+IF1Hi3RvwWs7DSq+spdpzYUhwOwwmzTbkypHgqr1nBe6xd71RG+VXm6t9yCvd53dDUoi1AkKw== X-Received: by 2002:a5d:5a13:0:b0:37c:fbf8:fc4 with SMTP id ffacd0b85a97d-381c7af3be3mr3201528f8f.59.1730460114103; Fri, 01 Nov 2024 04:21:54 -0700 (PDT) Received: from linaro.org ([82.76.168.176]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381c113e89csm4808765f8f.74.2024.11.01.04.21.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2024 04:21:53 -0700 (PDT) Date: Fri, 1 Nov 2024 13:21:52 +0200 From: Abel Vesa To: Konrad Dybcio Cc: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Johan Hovold , Dmitry Baryshkov , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: Re: [PATCH v3 2/3] arm64: dts: qcom: x1e80100: Describe TLMM pins for SDC2 Message-ID: References: <20241022-x1e80100-qcp-sdhc-v3-0-46c401e32cbf@linaro.org> <20241022-x1e80100-qcp-sdhc-v3-2-46c401e32cbf@linaro.org> <327507d8-2dc7-4645-ac3d-d68ff31a84dd@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <327507d8-2dc7-4645-ac3d-d68ff31a84dd@oss.qualcomm.com> On 24-10-28 14:10:54, Konrad Dybcio wrote: > On 28.10.2024 9:48 AM, Abel Vesa wrote: > > On 24-10-25 20:34:19, Konrad Dybcio wrote: > >> On 22.10.2024 12:46 PM, Abel Vesa wrote: > >>> Describe the SDC2 default and sleep state pins configuration > >>> in TLMM. Do this in SoC dtsi file since they will be shared > >>> across multiple boards. > >>> > >>> Signed-off-by: Abel Vesa > >>> --- > >> > >> Not very useful on its own but okay.. > > > > Fair enough. For some reason, I'm not able to get sdc4 pinconf > > to work. > > Any chance you tried to define 'sdc4_cmd' etc.? This one seems to have > sdc4 pins on gpio127..=132 Yes. But since the sdc4 pins can have other functions and since there is no device that uses them (yet). Shouldn't we just skip describing the sdc4 pinconf entirely as that should be done on a per-board basis? > > Konrad