From: claudiu beznea <claudiu.beznea@tuxon.dev>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: magnus.damm@gmail.com, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
mturquette@baylibre.com, sboyd@kernel.org,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Subject: Re: [PATCH 4/6] arm64: dts: renesas: rzg3s-smarc-som: Enable SDHI2
Date: Fri, 13 Oct 2023 08:45:52 +0300 [thread overview]
Message-ID: <a007c3a9-0a68-4f4c-bcea-4ffc111939a1@tuxon.dev> (raw)
In-Reply-To: <CAMuHMdW-m+ikzOiCqGaiofd0QG5BVuoMK+z6G7u2JboGTw3xhQ@mail.gmail.com>
Hi, Geert,
Thanks for reviewing!
On 12.10.2023 17:36, Geert Uytterhoeven wrote:
> Hi Claudiu,
>
> Thanks for your patch!
>
> On Tue, Oct 10, 2023 at 3:27 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> Add SDHI2 to RZ/G3S Smarc SoM. SDHI2 pins are multiplexed with SCIF1, SSI3,
>
> SSI0
>
>> IRQ0. The selection b/w SDHI2 and SCIF1, SSI3, IRQ0 is done with a switch
>
> and IRQ1 (twice). Or just say "The selection is done ...".
>
>> button. To be able to select b/w these a compilation flag has been added
>> (SW_SD2_EN) at the moment being instantiated to select SDHI2.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
>> --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
>> +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
>> @@ -13,14 +13,21 @@
>> * @SW_SD0_DEV_SEL:
>> * 0 - SD0 is connected to eMMC
>> * 1 - SD0 is connected to uSD0 card
>> + * @SW_SD2_EN:
>> + * 0 - SCIF1, SSI3, IRQ0, IRQ1 connected to SoC
>
> SSI0
>
>> + * 1 - SD2 is connected to SoC
>> */
>> #define SW_SD0_DEV_SEL 1
>> +#define SW_SD2_EN 1
>
>> @@ -100,6 +125,19 @@ &sdhi0 {
>> };
>> #endif
>>
>> +#if SW_SD2_EN
>> +&sdhi2 {
>> + pinctrl-0 = <&sdhi2_pins>;
>> + pinctrl-1 = <&sdhi2_pins>;
>> + pinctrl-names = "default", "state_uhs";
>
> Do you need two states if there is only a single voltage?
> AFAIK, UHS needs 1.8V.
I had the impression that driver needs them both anyway. I double checked
now and it seems it is not the case. I'll update it in the next version.
Thank you,
Claudiu Beznea
>
>> + vmmc-supply = <&vcc_sdhi2>;
>> + vqmmc-supply = <®_3p3v>;
>> + bus-width = <4>;
>> + max-frequency = <50000000>;
>> + status = "okay";
>> +};
>> +#endif
>> +
>> &pinctrl {
>> sdhi0_pins: sd0 {
>> data {
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
next prev parent reply other threads:[~2023-10-13 5:46 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-10 13:26 [PATCH 0/6] arm64: dts: renesas: Add SDHI1 and SDHI2 for RZ/G3S Claudiu
2023-10-10 13:26 ` [PATCH 1/6] clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R() Claudiu
2023-10-10 14:52 ` Sergei Shtylyov
2023-10-11 7:36 ` claudiu beznea
2023-10-11 7:43 ` Geert Uytterhoeven
2023-10-11 15:55 ` claudiu beznea
2023-10-12 12:37 ` Geert Uytterhoeven
2023-10-10 13:26 ` [PATCH 2/6] clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2 Claudiu
2023-10-12 13:22 ` Geert Uytterhoeven
2023-10-10 13:26 ` [PATCH 3/6] arm64: dts: renesas: r9a08g045: Add nodes " Claudiu
2023-10-12 13:35 ` Geert Uytterhoeven
2023-10-10 13:26 ` [PATCH 4/6] arm64: dts: renesas: rzg3s-smarc-som: Enable SDHI2 Claudiu
2023-10-12 14:36 ` Geert Uytterhoeven
2023-10-13 5:45 ` claudiu beznea [this message]
2023-10-10 13:27 ` [PATCH 5/6] arm64: dts: renesas: rzg3s-smarc: Enable SDHI1 Claudiu
2023-10-12 14:44 ` Geert Uytterhoeven
2023-10-13 5:51 ` claudiu beznea
2023-10-10 13:27 ` [PATCH 6/6] arm64: dts: renesas: rzg3s: Fix dtbs_check Claudiu
2023-10-12 14:49 ` Geert Uytterhoeven
2023-10-13 5:55 ` claudiu beznea
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