* [PATCH 0/1] Add eMMC support for qcs8300
@ 2025-06-12 9:21 Sayali Lokhande
2025-06-12 9:21 ` [PATCH 1/1] arm64: dts: msm: " Sayali Lokhande
2025-06-12 20:12 ` [PATCH 0/1] " Rob Herring (Arm)
0 siblings, 2 replies; 5+ messages in thread
From: Sayali Lokhande @ 2025-06-12 9:21 UTC (permalink / raw)
To: andersson, konradybcio, robh, krzk+dt, conor+dt
Cc: linux-arm-msm, devicetree, linux-kernel, linux-mmc-owner
Add eMMC support for qcs8300 board.
Sayali Lokhande (1):
arm64: dts: msm: Add eMMC support for qcs8300
arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 33 ++++++++
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 97 +++++++++++++++++++++++
2 files changed, 130 insertions(+)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/1] arm64: dts: msm: Add eMMC support for qcs8300
2025-06-12 9:21 [PATCH 0/1] Add eMMC support for qcs8300 Sayali Lokhande
@ 2025-06-12 9:21 ` Sayali Lokhande
2025-06-12 10:02 ` Krzysztof Kozlowski
2025-06-13 19:40 ` Konrad Dybcio
2025-06-12 20:12 ` [PATCH 0/1] " Rob Herring (Arm)
1 sibling, 2 replies; 5+ messages in thread
From: Sayali Lokhande @ 2025-06-12 9:21 UTC (permalink / raw)
To: andersson, konradybcio, robh, krzk+dt, conor+dt
Cc: linux-arm-msm, devicetree, linux-kernel, linux-mmc-owner
Add eMMC support for qcs8300 board.
Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 33 ++++++++
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 97 +++++++++++++++++++++++
2 files changed, 130 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
index 8c166ead912c..73aabed0f4f9 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
@@ -407,3 +407,36 @@
&usb_2_dwc3 {
dr_mode = "host";
};
+
+&sdc1_clk {
+ bias-disable;
+ drive-strength = <16>;
+};
+
+&sdc1_cmd {
+ bias-pull-up;
+ drive-strength = <10>;
+};
+
+&sdc1_data {
+ bias-pull-up;
+ drive-strength = <10>;
+};
+
+&sdc1_rclk {
+ bias-pull-down;
+};
+
+&sdhc_1 {
+ vmmc-supply = <&vreg_l8a>;
+ vqmmc-supply = <&vreg_s4a>;
+
+ no-sd;
+ no-sdio;
+ non-removable;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>;
+ pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 7ada029c32c1..5dee0b913b88 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -3837,6 +3837,62 @@
clock-names = "apb_pclk";
};
+ sdhc_1: mmc@87C4000 {
+ compatible = "qcom,sdhci-msm-v5";
+ status = "disabled";
+
+ reg = <0x0 0x87C4000 0x0 0x1000>,
+ <0x0 0x87C5000 0x0 0x1000>;
+ reg-names = "hc", "cqhci";
+
+ interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "core", "xo";
+ interconnects = <&aggre1_noc MASTER_SDC 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDC1 0>;
+ interconnect-names = "sdhc-ddr","cpu-sdhc";
+
+ operating-points-v2 = <&sdhc1_opp_table>;
+ bus-width = <8>;
+ supports-cqe;
+ dma-coherent;
+
+ qcom,dll-config = <0x000F64EE>;
+ qcom,ddr-config = <0x80040868>;
+
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+
+ iommus = <&apps_smmu 0x0 0x0>;
+
+ resets = <&gcc GCC_SDCC1_BCR>;
+
+ sdhc1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1800000 400000>;
+ opp-avg-kBps = <100000 0>;
+ };
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <5400000 1600000>;
+ opp-avg-kBps = <390000 0>;
+ };
+ };
+ };
+
usb_1_hsphy: phy@8904000 {
compatible = "qcom,qcs8300-usb-hs-phy",
"qcom,usb-snps-hs-7nm-phy";
@@ -5042,6 +5098,47 @@
pins = "gpio13";
function = "qup2_se0";
};
+
+ sdc1_clk: sdc1-clk-state {
+ pins = "sdc1_clk";
+
+ };
+
+ sdc1_cmd: sdc1-cmd-state {
+ pins = "sdc1_cmd";
+ };
+
+ sdc1_data: sdc1-data-state {
+ pins = "sdc1_data";
+ };
+
+ sdc1_rclk: sdc1-rclk-state {
+ pins = "sdc1_rclk";
+ };
+
+ sdc1_clk_sleep: sdc1-clk-sleep-state {
+ pins = "sdc1_clk";
+ drive-strength = <2>;
+ bias-bus-hold;
+ };
+
+ sdc1_cmd_sleep: sdc1-cmd-sleep-state {
+ pins = "sdc1_cmd";
+ drive-strength = <2>;
+ bias-bus-hold;
+ };
+
+ sdc1_data_sleep: sdc1-data-sleep-state {
+ pins = "sdc1_data";
+ drive-strength = <2>;
+ bias-bus-hold;
+ };
+
+ sdc1_rclk_sleep: sdc1-rclk-sleep-state {
+ pins = "sdc1_rclk";
+ drive-strength = <2>;
+ bias-bus-hold;
+ };
};
sram: sram@146d8000 {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/1] arm64: dts: msm: Add eMMC support for qcs8300
2025-06-12 9:21 ` [PATCH 1/1] arm64: dts: msm: " Sayali Lokhande
@ 2025-06-12 10:02 ` Krzysztof Kozlowski
2025-06-13 19:40 ` Konrad Dybcio
1 sibling, 0 replies; 5+ messages in thread
From: Krzysztof Kozlowski @ 2025-06-12 10:02 UTC (permalink / raw)
To: Sayali Lokhande, andersson, konradybcio, robh, krzk+dt, conor+dt
Cc: linux-arm-msm, devicetree, linux-kernel, linux-mmc-owner
On 12/06/2025 11:21, Sayali Lokhande wrote:
> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
Please use subject prefixes matching the subsystem. You can get them for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching. For bindings, the preferred subjects are
explained here:
https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters
It is NEVER msm. Also missing soc/board prefix.
> index 7ada029c32c1..5dee0b913b88 100644
> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> @@ -3837,6 +3837,62 @@
> clock-names = "apb_pclk";
> };
>
> + sdhc_1: mmc@87C4000 {
> + compatible = "qcom,sdhci-msm-v5";
> + status = "disabled";
That's not correct place. Please follow DTS coding style.
> +
> + reg = <0x0 0x87C4000 0x0 0x1000>,
> + <0x0 0x87C5000 0x0 0x1000>;
Look at the rest of the file: lower or upper hex is used?
> + reg-names = "hc", "cqhci";
> +
> + interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq", "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> + <&gcc GCC_SDCC1_APPS_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface", "core", "xo";
> + interconnects = <&aggre1_noc MASTER_SDC 0 &mc_virt SLAVE_EBI1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDC1 0>;
> + interconnect-names = "sdhc-ddr","cpu-sdhc";
> +
> + operating-points-v2 = <&sdhc1_opp_table>;
> + bus-width = <8>;
> + supports-cqe;
> + dma-coherent;
> +
> + qcom,dll-config = <0x000F64EE>;
> + qcom,ddr-config = <0x80040868>;
> +
> + mmc-ddr-1_8v;
> + mmc-hs200-1_8v;
> + mmc-hs400-1_8v;
> + mmc-hs400-enhanced-strobe;
All these do not look like SoC-level properties.
> +
> + iommus = <&apps_smmu 0x0 0x0>;
> +
> + resets = <&gcc GCC_SDCC1_BCR>;
> +
> + sdhc1_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-100000000 {
> + opp-hz = /bits/ 64 <100000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <1800000 400000>;
> + opp-avg-kBps = <100000 0>;
> + };
> +
> + opp-384000000 {
> + opp-hz = /bits/ 64 <384000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + opp-peak-kBps = <5400000 1600000>;
> + opp-avg-kBps = <390000 0>;
> + };
> + };
> + };
> +
> usb_1_hsphy: phy@8904000 {
> compatible = "qcom,qcs8300-usb-hs-phy",
> "qcom,usb-snps-hs-7nm-phy";
> @@ -5042,6 +5098,47 @@
> pins = "gpio13";
> function = "qup2_se0";
> };
> +
> + sdc1_clk: sdc1-clk-state {
> + pins = "sdc1_clk";
> +
Stray blank line
> + };
> +
> + sdc1_cmd: sdc1-cmd-state {
> + pins = "sdc1_cmd";
> + };
> +
> + sdc1_data: sdc1-data-state {
> + pins = "sdc1_data";
> + };
> +
> + sdc1_rclk: sdc1-rclk-state {
> + pins = "sdc1_rclk";
> + };
Anyway, what is the point of all above pin nodes without config or muxing?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 0/1] Add eMMC support for qcs8300
2025-06-12 9:21 [PATCH 0/1] Add eMMC support for qcs8300 Sayali Lokhande
2025-06-12 9:21 ` [PATCH 1/1] arm64: dts: msm: " Sayali Lokhande
@ 2025-06-12 20:12 ` Rob Herring (Arm)
1 sibling, 0 replies; 5+ messages in thread
From: Rob Herring (Arm) @ 2025-06-12 20:12 UTC (permalink / raw)
To: Sayali Lokhande
Cc: andersson, linux-arm-msm, konradybcio, krzk+dt, conor+dt,
devicetree, linux-mmc-owner, linux-kernel
On Thu, 12 Jun 2025 14:51:45 +0530, Sayali Lokhande wrote:
> Add eMMC support for qcs8300 board.
>
> Sayali Lokhande (1):
> arm64: dts: msm: Add eMMC support for qcs8300
>
> arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 33 ++++++++
> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 97 +++++++++++++++++++++++
> 2 files changed, 130 insertions(+)
>
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
This patch series was applied (using b4) to base:
Base: attempting to guess base-commit...
Base: tags/next-20250612 (exact match)
If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)
New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/qcom/' for 20250612092146.5170-1-quic_sayalil@quicinc.com:
arch/arm64/boot/dts/qcom/qcs8300-ride.dtb: soc@0 (simple-bus): mmc@87C4000: 'ranges' is a required property
from schema $id: http://devicetree.org/schemas/simple-bus.yaml#
arch/arm64/boot/dts/qcom/qcs8300-ride.dtb: mmc@87C4000 (qcom,sdhci-msm-v5): compatible: 'oneOf' conditional failed, one must be fixed:
['qcom,sdhci-msm-v5'] is too short
'qcom,sdhci-msm-v5' is not one of ['qcom,sdhci-msm-v4']
'qcom,sdhci-msm-v5' is not one of ['qcom,apq8084-sdhci', 'qcom,ipq4019-sdhci', 'qcom,ipq8074-sdhci', 'qcom,msm8226-sdhci', 'qcom,msm8953-sdhci', 'qcom,msm8974-sdhci', 'qcom,msm8976-sdhci', 'qcom,msm8916-sdhci', 'qcom,msm8992-sdhci', 'qcom,msm8994-sdhci', 'qcom,msm8996-sdhci', 'qcom,msm8998-sdhci']
'qcom,sdhci-msm-v5' is not one of ['qcom,ipq5018-sdhci', 'qcom,ipq5332-sdhci', 'qcom,ipq5424-sdhci', 'qcom,ipq6018-sdhci', 'qcom,ipq9574-sdhci', 'qcom,qcm2290-sdhci', 'qcom,qcs404-sdhci', 'qcom,qcs615-sdhci', 'qcom,qdu1000-sdhci', 'qcom,sar2130p-sdhci', 'qcom,sc7180-sdhci', 'qcom,sc7280-sdhci', 'qcom,sc8280xp-sdhci', 'qcom,sdm630-sdhci', 'qcom,sdm670-sdhci', 'qcom,sdm845-sdhci', 'qcom,sdx55-sdhci', 'qcom,sdx65-sdhci', 'qcom,sdx75-sdhci', 'qcom,sm6115-sdhci', 'qcom,sm6125-sdhci', 'qcom,sm6350-sdhci', 'qcom,sm6375-sdhci', 'qcom,sm7150-sdhci', 'qcom,sm8150-sdhci', 'qcom,sm8250-sdhci', 'qcom,sm8350-sdhci', 'qcom,sm8450-sdhci', 'qcom,sm8550-sdhci', 'qcom,sm8650-sdhci', 'qcom,x1e80100-sdhci']
from schema $id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
arch/arm64/boot/dts/qcom/qcs8300-ride.dtb: mmc@87C4000 (qcom,sdhci-msm-v5): Unevaluated properties are not allowed ('compatible' was unexpected)
from schema $id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/1] arm64: dts: msm: Add eMMC support for qcs8300
2025-06-12 9:21 ` [PATCH 1/1] arm64: dts: msm: " Sayali Lokhande
2025-06-12 10:02 ` Krzysztof Kozlowski
@ 2025-06-13 19:40 ` Konrad Dybcio
1 sibling, 0 replies; 5+ messages in thread
From: Konrad Dybcio @ 2025-06-13 19:40 UTC (permalink / raw)
To: Sayali Lokhande, andersson, konradybcio, robh, krzk+dt, conor+dt
Cc: linux-arm-msm, devicetree, linux-kernel, linux-mmc-owner
On 6/12/25 11:21 AM, Sayali Lokhande wrote:
> Add eMMC support for qcs8300 board.
>
> Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com>
> ---
[...]
> + sdhc_1: mmc@87C4000 {
> + compatible = "qcom,sdhci-msm-v5";
This needs a SoC-specific compatible and a corresponding dt-bindings
change (see other soc dtsi files, e.g. x1e80100.dtsi)
> + status = "disabled";
> +
> + reg = <0x0 0x87C4000 0x0 0x1000>,
> + <0x0 0x87C5000 0x0 0x1000>;
Please align the '<'s across this change
> + reg-names = "hc", "cqhci";
> +
> + interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq", "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> + <&gcc GCC_SDCC1_APPS_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface", "core", "xo";
> + interconnects = <&aggre1_noc MASTER_SDC 0 &mc_virt SLAVE_EBI1 0>,
0 -> QCOM_ICC_TAG_ALWAYS on this path
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDC1 0>;
0 -> QCOM_ICC_TAG_ACTIVE_ONLY on this path
> + interconnect-names = "sdhc-ddr","cpu-sdhc";
one per line, please, also change-wide
Konrad
^ permalink raw reply [flat|nested] 5+ messages in thread
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2025-06-12 9:21 [PATCH 0/1] Add eMMC support for qcs8300 Sayali Lokhande
2025-06-12 9:21 ` [PATCH 1/1] arm64: dts: msm: " Sayali Lokhande
2025-06-12 10:02 ` Krzysztof Kozlowski
2025-06-13 19:40 ` Konrad Dybcio
2025-06-12 20:12 ` [PATCH 0/1] " Rob Herring (Arm)
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