[PATCH v2 0/8] MT8188 DT and binding fixes

[PATCH v2 0/8] MT8188 DT and binding fixes

[Fei Shao]

Hi,

This series is split from a previous series[*] to focus on few fixes and
improvements around MediaTek MT8188 device tree and associated bindings,
and addressed comments and carried tags from the previous series.

[*]: https://lore.kernel.org/all/20240909111535.528624-1-fshao@chromium.org/
[v1]: https://lore.kernel.org/all/20240925110044.3678055-1-fshao@chromium.org/

Regards,
Fei

Changes in v2:
- new patch to MediaTek jpeg and vcodec bindings
- new patch to move MT8188 SPI NOR cell properties
- revise commit message of vdec power domain changes

Fei Shao (8):
  dt-bindings: power: mediatek: Add another nested power-domain layer
  dt-bindings: PCI: mediatek-gen3: Allow exact number of clocks only
  dt-bindings: media: mediatek,jpeg: Relax IOMMU max item count
  dt-bindings: media: mediatek,vcodec: Revise description
  arm64: dts: mediatek: mt8188: Add missing dma-ranges to soc node
  arm64: dts: mediatek: mt8188: Update vppsys node names to syscon
  arm64: dts: mediatek: mt8188: Move vdec1 power domain under vdec0
  arm64: dts: mediatek: mt8188: Move SPI NOR *-cells properties

 .../media/mediatek,vcodec-subdev-decoder.yaml | 100 +++++++++++-------
 .../bindings/media/mediatek-jpeg-decoder.yaml |   3 +-
 .../bindings/media/mediatek-jpeg-encoder.yaml |   2 +-
 .../bindings/pci/mediatek-pcie-gen3.yaml      |   5 +-
 .../power/mediatek,power-controller.yaml      |   4 +
 arch/arm64/boot/dts/mediatek/mt8188-evb.dts   |   2 -
 arch/arm64/boot/dts/mediatek/mt8188.dtsi      |  33 +++---
 7 files changed, 88 insertions(+), 61 deletions(-)

-- 
2.46.1.824.gd892dcdcdd-goog

[PATCH v2 1/8] dt-bindings: power: mediatek: Add another nested power-domain layer

[Fei Shao]

The MT8188 SoC has a more in-depth power-domain tree, and the
CHECK_DTBS=y check could fail because the current MediaTek power
dt-binding is insufficient to cover its CAM_SUBA and CAM_SUBB
sub-domains.

Add one more nested power-domain layer to pass the check.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Fei Shao <fshao@chromium.org>
---

(no changes since v1)

 .../devicetree/bindings/power/mediatek,power-controller.yaml  | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
index 8985e2df8a56..a7df4041b745 100644
--- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
+++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
@@ -54,6 +54,10 @@ patternProperties:
             patternProperties:
               "^power-domain@[0-9a-f]+$":
                 $ref: "#/$defs/power-domain-node"
+                patternProperties:
+                  "^power-domain@[0-9a-f]+$":
+                    $ref: "#/$defs/power-domain-node"
+                    unevaluatedProperties: false
                 unevaluatedProperties: false
             unevaluatedProperties: false
         unevaluatedProperties: false
-- 
2.46.1.824.gd892dcdcdd-goog

Re: [PATCH v2 1/8] dt-bindings: power: mediatek: Add another nested power-domain layer

[Ulf Hansson]

On Tue, 1 Oct 2024 at 13:31, Fei Shao <fshao@chromium.org> wrote:
>
> The MT8188 SoC has a more in-depth power-domain tree, and the
> CHECK_DTBS=y check could fail because the current MediaTek power
> dt-binding is insufficient to cover its CAM_SUBA and CAM_SUBB
> sub-domains.
>
> Add one more nested power-domain layer to pass the check.
>
> Acked-by: Rob Herring (Arm) <robh@kernel.org>
> Signed-off-by: Fei Shao <fshao@chromium.org>

Applied for fixes (to silence the warning in v6.13-rc[n], thanks!

Kind regards
Uffe


> ---
>
> (no changes since v1)
>
>  .../devicetree/bindings/power/mediatek,power-controller.yaml  | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
> index 8985e2df8a56..a7df4041b745 100644
> --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
> +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
> @@ -54,6 +54,10 @@ patternProperties:
>              patternProperties:
>                "^power-domain@[0-9a-f]+$":
>                  $ref: "#/$defs/power-domain-node"
> +                patternProperties:
> +                  "^power-domain@[0-9a-f]+$":
> +                    $ref: "#/$defs/power-domain-node"
> +                    unevaluatedProperties: false
>                  unevaluatedProperties: false
>              unevaluatedProperties: false
>          unevaluatedProperties: false
> --
> 2.46.1.824.gd892dcdcdd-goog
>

[PATCH v2 2/8] dt-bindings: PCI: mediatek-gen3: Allow exact number of clocks only

[Fei Shao]

In MediaTek PCIe gen3 bindings, "clocks" accepts a range of 1-6 clocks
across all SoCs. But in practice, each SoC requires a particular number
of clocks as defined in "clock-names", and the length of "clocks" and
"clock-names" can be inconsistent with current bindings.

For example:
- MT8188, MT8192 and MT8195 all require 6 clocks, while the bindings
  accept 4-6 clocks.
- MT7986 requires 4 clocks, while the bindings accept 4-6 clocks.

Update minItems and maxItems properties for individual SoCs as needed to
only accept the correct number of clocks.

Fixes: c6abd0eadec6 ("dt-bindings: PCI: mediatek-gen3: Add support for Airoha EN7581")
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Fei Shao <fshao@chromium.org>
---

(no changes since v1)

 .../devicetree/bindings/pci/mediatek-pcie-gen3.yaml          | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
index 898c1be2d6a4..f05aab2b1add 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
@@ -149,7 +149,7 @@ allOf:
     then:
       properties:
         clocks:
-          minItems: 4
+          minItems: 6
 
         clock-names:
           items:
@@ -178,7 +178,7 @@ allOf:
     then:
       properties:
         clocks:
-          minItems: 4
+          minItems: 6
 
         clock-names:
           items:
@@ -207,6 +207,7 @@ allOf:
       properties:
         clocks:
           minItems: 4
+          maxItems: 4
 
         clock-names:
           items:
-- 
2.46.1.824.gd892dcdcdd-goog

[PATCH v2 3/8] dt-bindings: media: mediatek,jpeg: Relax IOMMU max item count

[Fei Shao]

On MediaTek platforms with Multimedia MMU (M4U), a multimedia hardware
can be assigned with a local arbiter (LARB) which has a maximum of 32
ports for MediaTek's IOMMU infrastructure. That means there can be at
most 32 items in the iommus property in theory.

Instead of relaxing the max item count every time a newly introduced
device tree hits the limit, bump the number to 32 as an one-time effort.

On the other hand, all existing and foreseeable JPEG decoder nodes at
this point have at least 2 IOMMUs, so set minItems to 2 accordingly.

Signed-off-by: Fei Shao <fshao@chromium.org>
---
It's not in the upstream tree yet, but the upcoming MT8188 DT will have
6 IOMMUs in its JPEG decoder. This patch is to pave the way for that.

Changes in v2:
New patch.

 .../devicetree/bindings/media/mediatek-jpeg-decoder.yaml       | 3 ++-
 .../devicetree/bindings/media/mediatek-jpeg-encoder.yaml       | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml
index cfabf360f278..a4aacd3eb189 100644
--- a/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml
@@ -44,7 +44,8 @@ properties:
     maxItems: 1
 
   iommus:
-    maxItems: 2
+    minItems: 2
+    maxItems: 32
     description: |
       Points to the respective IOMMU block with master port as argument, see
       Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml
index 83c020a673d6..5b15f8977f67 100644
--- a/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml
@@ -39,7 +39,7 @@ properties:
 
   iommus:
     minItems: 2
-    maxItems: 4
+    maxItems: 32
     description: |
       Points to the respective IOMMU block with master port as argument, see
       Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
-- 
2.46.1.824.gd892dcdcdd-goog

Re: [PATCH v2 3/8] dt-bindings: media: mediatek,jpeg: Relax IOMMU max item count

[Krzysztof Kozlowski]

On Tue, Oct 01, 2024 at 07:27:21PM +0800, Fei Shao wrote:
> On MediaTek platforms with Multimedia MMU (M4U), a multimedia hardware
> can be assigned with a local arbiter (LARB) which has a maximum of 32
> ports for MediaTek's IOMMU infrastructure. That means there can be at
> most 32 items in the iommus property in theory.
> 
> Instead of relaxing the max item count every time a newly introduced
> device tree hits the limit, bump the number to 32 as an one-time effort.
> 
> On the other hand, all existing and foreseeable JPEG decoder nodes at
> this point have at least 2 IOMMUs, so set minItems to 2 accordingly.
> 
> Signed-off-by: Fei Shao <fshao@chromium.org>
> ---
> It's not in the upstream tree yet, but the upcoming MT8188 DT will have
> 6 IOMMUs in its JPEG decoder. This patch is to pave the way for that.
> 
> Changes in v2:
> New patch.
> 

I do not see any user of this in this patchset.

Best regards,
Krzysztof

Re: [PATCH v2 3/8] dt-bindings: media: mediatek,jpeg: Relax IOMMU max item count

[Fei Shao]

On Wed, Oct 2, 2024 at 2:16 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On Tue, Oct 01, 2024 at 07:27:21PM +0800, Fei Shao wrote:
> > On MediaTek platforms with Multimedia MMU (M4U), a multimedia hardware
> > can be assigned with a local arbiter (LARB) which has a maximum of 32
> > ports for MediaTek's IOMMU infrastructure. That means there can be at
> > most 32 items in the iommus property in theory.
> >
> > Instead of relaxing the max item count every time a newly introduced
> > device tree hits the limit, bump the number to 32 as an one-time effort.
> >
> > On the other hand, all existing and foreseeable JPEG decoder nodes at
> > this point have at least 2 IOMMUs, so set minItems to 2 accordingly.
> >
> > Signed-off-by: Fei Shao <fshao@chromium.org>
> > ---
> > It's not in the upstream tree yet, but the upcoming MT8188 DT will have
> > 6 IOMMUs in its JPEG decoder. This patch is to pave the way for that.
> >
> > Changes in v2:
> > New patch.
> >
>
> I do not see any user of this in this patchset.
>

Sorry, I was doing more checks before sending out that series.
The particular patch depending on this is now available as
https://lore.kernel.org/all/20241002114614.847553-6-fshao@chromium.org/

Regards,
Fei

Re: [PATCH v2 3/8] dt-bindings: media: mediatek,jpeg: Relax IOMMU max item count

[Matthias Brugger]

On 02/10/2024 08:16, Krzysztof Kozlowski wrote:
> On Tue, Oct 01, 2024 at 07:27:21PM +0800, Fei Shao wrote:
>> On MediaTek platforms with Multimedia MMU (M4U), a multimedia hardware
>> can be assigned with a local arbiter (LARB) which has a maximum of 32
>> ports for MediaTek's IOMMU infrastructure. That means there can be at
>> most 32 items in the iommus property in theory.
>>
>> Instead of relaxing the max item count every time a newly introduced
>> device tree hits the limit, bump the number to 32 as an one-time effort.
>>
>> On the other hand, all existing and foreseeable JPEG decoder nodes at
>> this point have at least 2 IOMMUs, so set minItems to 2 accordingly.
>>
>> Signed-off-by: Fei Shao <fshao@chromium.org>
>> ---
>> It's not in the upstream tree yet, but the upcoming MT8188 DT will have
>> 6 IOMMUs in its JPEG decoder. This patch is to pave the way for that.
>>
>> Changes in v2:
>> New patch.
>>
> 
> I do not see any user of this in this patchset.
> 

I'm not sure I understand you: the binding describes the hardware. If it can 
have up to 32 ports, then this should be reflected in the binding.

Regards,
Matthias

Re: [PATCH v2 3/8] dt-bindings: media: mediatek,jpeg: Relax IOMMU max item count

[Krzysztof Kozlowski]

On 02/10/2024 15:12, Matthias Brugger wrote:
> 
> 
> On 02/10/2024 08:16, Krzysztof Kozlowski wrote:
>> On Tue, Oct 01, 2024 at 07:27:21PM +0800, Fei Shao wrote:
>>> On MediaTek platforms with Multimedia MMU (M4U), a multimedia hardware
>>> can be assigned with a local arbiter (LARB) which has a maximum of 32
>>> ports for MediaTek's IOMMU infrastructure. That means there can be at
>>> most 32 items in the iommus property in theory.
>>>
>>> Instead of relaxing the max item count every time a newly introduced
>>> device tree hits the limit, bump the number to 32 as an one-time effort.
>>>
>>> On the other hand, all existing and foreseeable JPEG decoder nodes at
>>> this point have at least 2 IOMMUs, so set minItems to 2 accordingly.
>>>
>>> Signed-off-by: Fei Shao <fshao@chromium.org>
>>> ---
>>> It's not in the upstream tree yet, but the upcoming MT8188 DT will have
>>> 6 IOMMUs in its JPEG decoder. This patch is to pave the way for that.
>>>
>>> Changes in v2:
>>> New patch.
>>>
>>
>> I do not see any user of this in this patchset.
>>
> 
> I'm not sure I understand you: the binding describes the hardware. If it can 
> have up to 32 ports, then this should be reflected in the binding.

Yeah, but people do not describe hardware but drivers. Looking at DTS
clarifies sometimes such cases and avoids lengthy discussions. Plus I
was not really sure if these are IOMMUs for the same device for example
(again: people do weird stuff).

Best regards,
Krzysztof

Re: [PATCH v2 3/8] dt-bindings: media: mediatek,jpeg: Relax IOMMU max item count

[Krzysztof Kozlowski]

On 01/10/2024 13:27, Fei Shao wrote:
> On MediaTek platforms with Multimedia MMU (M4U), a multimedia hardware
> can be assigned with a local arbiter (LARB) which has a maximum of 32
> ports for MediaTek's IOMMU infrastructure. That means there can be at
> most 32 items in the iommus property in theory.
> 
> Instead of relaxing the max item count every time a newly introduced
> device tree hits the limit, bump the number to 32 as an one-time effort.
> 
> On the other hand, all existing and foreseeable JPEG decoder nodes at
> this point have at least 2 IOMMUs, so set minItems to 2 accordingly.
> 
> Signed-off-by: Fei Shao <fshao@chromium.org>
> ---
> It's not in the upstream tree yet, but the upcoming MT8188 DT will have
> 6 IOMMUs in its JPEG decoder. This patch is to pave the way for that.
> 
> Changes in v2:
> New patch.


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH v2 4/8] dt-bindings: media: mediatek,vcodec: Revise description

[Fei Shao]

Revise the description of MediaTek video decoder to improve wording, fix
typos, simplify diagram, and extend the pipeline architecture used in
newer MediaTek SoCs (MT8186 and MT8188).

Signed-off-by: Fei Shao <fshao@chromium.org>
---
Feedback are welcome.
I've tried my best to organize the existing information with some
educated guesses, but there might be inaccuracies or gaps still.
Please let me know if you have anything to add so we can make this more
comprehensive. Thanks!

Changes in v2:
New patch.

 .../media/mediatek,vcodec-subdev-decoder.yaml | 100 +++++++++++-------
 1 file changed, 59 insertions(+), 41 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
index a500a585c692..52a96a5aec96 100644
--- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
@@ -5,52 +5,70 @@
 $id: http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Mediatek Video Decode Accelerator With Multi Hardware
+title: MediaTek Video Decode Accelerator With Multi Hardware
 
 maintainers:
   - Yunfei Dong <yunfei.dong@mediatek.com>
 
 description: |
-  Mediatek Video Decode is the video decode hardware present in Mediatek
-  SoCs which supports high resolution decoding functionalities. Required
-  parent and child device node.
-
-  About the Decoder Hardware Block Diagram, please check below:
-
-    +------------------------------------------------+-------------------------------------+
-    |                                                |                                     |
-    |  input -> lat soc HW -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output  |
-    |            ||             ||                   |                     ||              |
-    +------------||-------------||-------------------+---------------------||--------------+
-                 ||     lat     ||                   |               core workqueue  <parent>
-    -------------||-------------||-------------------|---------------------||---------------
-                 ||<------------||----------------HW index---------------->||        <child>
-                 \/             \/                                         \/
-               +-------------------------------------------------------------+
-               |                          enable/disable                     |
-               |                 clk     power    irq    iommu               |
-               |                   (lat/lat soc/core0/core1)                 |
-               +-------------------------------------------------------------+
-
-  As above, there are parent and child devices, child mean each hardware. The child device
-  controls the information of each hardware independent which include clk/power/irq.
-
-  There are two workqueues in parent device: lat workqueue and core workqueue. They are used
-  to lat and core hardware decoder. Lat workqueue need to get input bitstream and lat buffer,
-  then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode
-  done. Core workqueue need to get lat buffer and output buffer, then enable core to decode,
-  writing the result to output buffer, disable hardware when core decode done. These two
-  hardwares will decode each frame cyclically.
-
-  For the smi common may not the same for each hardware, can't combine all hardware in one node,
-  or leading to iommu fault when access dram data.
-
-  Lat soc is a hardware which is related with some larb(local arbiter) ports. For mt8195
-  platform, there are some ports like RDMA, UFO in lat soc larb, need to enable its power and
-  clock when lat start to work, don't have interrupt.
-
-  mt8195: lat soc HW + lat HW + core HW
-  mt8192: lat HW + core HW
+  MediaTek Video Decode Accelerator is the video decoding hardware present in
+  MediaTek SoCs that supports high-resolution decoding functionalities.
+  It consists of parent and child nodes.
+
+  The decoder hardware block diagram is shown below:
+
+    +------------------------------------------------+------------------------------+
+    |                                                |                              |
+    |  input -> LAT-SoC HW -> LAT HW -> LAT buffer --|--> Core HW -> output buffer  |
+    |              ||           ||                   |       ||                     |
+    +--------------||-----------||-------------------+-------||---------------------+
+                    LAT Workqueue                    |  Core Workqueue       <parent>
+    ---------------||-----------||-------------------|-------||----------------------
+                   ||<----------||---------HW index--------->||              <child>
+                   \/           \/                           \/
+           +-------------------------------------------------------------+
+           |                          enable/disable                     |
+           |                 clk     power    irq    iommu               |
+           |                   (lat/lat-soc/core0/core1)                 |
+           +-------------------------------------------------------------+
+
+  The child nodes represent the individual hardware blocks within the decoding
+  pipeline, such as LAT-SoC, LAT and Core.
+  Each child node is responsible for managing the dedicated resources of the
+  hardware, such as clocks, power domains, interrupts and IOMMUs.
+
+  The parent node is a central point of control for the child nodes.
+  It identifies the specific video decoding pipeline architecture used by the
+  SoC, manages the shared resources like workqueues and platform data, and
+  handles V4L2 API calls on behalf of the underlying hardware.
+
+  The parent utilizes two workqueues to manage the decoding process.
+  1. LAT Workqueue, for LAT-SoC and LAT decoder:
+     Its workers take input bitstream and LAT buffer, enable the hardware for
+     decoding tasks, write the result to LAT buffer, and disable the hardware
+     after the LAT decoding is done.
+  2. Core Workqueue, for Core decoder:
+     Its workers take LAT buffer and output buffer, enable the hardware for
+     decoding tasks, write the result to output buffer, and disable the hardware
+     after the Core decoding is done.
+
+  These hardware decode each frame cyclically.
+
+  The hardware might be associated with different SMI-common devices.
+  To prevent IOMMU faults during DRAM access in such cases, each hardware with
+  the unique SMI-common device must be placed under a separate parent node in
+  the device tree.
+
+  LAT-SoC refers to another hardware block that connected to additional LARB
+  (local arbiter) ports, such as RDMA and UFO.
+  It requires independent power and clock control to work with LAT decoder, and
+  it doesn't have a dedicated interrupt.
+
+  The used video decoding pipeline architecture across various Mediatek SoC:
+    MT8195: LAT-SoC + LAT + Core
+    MT8192: LAT + Core
+    MT8188: LAT + Core
+    MT8186: Core
 
 properties:
   compatible:
-- 
2.46.1.824.gd892dcdcdd-goog

Re: [PATCH v2 4/8] dt-bindings: media: mediatek,vcodec: Revise description

[Krzysztof Kozlowski]

On Tue, Oct 01, 2024 at 07:27:22PM +0800, Fei Shao wrote:
> Revise the description of MediaTek video decoder to improve wording, fix
> typos, simplify diagram, and extend the pipeline architecture used in
> newer MediaTek SoCs (MT8186 and MT8188).
> 
> Signed-off-by: Fei Shao <fshao@chromium.org>
> ---
> Feedback are welcome.
> I've tried my best to organize the existing information with some
> educated guesses, but there might be inaccuracies or gaps still.
> Please let me know if you have anything to add so we can make this more
> comprehensive. Thanks!
> 
> Changes in v2:
> New patch.
> 
>  .../media/mediatek,vcodec-subdev-decoder.yaml | 100 +++++++++++-------
>  1 file changed, 59 insertions(+), 41 deletions(-)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH v2 5/8] arm64: dts: mediatek: mt8188: Add missing dma-ranges to soc node

[Fei Shao]

Add the missing dma-ranges property to the soc node, similar to how it
was done for MT8195 and MT8192.

This allows the entire 16GB of iova range to be used and enables
multimedia processing usages, like vcodec and MIPI camera.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Fei Shao <fshao@chromium.org>
---

(no changes since v1)

 arch/arm64/boot/dts/mediatek/mt8188.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index cd27966d2e3c..69390da9cfe0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -878,6 +878,7 @@ soc {
 		#address-cells = <2>;
 		#size-cells = <2>;
 		compatible = "simple-bus";
+		dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
 		ranges;
 
 		gic: interrupt-controller@c000000 {
-- 
2.46.1.824.gd892dcdcdd-goog

[PATCH v2 6/8] arm64: dts: mediatek: mt8188: Update vppsys node names to syscon

[Fei Shao]

The MediaTek mmsys is more than just a clock controller; it's a
system controller. In addition to clock controls, it provides display
pipeline routing controls and other miscellaneous control registers.

On the MT8188 and MT8195 SoCs, the mmsys blocks utilize the same mmsys
driver but have been aliased to "vdosys" and "vppsys", likely to better
represent their actual functionality.

Update the vppsys node names and compatibles in MT8188 DT to reflect
that and fix dtbs_check errors against mediatek/mt8188-evb.dtb.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Fei Shao <fshao@chromium.org>
---

(no changes since v1)

 arch/arm64/boot/dts/mediatek/mt8188.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index 69390da9cfe0..790315c1bdb3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -1779,8 +1779,8 @@ mfgcfg: clock-controller@13fbf000 {
 			#clock-cells = <1>;
 		};
 
-		vppsys0: clock-controller@14000000 {
-			compatible = "mediatek,mt8188-vppsys0";
+		vppsys0: syscon@14000000 {
+			compatible = "mediatek,mt8188-vppsys0", "syscon";
 			reg = <0 0x14000000 0 0x1000>;
 			#clock-cells = <1>;
 		};
@@ -1797,8 +1797,8 @@ wpesys_vpp0: clock-controller@14e02000 {
 			#clock-cells = <1>;
 		};
 
-		vppsys1: clock-controller@14f00000 {
-			compatible = "mediatek,mt8188-vppsys1";
+		vppsys1: syscon@14f00000 {
+			compatible = "mediatek,mt8188-vppsys1", "syscon";
 			reg = <0 0x14f00000 0 0x1000>;
 			#clock-cells = <1>;
 		};
-- 
2.46.1.824.gd892dcdcdd-goog

[PATCH v2 7/8] arm64: dts: mediatek: mt8188: Move vdec1 power domain under vdec0

[Fei Shao]

The MT8188 video decoder pipeline has two hardware IP blocks: LAT and
Core, which are powered by vdec0 and vdec1 power domains, respectively.

The hardware design includes a dependency between the vdec0 and vdec1
power domains to ensure that Core is powered down before LAT. Without
correctly describing this dependency in DT, the system will fail to
suspend.

As a comparable reference, MT8192 also uses the LAT + Core decoding
pipeline, and it has the correct power domain dependency defined in DT.

Update vdec1 as a sub-domain of vdec0 in MT8188 DT to reflect the
hardware design. Also, use more specific clock names for both power
domains.

Signed-off-by: Fei Shao <fshao@chromium.org>
---

Changes in v2:
Revise commit message.

 arch/arm64/boot/dts/mediatek/mt8188.dtsi | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index 790315c1bdb3..ca50ed20fca0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -1062,20 +1062,22 @@ power-domain@MT8188_POWER_DOMAIN_VPPSYS1 {
 							#power-domain-cells = <0>;
 						};
 
-						power-domain@MT8188_POWER_DOMAIN_VDEC1 {
-							reg = <MT8188_POWER_DOMAIN_VDEC1>;
-							clocks = <&vdecsys CLK_VDEC2_LARB1>;
-							clock-names = "ss-vdec";
-							mediatek,infracfg = <&infracfg_ao>;
-							#power-domain-cells = <0>;
-						};
-
 						power-domain@MT8188_POWER_DOMAIN_VDEC0 {
 							reg = <MT8188_POWER_DOMAIN_VDEC0>;
 							clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>;
-							clock-names = "ss-vdec";
+							clock-names = "ss-vdec1-soc-l1";
 							mediatek,infracfg = <&infracfg_ao>;
-							#power-domain-cells = <0>;
+							#address-cells = <1>;
+							#size-cells = <0>;
+							#power-domain-cells = <1>;
+
+							power-domain@MT8188_POWER_DOMAIN_VDEC1 {
+								reg = <MT8188_POWER_DOMAIN_VDEC1>;
+								clocks = <&vdecsys CLK_VDEC2_LARB1>;
+								clock-names = "ss-vdec2-l1";
+								mediatek,infracfg = <&infracfg_ao>;
+								#power-domain-cells = <0>;
+							};
 						};
 
 						cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE {
-- 
2.46.1.824.gd892dcdcdd-goog

[PATCH v2 8/8] arm64: dts: mediatek: mt8188: Move SPI NOR *-cells properties

[Fei Shao]

Move the #address-cells and #size-cells properties from the board dts
to SoC dtsi to be reused by other boards and avoid duplicated lines.

Signed-off-by: Fei Shao <fshao@chromium.org>
---

Changes in v2:
New patch.

 arch/arm64/boot/dts/mediatek/mt8188-evb.dts | 2 --
 arch/arm64/boot/dts/mediatek/mt8188.dtsi    | 2 ++
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8188-evb.dts b/arch/arm64/boot/dts/mediatek/mt8188-evb.dts
index 68a82b49f7a3..f89835ac36f3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8188-evb.dts
@@ -140,8 +140,6 @@ &mt6359_vrf12_ldo_reg {
 &nor_flash {
 	pinctrl-names = "default";
 	pinctrl-0 = <&nor_pins_default>;
-	#address-cells = <1>;
-	#size-cells = <0>;
 	status = "okay";
 
 	flash@0 {
diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index ca50ed20fca0..e2c6ed816507 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -1618,6 +1618,8 @@ nor_flash: spi@1132c000 {
 			clock-names = "spi", "sf", "axi";
 			assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
 			interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			status = "disabled";
 		};
 
-- 
2.46.1.824.gd892dcdcdd-goog

Re: (subset) [PATCH v2 0/8] MT8188 DT and binding fixes

[AngeloGioacchino Del Regno]

On Tue, 01 Oct 2024 19:27:18 +0800, Fei Shao wrote:
> This series is split from a previous series[*] to focus on few fixes and
> improvements around MediaTek MT8188 device tree and associated bindings,
> and addressed comments and carried tags from the previous series.
> 
> [*]: https://lore.kernel.org/all/20240909111535.528624-1-fshao@chromium.org/
> [v1]: https://lore.kernel.org/all/20240925110044.3678055-1-fshao@chromium.org/
> 
> [...]

Applied to v6.12-next/dts64, thanks!

[5/8] arm64: dts: mediatek: mt8188: Add missing dma-ranges to soc node
      https://git.kernel.org/mediatek/c/ad9d9e15
[6/8] arm64: dts: mediatek: mt8188: Update vppsys node names to syscon
      https://git.kernel.org/mediatek/c/c1134cbf
[7/8] arm64: dts: mediatek: mt8188: Move vdec1 power domain under vdec0
      https://git.kernel.org/mediatek/c/66c466da
[8/8] arm64: dts: mediatek: mt8188: Move SPI NOR *-cells properties
      https://git.kernel.org/mediatek/c/08ea5de5

Cheers,
Angelo

Re: [PATCH v2 0/8] MT8188 DT and binding fixes

[Chen-Yu Tsai]

Hi,

On Tue, Oct 1, 2024 at 7:31 PM Fei Shao <fshao@chromium.org> wrote:
>
> Hi,
>
> This series is split from a previous series[*] to focus on few fixes and
> improvements around MediaTek MT8188 device tree and associated bindings,
> and addressed comments and carried tags from the previous series.
>
> [*]: https://lore.kernel.org/all/20240909111535.528624-1-fshao@chromium.org/
> [v1]: https://lore.kernel.org/all/20240925110044.3678055-1-fshao@chromium.org/
>
> Regards,
> Fei
>
> Changes in v2:
> - new patch to MediaTek jpeg and vcodec bindings
> - new patch to move MT8188 SPI NOR cell properties
> - revise commit message of vdec power domain changes
>
> Fei Shao (8):

>   dt-bindings: power: mediatek: Add another nested power-domain layer

This one ^

>   dt-bindings: PCI: mediatek-gen3: Allow exact number of clocks only

>   dt-bindings: media: mediatek,jpeg: Relax IOMMU max item count
>   dt-bindings: media: mediatek,vcodec: Revise description

and these two ^ have not been picked up, and now v6.13-rc1 has DT
validation errors for MT8188:

/ssd1/wenst/linux/mtk/arch/arm64/boot/dts/mediatek/mt8188-evb.dtb:
syscon@10006000:
power-controller:power-domain@15:power-domain@16:power-domain@29:power-domain@30:
Unevaluated properties are not allowed ('power-domain@31',
'power-domain@32' were unexpected)
    from schema $id:
http://devicetree.org/schemas/mfd/mediatek,mt8195-scpsys.yaml#
/ssd1/wenst/linux/mtk/arch/arm64/boot/dts/mediatek/mt8188-evb.dtb:
power-controller:
power-domain@15:power-domain@16:power-domain@29:power-domain@30:
Unevaluated properties are not allowed ('power-domain@31',
'power-domain@32' were unexpected)
    from schema $id:
http://devicetree.org/schemas/power/mediatek,power-controller.yaml#

/ssd1/wenst/linux/mtk/arch/arm64/boot/dts/mediatek/mt8188-evb.dtb:
jpeg-decoder@1a040000: iommus: [[101, 685], [101, 686], [101, 690],
[101, 691], [101, 692], [101, 693]] is too long
    from schema $id:
http://devicetree.org/schemas/media/mediatek-jpeg-decoder.yaml#


Is there any way we can get them into v6.13 as well?

ChenYu

>   arm64: dts: mediatek: mt8188: Add missing dma-ranges to soc node
>   arm64: dts: mediatek: mt8188: Update vppsys node names to syscon
>   arm64: dts: mediatek: mt8188: Move vdec1 power domain under vdec0
>   arm64: dts: mediatek: mt8188: Move SPI NOR *-cells properties
>
>  .../media/mediatek,vcodec-subdev-decoder.yaml | 100 +++++++++++-------
>  .../bindings/media/mediatek-jpeg-decoder.yaml |   3 +-
>  .../bindings/media/mediatek-jpeg-encoder.yaml |   2 +-
>  .../bindings/pci/mediatek-pcie-gen3.yaml      |   5 +-
>  .../power/mediatek,power-controller.yaml      |   4 +
>  arch/arm64/boot/dts/mediatek/mt8188-evb.dts   |   2 -
>  arch/arm64/boot/dts/mediatek/mt8188.dtsi      |  33 +++---
>  7 files changed, 88 insertions(+), 61 deletions(-)
>
> --
> 2.46.1.824.gd892dcdcdd-goog
>
>

Re: [PATCH v2 0/8] MT8188 DT and binding fixes

[Ulf Hansson]

On Mon, 2 Dec 2024 at 05:24, Chen-Yu Tsai <wenst@chromium.org> wrote:
>
> Hi,
>
> On Tue, Oct 1, 2024 at 7:31 PM Fei Shao <fshao@chromium.org> wrote:
> >
> > Hi,
> >
> > This series is split from a previous series[*] to focus on few fixes and
> > improvements around MediaTek MT8188 device tree and associated bindings,
> > and addressed comments and carried tags from the previous series.
> >
> > [*]: https://lore.kernel.org/all/20240909111535.528624-1-fshao@chromium.org/
> > [v1]: https://lore.kernel.org/all/20240925110044.3678055-1-fshao@chromium.org/
> >
> > Regards,
> > Fei
> >
> > Changes in v2:
> > - new patch to MediaTek jpeg and vcodec bindings
> > - new patch to move MT8188 SPI NOR cell properties
> > - revise commit message of vdec power domain changes
> >
> > Fei Shao (8):
>
> >   dt-bindings: power: mediatek: Add another nested power-domain layer
>
> This one ^
>
> >   dt-bindings: PCI: mediatek-gen3: Allow exact number of clocks only
>
> >   dt-bindings: media: mediatek,jpeg: Relax IOMMU max item count
> >   dt-bindings: media: mediatek,vcodec: Revise description
>
> and these two ^ have not been picked up, and now v6.13-rc1 has DT
> validation errors for MT8188:
>
> /ssd1/wenst/linux/mtk/arch/arm64/boot/dts/mediatek/mt8188-evb.dtb:
> syscon@10006000:
> power-controller:power-domain@15:power-domain@16:power-domain@29:power-domain@30:
> Unevaluated properties are not allowed ('power-domain@31',
> 'power-domain@32' were unexpected)
>     from schema $id:
> http://devicetree.org/schemas/mfd/mediatek,mt8195-scpsys.yaml#
> /ssd1/wenst/linux/mtk/arch/arm64/boot/dts/mediatek/mt8188-evb.dtb:
> power-controller:
> power-domain@15:power-domain@16:power-domain@29:power-domain@30:
> Unevaluated properties are not allowed ('power-domain@31',
> 'power-domain@32' were unexpected)
>     from schema $id:
> http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
>
> /ssd1/wenst/linux/mtk/arch/arm64/boot/dts/mediatek/mt8188-evb.dtb:
> jpeg-decoder@1a040000: iommus: [[101, 685], [101, 686], [101, 690],
> [101, 691], [101, 692], [101, 693]] is too long
>     from schema $id:
> http://devicetree.org/schemas/media/mediatek-jpeg-decoder.yaml#
>
>
> Is there any way we can get them into v6.13 as well?

I don't know why I missed picking up the DT power-domain patch for
v6.13. Sorry for the delay. Anyway, I have taken it now and applied it
as a fix for v6.13-rc[n], thanks!

I assume someone else can help to take the DT media patches.

Kind regards
Uffe


>
> ChenYu
>
> >   arm64: dts: mediatek: mt8188: Add missing dma-ranges to soc node
> >   arm64: dts: mediatek: mt8188: Update vppsys node names to syscon
> >   arm64: dts: mediatek: mt8188: Move vdec1 power domain under vdec0
> >   arm64: dts: mediatek: mt8188: Move SPI NOR *-cells properties
> >
> >  .../media/mediatek,vcodec-subdev-decoder.yaml | 100 +++++++++++-------
> >  .../bindings/media/mediatek-jpeg-decoder.yaml |   3 +-
> >  .../bindings/media/mediatek-jpeg-encoder.yaml |   2 +-
> >  .../bindings/pci/mediatek-pcie-gen3.yaml      |   5 +-
> >  .../power/mediatek,power-controller.yaml      |   4 +
> >  arch/arm64/boot/dts/mediatek/mt8188-evb.dts   |   2 -
> >  arch/arm64/boot/dts/mediatek/mt8188.dtsi      |  33 +++---
> >  7 files changed, 88 insertions(+), 61 deletions(-)
> >
> > --
> > 2.46.1.824.gd892dcdcdd-goog
> >
> >