From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20093C4332F for ; Tue, 29 Nov 2022 19:59:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237144AbiK2T7P (ORCPT ); Tue, 29 Nov 2022 14:59:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44054 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237143AbiK2T7O (ORCPT ); Tue, 29 Nov 2022 14:59:14 -0500 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D0F6827CCD for ; Tue, 29 Nov 2022 11:59:11 -0800 (PST) Received: by mail-lj1-x22e.google.com with SMTP id d3so18544272ljl.1 for ; Tue, 29 Nov 2022 11:59:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=AmnMdhMIbuK+ioOE5wyae0BlwkJ1ypVUOrJTSmxMhn8=; b=dgFKKoEXnI+rRu0A8nhpr9dIH8IXvWuvvzO9BpJZlIKDLavNMwYCmA5eeVuu55peXf OBEEo8a7yZU4vrsEm2H9LcvLtSKiOMsQfsN/a6uiTGDgv3q0PIt4aMkxxCnKKoAfChIf auDiKy0ExYOszLxQT+sUCwlIX3ceL1iohbJ6pSzgtfjHtDXGSHFH2fpD3hCTEOIxBYMS 4zV1sVz31MK4SLt5UeGdBkqc9H9+2U0224CKZI5tRM8f2YxywtP5EMkDcrNDOH3I9c0m /mB/uykcptyuDWlMtDH+4v1WoybyWJkBPKsHxYX3g9h5hz/TugzFJ6dOnu78AiQGAW9W hcKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=AmnMdhMIbuK+ioOE5wyae0BlwkJ1ypVUOrJTSmxMhn8=; b=4LIMs5XTtZsHr9eVvjX+VliAYJayRthok5/jgjKWGhQ3VeS66Yzo6sObXLk3lIUxT2 S1B2a0Zp4VqQOngIKrRPlqBrB+BIvFsTtudUc6WQqYTWJgfVOkuNbnR7zEL3SR39/9Uq b++PgqkKofuAPwREGCPRnASabEl4D2k3a/H5ainXE6ckUiBRvbExi3z47AAD9T5IkbeZ epBh27bZo8iXKhQ/qDqzYkM+hkm4zExaqdavWBjkF4oOPFsmMRHkoDRhGDr5aYrAvMfX 6MtxXCR3G2b8fOjjiits+CQ1RzHg/cEQ0ExTOebnkU1oY1wRz9DSFxUhFCwgUdHoxcUk 13Fw== X-Gm-Message-State: ANoB5pmNURiT2QWSAlBwUEnaMbiswpcB3vMyaqC8B14SG7ULOV+0wsWG sDx3rZL/jbLdQz1mluroejiBAQ== X-Google-Smtp-Source: AA0mqf6eEb4mm4hewBmMNDBECy0NIbeDiiZarC+hAyVtbboS9KaMxc0n1e9xi4MDoQXy+dx122HEUg== X-Received: by 2002:a2e:930f:0:b0:279:a72b:815b with SMTP id e15-20020a2e930f000000b00279a72b815bmr3336062ljh.490.1669751950146; Tue, 29 Nov 2022 11:59:10 -0800 (PST) Received: from ?IPV6:2001:14ba:a085:4d00::8a5? (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id x7-20020ac259c7000000b004b529517d95sm321732lfn.40.2022.11.29.11.59.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 29 Nov 2022 11:59:06 -0800 (PST) Message-ID: Date: Tue, 29 Nov 2022 21:59:05 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [PATCH v2 10/12] arm64: dts: qcom: sm8350: Add display system nodes Content-Language: en-GB To: Robert Foss , Konrad Dybcio Cc: robdclark@gmail.com, quic_abhinavk@quicinc.com, sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, quic_kalyant@quicinc.com, swboyd@chromium.org, angelogioacchino.delregno@somainline.org, loic.poulain@linaro.org, quic_khsieh@quicinc.com, quic_vpolimer@quicinc.com, vkoul@kernel.org, dianders@chromium.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek , vinod.koul@linaro.org, quic_jesszhan@quicinc.com, andersson@kernel.org References: <20221115133105.980877-1-robert.foss@linaro.org> <20221115133105.980877-11-robert.foss@linaro.org> From: Dmitry Baryshkov In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 29/11/2022 18:47, Robert Foss wrote: > On Tue, 15 Nov 2022 at 14:47, Konrad Dybcio wrote: >> >> >> >> On 15/11/2022 14:31, Robert Foss wrote: >>> Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these >>> nodes the display subsystem is configured to support >>> one DSI output. >>> >>> Signed-off-by: Robert Foss >>> --- >>> arch/arm64/boot/dts/qcom/sm8350.dtsi | 197 ++++++++++++++++++++++++++- >>> 1 file changed, 193 insertions(+), 4 deletions(-) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi >>> index 434f8e8b12c1..5c98e5cf5ad0 100644 >>> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi >>> @@ -3,6 +3,7 @@ >>> * Copyright (c) 2020, Linaro Limited >>> */ >>> >>> +#include >>> #include >>> #include >>> #include >>> @@ -2536,14 +2537,201 @@ usb_2_dwc3: usb@a800000 { >>> }; >>> }; >>> >>> + mdss: mdss@ae00000 { >>> + compatible = "qcom,sm8350-mdss"; >>> + reg = <0 0x0ae00000 0 0x1000>; >>> + reg-names = "mdss"; >>> + >>> + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, >>> + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; >>> + interconnect-names = "mdp0-mem", "mdp1-mem"; >>> + >>> + power-domains = <&dispcc MDSS_GDSC>; >>> + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; >>> + >>> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, >>> + <&gcc GCC_DISP_HF_AXI_CLK>, >>> + <&gcc GCC_DISP_SF_AXI_CLK>, >>> + <&dispcc DISP_CC_MDSS_MDP_CLK>; >>> + clock-names = "iface", "bus", "nrt_bus", "core"; >>> + >>> + interrupts = ; >>> + interrupt-controller; >>> + #interrupt-cells = <1>; >>> + >>> + iommus = <&apps_smmu 0x820 0x402>; >>> + >>> + status = "disabled"; >>> + >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + ranges; >>> + >>> + mdss_mdp: display-controller@ae01000 { >>> + compatible = "qcom,sm8350-dpu"; >>> + reg = <0 0x0ae01000 0 0x8f000>, >>> + <0 0x0aeb0000 0 0x2008>; >>> + reg-names = "mdp", "vbif"; >>> + >>> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, >>> + <&gcc GCC_DISP_SF_AXI_CLK>, >>> + <&dispcc DISP_CC_MDSS_AHB_CLK>, >>> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, >>> + <&dispcc DISP_CC_MDSS_MDP_CLK>, >>> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; >>> + clock-names = "bus", >>> + "nrt_bus", >>> + "iface", >>> + "lut", >>> + "core", >>> + "vsync"; >>> + >>> + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; >>> + assigned-clock-rates = <19200000>; >>> + >>> + operating-points-v2 = <&mdp_opp_table>; >>> + power-domains = <&rpmhpd SM8350_MMCX>; >>> + >>> + interrupt-parent = <&mdss>; >>> + interrupts = <0>; >>> + >>> + status = "disabled"; >> It doesn't make sense to disable mdp separately, as mdss is essentially >> useless without it. > > Ack > >> >>> + >>> + ports { >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + >>> + port@0 { >>> + reg = <0>; >>> + dpu_intf1_out: endpoint { >>> + remote-endpoint = <&dsi0_in>; >>> + }; >>> + }; >>> + }; >>> + >>> + mdp_opp_table: opp-table { >>> + compatible = "operating-points-v2"; >>> + >>> + opp-200000000 { >>> + opp-hz = /bits/ 64 <200000000>; >>> + required-opps = <&rpmhpd_opp_low_svs>; >>> + }; >>> + >>> + opp-300000000 { >>> + opp-hz = /bits/ 64 <300000000>; >>> + required-opps = <&rpmhpd_opp_svs>; >>> + }; >>> + >>> + opp-345000000 { >>> + opp-hz = /bits/ 64 <345000000>; >>> + required-opps = <&rpmhpd_opp_svs_l1>; >>> + }; >>> + >>> + opp-460000000 { >>> + opp-hz = /bits/ 64 <460000000>; >>> + required-opps = <&rpmhpd_opp_nom>; >>> + }; >>> + }; >>> + }; >>> + >>> + dsi0: dsi@ae94000 { >>> + compatible = "qcom,mdss-dsi-ctrl"; >>> + reg = <0 0x0ae94000 0 0x400>; >>> + reg-names = "dsi_ctrl"; >>> + >>> + interrupt-parent = <&mdss>; >>> + interrupts = <4>; >>> + >>> + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, >>> + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, >>> + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, >>> + <&dispcc DISP_CC_MDSS_ESC0_CLK>, >>> + <&dispcc DISP_CC_MDSS_AHB_CLK>, >>> + <&gcc GCC_DISP_HF_AXI_CLK>; >>> + clock-names = "byte", >>> + "byte_intf", >>> + "pixel", >>> + "core", >>> + "iface", >>> + "bus"; >>> + >>> + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, >>> + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; >>> + assigned-clock-parents = <&dsi0_phy 0>, >>> + <&dsi0_phy 1>; >>> + >>> + operating-points-v2 = <&dsi_opp_table>; >>> + power-domains = <&rpmhpd SM8350_MMCX>; >>> + >>> + phys = <&dsi0_phy>; >>> + phy-names = "dsi"; >> I think that was dropped as of late. > > Ack > >> >>> + >>> + status = "disabled"; >>> + >>> + ports { >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + >>> + port@0 { >>> + reg = <0>; >>> + dsi0_in: endpoint { >>> + remote-endpoint = <&dpu_intf1_out>; >>> + }; >>> + }; >>> + >>> + port@1 { >>> + reg = <1>; >>> + dsi0_out: endpoint { >>> + }; >>> + }; >>> + }; >>> + }; >>> + >>> + dsi0_phy: phy@ae94400 { >>> + compatible = "qcom,dsi-phy-5nm-8350"; >>> + reg = <0 0x0ae94400 0 0x200>, >>> + <0 0x0ae94600 0 0x280>, >>> + <0 0x0ae94900 0 0x260>; >>> + reg-names = "dsi_phy", >>> + "dsi_phy_lane", >>> + "dsi_pll"; >>> + >>> + #clock-cells = <1>; >>> + #phy-cells = <0>; >>> + >>> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, >>> + <&rpmhcc RPMH_CXO_CLK>; >>> + clock-names = "iface", "ref"; >>> + >>> + status = "disabled"; >>> + >>> + dsi_opp_table: dsi-opp-table { >>> + compatible = "operating-points-v2"; >>> + >>> + opp-187500000 { >>> + opp-hz = /bits/ 64 <187500000>; >>> + required-opps = <&rpmhpd_opp_low_svs>; >>> + }; >>> + >>> + opp-300000000 { >>> + opp-hz = /bits/ 64 <300000000>; >>> + required-opps = <&rpmhpd_opp_svs>; >>> + }; >>> + >>> + opp-358000000 { >>> + opp-hz = /bits/ 64 <358000000>; >>> + required-opps = <&rpmhpd_opp_svs_l1>; >>> + }; >>> + }; >>> + }; >>> + }; >>> + >>> dispcc: clock-controller@af00000 { >>> compatible = "qcom,sm8350-dispcc"; >>> reg = <0 0x0af00000 0 0x10000>; >>> clocks = <&rpmhcc RPMH_CXO_CLK>, >>> - <0>, >>> - <0>, >>> - <0>, >>> - <0>, >>> + <&dsi0_phy 0>, <&dsi0_phy 1>, >>> + <0>, <0>, >>> <0>, >>> <0>; >>> clock-names = "bi_tcxo", >>> @@ -2558,6 +2746,7 @@ dispcc: clock-controller@af00000 { >>> #power-domain-cells = <1>; >>> >>> power-domains = <&rpmhpd SM8350_MMCX>; >>> + required-opps = <&rpmhpd_opp_turbo>; >> A turbo vote is required for it to function? Seems a bit high.. > > Dmitry hit a snag using &rpmhpd_opp_low_svs, so this was a dummy > value. I can't replicate that issue, but am having a conversation with > him off-list about this. > > On my sm8350-hdk board &rpmhpd_opp_low_svs is working fine. Maybe this is related to the bootloader setting up the mode or maybe it was caused by the fact that I have the drm_msm set up as built-in rather than a module. > >> >> Konrad >>> }; >>> >>> adsp: remoteproc@17300000 { -- With best wishes Dmitry