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[146.241.115.66]) by smtp.gmail.com with ESMTPSA id e23-20020adf9bd7000000b0020c5253d8ccsm6694778wrc.24.2022.05.02.02.03.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 May 2022 02:03:36 -0700 (PDT) Message-ID: Subject: Re: [PATCH 1/2] dt-bindings: net: adin: document adi,clk_rcvr_125_en property From: Paolo Abeni To: Nate Drude , netdev@vger.kernel.org Cc: michael.hennerich@analog.com, eran.m@variscite.com, Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org Date: Mon, 02 May 2022 11:03:35 +0200 In-Reply-To: <20220429184432.962738-1-nate.d@variscite.com> References: <20220429184432.962738-1-nate.d@variscite.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.42.4 (3.42.4-2.fc35) MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hello, On Fri, 2022-04-29 at 13:44 -0500, Nate Drude wrote: > Document device tree property to set GE_CLK_RCVR_125_EN (bit 5 of GE_CLK_CFG), > causing the 125 MHz PHY recovered clock (or PLL clock) to be driven at > the GP_CLK pin. > > Signed-off-by: Nate Drude > --- > Documentation/devicetree/bindings/net/adi,adin.yaml | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/net/adi,adin.yaml b/Documentation/devicetree/bindings/net/adi,adin.yaml > index 1129f2b58e98..5fdbbd5aff82 100644 > --- a/Documentation/devicetree/bindings/net/adi,adin.yaml > +++ b/Documentation/devicetree/bindings/net/adi,adin.yaml > @@ -36,6 +36,11 @@ properties: > enum: [ 4, 8, 12, 16, 20, 24 ] > default: 8 > > + adi,clk_rcvr_125_en: > + description: | > + Set GE_CLK_RCVR_125_EN (bit 5 of GE_CLK_CFG), causing the 125 MHz > + PHY recovered clock (or PLL clock) to be driven at the GP_CLK pin. > + > unevaluatedProperties: false > > examples: The recipients list does not contain a few required ones, adding for awareness Rob, Krzysztof and the devicetree ML. If a new version should be required, please include them. Thanks! Paolo