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[188.155.201.27]) by smtp.gmail.com with ESMTPSA id u6-20020a17090626c600b006e74ef7f092sm6549148ejc.176.2022.04.08.01.10.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 08 Apr 2022 01:10:03 -0700 (PDT) Message-ID: Date: Fri, 8 Apr 2022 10:10:02 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH V2 01/15] dt-bindings: cpufreq: mediatek: Add MediaTek CCI property Content-Language: en-US To: Rex-BC Chen , rafael@kernel.org, viresh.kumar@linaro.org, robh+dt@kernel.org, krzk+dt@kernel.org Cc: matthias.bgg@gmail.com, jia-wei.chang@mediatek.com, roger.lu@mediatek.com, hsinyi@google.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Project_Global_Chrome_Upstream_Group@mediatek.com References: <20220408045908.21671-1-rex-bc.chen@mediatek.com> <20220408045908.21671-2-rex-bc.chen@mediatek.com> From: Krzysztof Kozlowski In-Reply-To: <20220408045908.21671-2-rex-bc.chen@mediatek.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 08/04/2022 06:58, Rex-BC Chen wrote: > From: Jia-Wei Chang > > MediaTek Cache Coherent Interconnect (CCI) uses software devfreq module > for scaling clock frequency and adjust voltage. > The phandle could be linked between CPU and MediaTek CCI for some > MediaTek SoCs, like MT8183 and MT8186. > Therefore, we add this property in cpufreq-mediatek.txt. > > Signed-off-by: Jia-Wei Chang > Signed-off-by: Rex-BC Chen > --- > .../devicetree/bindings/cpufreq/cpufreq-mediatek.txt | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt > index b8233ec91d3d..d1b3d430c25c 100644 > --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt > +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt > @@ -20,6 +20,10 @@ Optional properties: > Vsram to fit SoC specific needs. When absent, the voltage scaling > flow is handled by hardware, hence no software "voltage tracking" is > needed. > +- cci: MediaTek Cache Coherent Interconnect uses software devfreq module for scaling > + clock frequency and adjust voltage. You need to describe the type. I am a bit confused whether this is a cci (so cci-control-port property?) or an interconnect (so interconnect property)... It does not look like a generic property, so you need vendor prefix. > + For details, please refer to > + Documentation/devicetree/bindings/devfreq/mtk-cci.yaml Such file does not exist. Best regards, Krzysztof