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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id i19-20020a056512007300b004db508326c0sm2341220lfo.90.2023.03.08.04.35.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 08 Mar 2023 04:35:59 -0800 (PST) Message-ID: Date: Wed, 8 Mar 2023 13:35:57 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v2 3/6] ARM: dts: qcom: sdx65: Add support for PCIe PHY Content-Language: en-US To: Rohit Agarwal , agross@kernel.org, andersson@kernel.org, lee@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mani@kernel.org, lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org References: <1678277993-18836-1-git-send-email-quic_rohiagar@quicinc.com> <1678277993-18836-4-git-send-email-quic_rohiagar@quicinc.com> From: Konrad Dybcio In-Reply-To: <1678277993-18836-4-git-send-email-quic_rohiagar@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 8.03.2023 13:19, Rohit Agarwal wrote: > Add devicetree support for PCIe PHY used in SDX65 platform. This PHY is > used by the PCIe EP controller. > > Signed-off-by: Rohit Agarwal > --- > arch/arm/boot/dts/qcom-sdx65.dtsi | 33 +++++++++++++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi > index 192f9f9..df9d428 100644 > --- a/arch/arm/boot/dts/qcom-sdx65.dtsi > +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi > @@ -293,6 +293,39 @@ > status = "disabled"; > }; > > + pcie_phy: phy@1c06000 { > + compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy"; > + reg = <0x01c06000 0x2000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; No child nodes, please drop this hunk. Konrad > + clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, > + <&gcc GCC_PCIE_CFG_AHB_CLK>, > + <&gcc GCC_PCIE_0_CLKREF_EN>, > + <&gcc GCC_PCIE_RCHNG_PHY_CLK>; > + <&gcc GCC_PCIE_PIPE_CLK>; > + clock-names = "aux", > + "cfg_ahb", > + "ref", > + "rchng", > + "pipe"; > + > + resets = <&gcc GCC_PCIE_PHY_BCR>; > + reset-names = "phy"; > + > + assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; > + assigned-clock-rates = <100000000>; > + > + power-domains = <&gcc PCIE_GDSC>; > + > + #clock-cells = <0>; > + clock-output-names = "pcie_pipe_clk"; > + > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > tcsr_mutex: hwlock@1f40000 { > compatible = "qcom,tcsr-mutex"; > reg = <0x01f40000 0x40000>;