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Mon, 08 Jun 2026 07:02:52 -0700 (PDT) X-Received: by 2002:a05:6a20:2d14:b0:3aa:ec1c:84e5 with SMTP id adf61e73a8af0-3b4cd09ace8mr18854371637.43.1780927371975; Mon, 08 Jun 2026 07:02:51 -0700 (PDT) Received: from [10.219.56.113] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c85df03498csm18010993a12.1.2026.06.08.07.02.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Jun 2026 07:02:51 -0700 (PDT) Message-ID: Date: Mon, 8 Jun 2026 19:32:45 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/6] dt-bindings: iommu: arm,smmu: Document interconnects property To: Dmitry Baryshkov Cc: Konrad Dybcio , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org References: <20260526-smmu_interconnect_addition-v2-0-2a6d8ca30d63@oss.qualcomm.com> <20260526-smmu_interconnect_addition-v2-1-2a6d8ca30d63@oss.qualcomm.com> <1b5ef5b8-c9f2-4eea-8040-22c1d704b529@oss.qualcomm.com> <0ded611e-1932-470c-8e80-9a5e94268583@oss.qualcomm.com> <2roy5rvazzb5p3vl3dyutft635n3acwssqnqvrzqziivh3ebq2@wptxg7exupmr> Content-Language: en-US From: Bibek Kumar Patro In-Reply-To: <2roy5rvazzb5p3vl3dyutft635n3acwssqnqvrzqziivh3ebq2@wptxg7exupmr> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA4MDEzMyBTYWx0ZWRfX3pOI56cmawFH NkxkTWrVb5nhrUzAtES73oLWvKXPNqiEMpZoSedWh2WpyMEr9shBnmsF3/LvbaJLG8MnhG1ghes iPtIEb/lDzKZeNUXiLkOClXQR3E9DBF+03GpTfTiWk8qh5EI0dW4DQJVVcChbuZ9GOO9+p3gToa XerS2Fh1aCQvbx51T3edLYd8SyrpwKAA3BP2QZs6yE8Usk0NNwCjrup02Q8+NFU9WVkHWt6aqh1 nHQzrEJepaGNqUDPRxF4+SWKyDOV+mzoD434Ecm7OQkHT+7LdJ4BVFnDD+x1O0YY+ulQRUbp2Br lFtBAMVpnquHY6tOh3unwK9S9oEBd6EufK45ggDUJ9VBUu3HCc6TfQ9BTe8kCV3EGvSpRyy7Zsz UD85+rszRnfZ5amA22xivT+bHD41YIWY5m6UXWyfWp8Uy5ha/f7qRwD97dEjegKx2Q80l7E55ZN nsZysnC0TBiABPE31+Q== X-Proofpoint-ORIG-GUID: JR6U66bRlzuOLXbHxMwHpbc1yQskTdBG X-Authority-Analysis: v=2.4 cv=ZY4t8MVA c=1 sm=1 tr=0 ts=6a26cb8d cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=NEAV23lmAAAA:8 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=N6J3eu7hh-G8EisLkUMA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: JR6U66bRlzuOLXbHxMwHpbc1yQskTdBG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-08_03,2026-06-05_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 adultscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 spamscore=0 malwarescore=0 bulkscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606080133 On 6/8/2026 7:19 PM, Dmitry Baryshkov wrote: > On Mon, Jun 08, 2026 at 07:14:43PM +0530, Bibek Kumar Patro wrote: >> >> >> On 6/8/2026 3:22 PM, Konrad Dybcio wrote: >>> On 5/26/26 4:42 PM, Bibek Kumar Patro wrote: >>>> Some SoC implementations require a bandwidth vote on an interconnect >>>> path before the SMMU register space is accessible. Add the optional >>>> 'interconnects' property to the binding to allow platform DT nodes >>>> to describe this path. >>>> >>>> Signed-off-by: Bibek Kumar Patro >>>> --- >>>> .../devicetree/bindings/iommu/arm,smmu.yaml | 27 ++++++++++++++++++++++ >>>> 1 file changed, 27 insertions(+) >>>> >>>> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >>>> index 06fb5c8e7547cb7a92823adc2772b94f747376a6..3a677ff1a18fcdf5c0ca9ec8a017d41f9eb5ff09 100644 >>>> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >>>> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >>>> @@ -243,6 +243,13 @@ properties: >>>> minItems: 1 >>>> maxItems: 3 >>>> + interconnects: >>>> + maxItems: 1 >>>> + description: >>>> + Interconnect path to the SMMU register space. Required on SoCs >>>> + where the SMMU registers are only accessible after a bandwidth >>>> + vote has been placed on the interconnect fabric. >>>> + >>>> nvidia,memory-controller: >>>> description: | >>>> A phandle to the memory controller on NVIDIA Tegra186 and later SoCs. >>>> @@ -602,6 +609,26 @@ allOf: >>>> clock-names: false >>>> clocks: false >>>> + - if: >>>> + properties: >>>> + compatible: >>>> + items: >>>> + - enum: >>>> + - qcom,qcs615-smmu-500 >>>> + - qcom,qcs8300-smmu-500 >>>> + - qcom,sa8775p-smmu-500 >>>> + - qcom,sc7280-smmu-500 >>> >>> This is a list of targets that happen to be supported by QLI.. but should >>> this list not contain _all_ Qualcomm SoCs, or at least a much broader range? >>> >>> Perhaps >>> >>> if: properties: compatible: contains: qcom,adreno-smmu >>> >>> ? >>> >> >> As of now platforms where the issues [1] getting reported are added, the >> list will grow. >> > upstream [2]> > > Do you really need to test, which platforms have an interconnect, or can > you predict it by checking the SoC documentation? I strongly belive, the > latter is the case. > Agree, for interconnect path we can surely predict from the SoC documentation, But for the corresponding FLAGS/values (MASTER_GPU_TCU, SLAVE_EBI1), it would need some testing before finalizing the change on corresponding platforms. Thanks, Bibek >> >> [1]: https://github.com/qualcomm-linux/kernel/issues/297 >> [2]: https://lore.kernel.org/all/a437f9f9-3560-40f8-85ea-35433e33c428@oss.qualcomm.com/ >> >>> Konrad >> >