From: Dinh Nguyen <dinguyen@kernel.org>
To: niravkumar.l.rabara@intel.com, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
nirav.rabara@altera.com, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH RESEND] arm64: dts: socfpga: agilex5: add VGIC maintenance interrupt
Date: Thu, 23 Oct 2025 22:29:49 -0500 [thread overview]
Message-ID: <a1e9afd0-b977-42c8-88cb-e82ea89dedaf@kernel.org> (raw)
In-Reply-To: <20250311033601.1940199-1-niravkumar.l.rabara@intel.com>
On 3/10/25 22:36, niravkumar.l.rabara@intel.com wrote:
> From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
>
> Add VGIC maintenance interrupt and interrupt-parent property for
> interrupt controller, required to run Linux in virtualized environment.
>
> Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> ---
> arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index 51c6e19e40b8..75397e84bd2c 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -75,8 +75,11 @@ intc: interrupt-controller@1d000000 {
> #address-cells = <2>;
> #size-cells = <2>;
> interrupt-controller;
> + interrupt-parent = <&intc>;
> #redistributor-regions = <1>;
> redistributor-stride = <0x0 0x20000>;
> + /* VGIC maintenance interrupt */
> + interrupts = <GIC_PPI 25 IRQ_TYPE_LEVEL_HIGH>;
>
> its: msi-controller@1d040000 {
> compatible = "arm,gic-v3-its";
Applied!
Thanks,
Dinh
prev parent reply other threads:[~2025-10-24 3:29 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-11 3:36 [PATCH RESEND] arm64: dts: socfpga: agilex5: add VGIC maintenance interrupt niravkumar.l.rabara
2025-10-24 3:29 ` Dinh Nguyen [this message]
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