* [PATCH v4 1/4] dt-bindings: thermal: r9a08g045-tsu: Document the TSU unit
2025-08-10 12:21 [PATCH v4 0/4] thermal: renesas: Add support for RZ/G3S Claudiu
@ 2025-08-10 12:21 ` Claudiu
2025-08-10 12:21 ` [PATCH v4 2/4] thermal: renesas: rzg3s: Add thermal driver for the Renesas RZ/G3S SoC Claudiu
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Claudiu @ 2025-08-10 12:21 UTC (permalink / raw)
To: rafael, daniel.lezcano, rui.zhang, lukasz.luba, robh, krzk+dt,
conor+dt, geert+renesas, magnus.damm, p.zabel
Cc: claudiu.beznea, linux-pm, devicetree, linux-kernel,
linux-renesas-soc, linux-arm-kernel, niklas.soderlund,
Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
The Renesas RZ/G3S SoC includes a Thermal Sensor Unit (TSU) block designed
to measure the junction temperature. The temperature is measured using
the RZ/G3S ADC, with a dedicated ADC channel directly connected to the TSU.
Add documentation for it.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v4:
- none
Changes in v3:
- none
Changes in v2:
- collected tags
.../thermal/renesas,r9a08g045-tsu.yaml | 93 +++++++++++++++++++
1 file changed, 93 insertions(+)
create mode 100644 Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml
diff --git a/Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml b/Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml
new file mode 100644
index 000000000000..573e2b9d3752
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/thermal/renesas,r9a08g045-tsu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G3S Thermal Sensor Unit
+
+description:
+ The thermal sensor unit (TSU) measures the temperature(Tj) inside
+ the LSI.
+
+maintainers:
+ - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
+
+$ref: thermal-sensor.yaml#
+
+properties:
+ compatible:
+ const: renesas,r9a08g045-tsu
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: TSU module clock
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ items:
+ - description: TSU module reset
+
+ io-channels:
+ items:
+ - description: ADC channel which reports the TSU temperature
+
+ io-channel-names:
+ items:
+ - const: tsu
+
+ "#thermal-sensor-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - power-domains
+ - resets
+ - io-channels
+ - io-channel-names
+ - '#thermal-sensor-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r9a08g045-cpg.h>
+
+ tsu: thermal@10059000 {
+ compatible = "renesas,r9a08g045-tsu";
+ reg = <0x10059000 0x1000>;
+ clocks = <&cpg CPG_MOD R9A08G045_TSU_PCLK>;
+ resets = <&cpg R9A08G045_TSU_PRESETN>;
+ power-domains = <&cpg>;
+ #thermal-sensor-cells = <0>;
+ io-channels = <&adc 8>;
+ io-channel-names = "tsu";
+ };
+
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsu>;
+
+ trips {
+ sensor_crit: sensor-crit {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ target: trip-point {
+ temperature = <100000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+ };
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v4 2/4] thermal: renesas: rzg3s: Add thermal driver for the Renesas RZ/G3S SoC
2025-08-10 12:21 [PATCH v4 0/4] thermal: renesas: Add support for RZ/G3S Claudiu
2025-08-10 12:21 ` [PATCH v4 1/4] dt-bindings: thermal: r9a08g045-tsu: Document the TSU unit Claudiu
@ 2025-08-10 12:21 ` Claudiu
2025-08-10 12:21 ` [PATCH v4 3/4] arm64: dts: renesas: r9a08g045: Add TSU node Claudiu
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Claudiu @ 2025-08-10 12:21 UTC (permalink / raw)
To: rafael, daniel.lezcano, rui.zhang, lukasz.luba, robh, krzk+dt,
conor+dt, geert+renesas, magnus.damm, p.zabel
Cc: claudiu.beznea, linux-pm, devicetree, linux-kernel,
linux-renesas-soc, linux-arm-kernel, niklas.soderlund,
Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
The Renesas RZ/G3S SoC features a Thermal Sensor Unit (TSU) that reports
the junction temperature. The temperature is reported through a dedicated
ADC channel. Add a driver for the Renesas RZ/G3S TSU.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v4:
- dropped devres_group_id along with its code, as now the issue is fixed
by [3] which was integrated
- in rzg3s_thermal_get_temp():
-- moved val, ret declaration in for block as it is used only there
-- dropped ret = 0 and return 0 directly instead
-- use div_s64()
- added HW manual revision in citations
- s/mili/milli/g
- dropped pm_runtime_mark_last_busy() as now it is embedded in
pm_runtime_put_autosuspend()
- changed driver name into "rzg3s-thermal"
Changes in v3:
- drop the runtime resume/suspend from rzg3s_thermal_get_temp(); this
is not needed as the temperature is read with ADC
- opened the devres group id in rzg3s_thermal_probe() and rename
previsouly rzg3s_thermal_probe() to rzg3s_thermal_probe_helper(), to
have simpler code; this approach was suggested by Jonathan in [1];
as there is no positive feedback for the generic solution [2] this
looks currently the best approach
[1] https://lore.kernel.org/all/20250224120608.1769039-2-claudiu.beznea.uj@bp.renesas.com
[2] https://lore.kernel.org/all/20250215130849.227812-1-claudiu.beznea.uj@bp.renesas.com
[3] https://lore.kernel.org/all/20250703112708.1621607-1-claudiu.beznea.uj@bp.renesas.com/
Changes in v2:
- use a devres group for the devm resources obtained though this
driver to avoid issue described in [1]; with this dropped the
following calls:
-- thermal_add_hwmon_sysfs(priv->tz);
-- thermal_of_zone_register(priv->tz);
-- pm_runtime_enable(priv->dev);
and use devm variants
- used signed variables for temperature computation
- convert to mili degree Celsius before applying the computation formula
to avoid losing precision
[1] https://lore.kernel.org/all/20250215130849.227812-1-claudiu.beznea.uj@bp.renesas.com/
MAINTAINERS | 7 +
drivers/thermal/renesas/Kconfig | 8 +
drivers/thermal/renesas/Makefile | 1 +
drivers/thermal/renesas/rzg3s_thermal.c | 272 ++++++++++++++++++++++++
4 files changed, 288 insertions(+)
create mode 100644 drivers/thermal/renesas/rzg3s_thermal.c
diff --git a/MAINTAINERS b/MAINTAINERS
index e80494f93dbc..bc63bcd0e670 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -21544,6 +21544,13 @@ S: Maintained
F: Documentation/devicetree/bindings/iio/potentiometer/renesas,x9250.yaml
F: drivers/iio/potentiometer/x9250.c
+RENESAS RZ/G3S THERMAL SENSOR UNIT DRIVER
+M: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
+L: linux-pm@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml
+F: drivers/thermal/renesas/rzg3s_thermal.c
+
RESET CONTROLLER FRAMEWORK
M: Philipp Zabel <p.zabel@pengutronix.de>
S: Maintained
diff --git a/drivers/thermal/renesas/Kconfig b/drivers/thermal/renesas/Kconfig
index dcf5fc5ae08e..566478797095 100644
--- a/drivers/thermal/renesas/Kconfig
+++ b/drivers/thermal/renesas/Kconfig
@@ -26,3 +26,11 @@ config RZG2L_THERMAL
help
Enable this to plug the RZ/G2L thermal sensor driver into the Linux
thermal framework.
+
+config RZG3S_THERMAL
+ tristate "Renesas RZ/G3S thermal driver"
+ depends on ARCH_R9A08G045 || COMPILE_TEST
+ depends on OF && IIO && RZG2L_ADC
+ help
+ Enable this to plug the RZ/G3S thermal sensor driver into the Linux
+ thermal framework.
diff --git a/drivers/thermal/renesas/Makefile b/drivers/thermal/renesas/Makefile
index bf9cb3cb94d6..1feb5ab78827 100644
--- a/drivers/thermal/renesas/Makefile
+++ b/drivers/thermal/renesas/Makefile
@@ -3,3 +3,4 @@
obj-$(CONFIG_RCAR_GEN3_THERMAL) += rcar_gen3_thermal.o
obj-$(CONFIG_RCAR_THERMAL) += rcar_thermal.o
obj-$(CONFIG_RZG2L_THERMAL) += rzg2l_thermal.o
+obj-$(CONFIG_RZG3S_THERMAL) += rzg3s_thermal.o
diff --git a/drivers/thermal/renesas/rzg3s_thermal.c b/drivers/thermal/renesas/rzg3s_thermal.c
new file mode 100644
index 000000000000..e25e36c99a88
--- /dev/null
+++ b/drivers/thermal/renesas/rzg3s_thermal.c
@@ -0,0 +1,272 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G3S TSU Thermal Sensor Driver
+ *
+ * Copyright (C) 2024 Renesas Electronics Corporation
+ */
+
+#include <linux/bitfield.h>
+#include <linux/delay.h>
+#include <linux/iio/consumer.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/thermal.h>
+#include <linux/units.h>
+
+#include "../thermal_hwmon.h"
+
+#define TSU_SM 0x0
+#define TSU_SM_EN BIT(0)
+#define TSU_SM_OE BIT(1)
+#define OTPTSUTRIM_REG(n) (0x18 + (n) * 0x4)
+#define OTPTSUTRIM_EN_MASK BIT(31)
+#define OTPTSUTRIM_MASK GENMASK(11, 0)
+
+#define TSU_READ_STEPS 8
+
+/* Default calibration values, if FUSE values are missing. */
+#define SW_CALIB0_VAL 1297
+#define SW_CALIB1_VAL 751
+
+#define MCELSIUS(temp) ((temp) * MILLIDEGREE_PER_DEGREE)
+
+/**
+ * struct rzg3s_thermal_priv - RZ/G3S thermal private data structure
+ * @base: TSU base address
+ * @dev: device pointer
+ * @tz: thermal zone pointer
+ * @rstc: reset control
+ * @channel: IIO channel to read the TSU
+ * @mode: current device mode
+ * @calib0: calibration value
+ * @calib1: calibration value
+ */
+struct rzg3s_thermal_priv {
+ void __iomem *base;
+ struct device *dev;
+ struct thermal_zone_device *tz;
+ struct reset_control *rstc;
+ struct iio_channel *channel;
+ enum thermal_device_mode mode;
+ u16 calib0;
+ u16 calib1;
+};
+
+static int rzg3s_thermal_get_temp(struct thermal_zone_device *tz, int *temp)
+{
+ struct rzg3s_thermal_priv *priv = thermal_zone_device_priv(tz);
+ int ts_code_ave = 0;
+
+ if (priv->mode != THERMAL_DEVICE_ENABLED)
+ return -EAGAIN;
+
+ for (u8 i = 0; i < TSU_READ_STEPS; i++) {
+ int ret, val;
+
+ ret = iio_read_channel_raw(priv->channel, &val);
+ if (ret < 0)
+ return ret;
+
+ ts_code_ave += val;
+ /*
+ * According to the HW manual (Rev.1.10, section 40.4.4 Procedure for Measuring
+ * the Temperature) we need to wait here at leat 3us.
+ */
+ usleep_range(5, 10);
+ }
+
+ ts_code_ave = DIV_ROUND_CLOSEST(MCELSIUS(ts_code_ave), TSU_READ_STEPS);
+
+ /*
+ * According to the HW manual (Rev.1.10, section 40.4.4 Procedure for Measuring the
+ * Temperature) the computation formula is as follows:
+ *
+ * Tj = (ts_code_ave - priv->calib1) * 165 / (priv->calib0 - priv->calib1) - 40
+ *
+ * Convert everything to milli Celsius before applying the formula to avoid
+ * losing precision.
+ */
+
+ *temp = div_s64((s64)(ts_code_ave - MCELSIUS(priv->calib1)) * MCELSIUS(165),
+ MCELSIUS(priv->calib0 - priv->calib1)) - MCELSIUS(40);
+
+ /* Report it in milli degrees Celsius and round it up to 0.5 degrees Celsius. */
+ *temp = roundup(*temp, 500);
+
+ return 0;
+}
+
+static void rzg3s_thermal_set_mode(struct rzg3s_thermal_priv *priv,
+ enum thermal_device_mode mode)
+{
+ struct device *dev = priv->dev;
+ int ret;
+
+ ret = pm_runtime_resume_and_get(dev);
+ if (ret)
+ return;
+
+ if (mode == THERMAL_DEVICE_DISABLED) {
+ writel(0, priv->base + TSU_SM);
+ } else {
+ writel(TSU_SM_EN, priv->base + TSU_SM);
+ /*
+ * According to the HW manual (Rev.1.10, section 40.4.1 Procedure for
+ * Starting the TSU) we need to wait here 30us or more.
+ */
+ usleep_range(30, 40);
+
+ writel(TSU_SM_OE | TSU_SM_EN, priv->base + TSU_SM);
+ /*
+ * According to the HW manual (Rev.1.10, section 40.4.1 Procedure for
+ * Starting the TSU) we need to wait here 50us or more.
+ */
+ usleep_range(50, 60);
+ }
+
+ pm_runtime_put_autosuspend(dev);
+}
+
+static int rzg3s_thermal_change_mode(struct thermal_zone_device *tz,
+ enum thermal_device_mode mode)
+{
+ struct rzg3s_thermal_priv *priv = thermal_zone_device_priv(tz);
+
+ if (priv->mode == mode)
+ return 0;
+
+ rzg3s_thermal_set_mode(priv, mode);
+ priv->mode = mode;
+
+ return 0;
+}
+
+static const struct thermal_zone_device_ops rzg3s_tz_of_ops = {
+ .get_temp = rzg3s_thermal_get_temp,
+ .change_mode = rzg3s_thermal_change_mode,
+};
+
+static int rzg3s_thermal_read_calib(struct rzg3s_thermal_priv *priv)
+{
+ struct device *dev = priv->dev;
+ u32 val;
+ int ret;
+
+ ret = pm_runtime_resume_and_get(dev);
+ if (ret)
+ return ret;
+
+ val = readl(priv->base + OTPTSUTRIM_REG(0));
+ if (val & OTPTSUTRIM_EN_MASK)
+ priv->calib0 = FIELD_GET(OTPTSUTRIM_MASK, val);
+ else
+ priv->calib0 = SW_CALIB0_VAL;
+
+ val = readl(priv->base + OTPTSUTRIM_REG(1));
+ if (val & OTPTSUTRIM_EN_MASK)
+ priv->calib1 = FIELD_GET(OTPTSUTRIM_MASK, val);
+ else
+ priv->calib1 = SW_CALIB1_VAL;
+
+ pm_runtime_put_autosuspend(dev);
+
+ return 0;
+}
+
+static int rzg3s_thermal_probe(struct platform_device *pdev)
+{
+ struct rzg3s_thermal_priv *priv;
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ priv->channel = devm_iio_channel_get(dev, "tsu");
+ if (IS_ERR(priv->channel))
+ return dev_err_probe(dev, PTR_ERR(priv->channel), "Failed to get IIO channel!\n");
+
+ priv->rstc = devm_reset_control_get_exclusive_deasserted(dev, NULL);
+ if (IS_ERR(priv->rstc))
+ return dev_err_probe(dev, PTR_ERR(priv->rstc), "Failed to get reset!\n");
+
+ priv->dev = dev;
+ priv->mode = THERMAL_DEVICE_DISABLED;
+ platform_set_drvdata(pdev, priv);
+
+ pm_runtime_set_autosuspend_delay(dev, 300);
+ pm_runtime_use_autosuspend(dev);
+ ret = devm_pm_runtime_enable(dev);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to enable runtime PM!\n");
+
+ ret = rzg3s_thermal_read_calib(priv);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to read calibration data!\n");
+
+ priv->tz = devm_thermal_of_zone_register(dev, 0, priv, &rzg3s_tz_of_ops);
+ if (IS_ERR(priv->tz))
+ return dev_err_probe(dev, PTR_ERR(priv->tz), "Failed to register thermal zone!\n");
+
+ ret = devm_thermal_add_hwmon_sysfs(dev, priv->tz);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to add hwmon sysfs!\n");
+
+ return 0;
+}
+
+static int rzg3s_thermal_suspend(struct device *dev)
+{
+ struct rzg3s_thermal_priv *priv = dev_get_drvdata(dev);
+
+ rzg3s_thermal_set_mode(priv, THERMAL_DEVICE_DISABLED);
+
+ return reset_control_assert(priv->rstc);
+}
+
+static int rzg3s_thermal_resume(struct device *dev)
+{
+ struct rzg3s_thermal_priv *priv = dev_get_drvdata(dev);
+ int ret;
+
+ ret = reset_control_deassert(priv->rstc);
+ if (ret)
+ return ret;
+
+ if (priv->mode != THERMAL_DEVICE_DISABLED)
+ rzg3s_thermal_set_mode(priv, priv->mode);
+
+ return 0;
+}
+
+static const struct dev_pm_ops rzg3s_thermal_pm_ops = {
+ SYSTEM_SLEEP_PM_OPS(rzg3s_thermal_suspend, rzg3s_thermal_resume)
+};
+
+static const struct of_device_id rzg3s_thermal_dt_ids[] = {
+ { .compatible = "renesas,r9a08g045-tsu" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rzg3s_thermal_dt_ids);
+
+static struct platform_driver rzg3s_thermal_driver = {
+ .driver = {
+ .name = "rzg3s-thermal",
+ .of_match_table = rzg3s_thermal_dt_ids,
+ .pm = pm_ptr(&rzg3s_thermal_pm_ops),
+ },
+ .probe = rzg3s_thermal_probe,
+};
+module_platform_driver(rzg3s_thermal_driver);
+
+MODULE_DESCRIPTION("Renesas RZ/G3S Thermal Sensor Unit Driver");
+MODULE_AUTHOR("Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>");
+MODULE_LICENSE("GPL");
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v4 3/4] arm64: dts: renesas: r9a08g045: Add TSU node
2025-08-10 12:21 [PATCH v4 0/4] thermal: renesas: Add support for RZ/G3S Claudiu
2025-08-10 12:21 ` [PATCH v4 1/4] dt-bindings: thermal: r9a08g045-tsu: Document the TSU unit Claudiu
2025-08-10 12:21 ` [PATCH v4 2/4] thermal: renesas: rzg3s: Add thermal driver for the Renesas RZ/G3S SoC Claudiu
@ 2025-08-10 12:21 ` Claudiu
2025-08-10 12:21 ` [PATCH v4 4/4] arm64: defconfig: Enable RZ/G3S thermal Claudiu
2025-08-28 8:41 ` [PATCH v4 0/4] thermal: renesas: Add support for RZ/G3S Wolfram Sang
4 siblings, 0 replies; 7+ messages in thread
From: Claudiu @ 2025-08-10 12:21 UTC (permalink / raw)
To: rafael, daniel.lezcano, rui.zhang, lukasz.luba, robh, krzk+dt,
conor+dt, geert+renesas, magnus.damm, p.zabel
Cc: claudiu.beznea, linux-pm, devicetree, linux-kernel,
linux-renesas-soc, linux-arm-kernel, niklas.soderlund,
Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Add TSU node along with thermal zones and keep it enabled in the SoC DTSI.
The temperature reported by the TSU can only be read through channel 8 of
the ADC. Therefore, enable the ADC by default.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v4:
- none
Changes in v3:
- none
Changes in v2:
- collected Geert's tag
- adjusted the trip points temperature as suggested in the review
process
- added cpu_alert1 passive trip point as suggested in the review
process; along with it changed the trip point nodes and label names
Hi, Geert,
I kept your Rb tag. Please let me know if it should be dropped.
Thank you,
Claudiu
arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 49 ++++++++++++++++++-
.../boot/dts/renesas/rzg3s-smarc-som.dtsi | 4 --
2 files changed, 48 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index 0364f89776e6..3f56fff7d9b0 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -233,7 +233,6 @@ adc: adc@10058000 {
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
- status = "disabled";
channel@0 {
reg = <0>;
@@ -272,6 +271,17 @@ channel@8 {
};
};
+ tsu: thermal@10059000 {
+ compatible = "renesas,r9a08g045-tsu";
+ reg = <0 0x10059000 0 0x1000>;
+ clocks = <&cpg CPG_MOD R9A08G045_TSU_PCLK>;
+ resets = <&cpg R9A08G045_TSU_PRESETN>;
+ power-domains = <&cpg>;
+ #thermal-sensor-cells = <0>;
+ io-channels = <&adc 8>;
+ io-channel-names = "tsu";
+ };
+
vbattb: clock-controller@1005c000 {
compatible = "renesas,r9a08g045-vbattb";
reg = <0 0x1005c000 0 0x1000>;
@@ -717,6 +727,43 @@ timer {
"hyp-virt";
};
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsu>;
+ sustainable-power = <423>;
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device = <&cpu0 0 2>;
+ contribution = <1024>;
+ };
+ };
+
+ trips {
+ cpu_crit: cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+
+ cpu_alert1: trip-point1 {
+ temperature = <90000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ cpu_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+ };
+
vbattb_xtal: vbattb-xtal {
compatible = "fixed-clock";
#clock-cells = <0>;
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
index 39845faec894..6f25ab617982 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
@@ -84,10 +84,6 @@ x3_clk: x3-clock {
};
};
-&adc {
- status = "okay";
-};
-
#if SW_CONFIG3 == SW_ON
ð0 {
pinctrl-0 = <ð0_pins>;
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v4 4/4] arm64: defconfig: Enable RZ/G3S thermal
2025-08-10 12:21 [PATCH v4 0/4] thermal: renesas: Add support for RZ/G3S Claudiu
` (2 preceding siblings ...)
2025-08-10 12:21 ` [PATCH v4 3/4] arm64: dts: renesas: r9a08g045: Add TSU node Claudiu
@ 2025-08-10 12:21 ` Claudiu
2025-08-28 8:41 ` [PATCH v4 0/4] thermal: renesas: Add support for RZ/G3S Wolfram Sang
4 siblings, 0 replies; 7+ messages in thread
From: Claudiu @ 2025-08-10 12:21 UTC (permalink / raw)
To: rafael, daniel.lezcano, rui.zhang, lukasz.luba, robh, krzk+dt,
conor+dt, geert+renesas, magnus.damm, p.zabel
Cc: claudiu.beznea, linux-pm, devicetree, linux-kernel,
linux-renesas-soc, linux-arm-kernel, niklas.soderlund,
Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Enable the CONFIG_RZG3S_THERMAL flag for the RZ/G3S SoC.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v4:
- none
Changes in v3:
- none
Changes in v2:
- collected tags
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 58f87d09366c..540e85a0c676 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -728,6 +728,7 @@ CONFIG_ROCKCHIP_THERMAL=m
CONFIG_RCAR_THERMAL=y
CONFIG_RCAR_GEN3_THERMAL=y
CONFIG_RZG2L_THERMAL=y
+CONFIG_RZG3S_THERMAL=m
CONFIG_ARMADA_THERMAL=y
CONFIG_MTK_THERMAL=m
CONFIG_MTK_LVTS_THERMAL=m
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v4 0/4] thermal: renesas: Add support for RZ/G3S
2025-08-10 12:21 [PATCH v4 0/4] thermal: renesas: Add support for RZ/G3S Claudiu
` (3 preceding siblings ...)
2025-08-10 12:21 ` [PATCH v4 4/4] arm64: defconfig: Enable RZ/G3S thermal Claudiu
@ 2025-08-28 8:41 ` Wolfram Sang
2025-08-28 18:53 ` claudiu beznea
4 siblings, 1 reply; 7+ messages in thread
From: Wolfram Sang @ 2025-08-28 8:41 UTC (permalink / raw)
To: Claudiu
Cc: rafael, daniel.lezcano, rui.zhang, lukasz.luba, robh, krzk+dt,
conor+dt, geert+renesas, magnus.damm, p.zabel, linux-pm,
devicetree, linux-kernel, linux-renesas-soc, linux-arm-kernel,
niklas.soderlund, Claudiu Beznea
On Sun, Aug 10, 2025 at 03:21:21PM +0300, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Hi,
>
> This series adds thermal support for the Renesas RZ/G3S SoC.
>
> Series is organized as follows:
> - patches 1-2/4: add thermal support for RZ/G3S
> - patches 3-4/5: add device tree support
>
> Merge strategy, if any:
> - patches 1-2/4 can go through the thermal tree
> - patches 3-4/4 can go through the Renesas tree
Series applies fine; I can read the temp (36°) which increases
reasonably over time (40°).
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v4 0/4] thermal: renesas: Add support for RZ/G3S
2025-08-28 8:41 ` [PATCH v4 0/4] thermal: renesas: Add support for RZ/G3S Wolfram Sang
@ 2025-08-28 18:53 ` claudiu beznea
0 siblings, 0 replies; 7+ messages in thread
From: claudiu beznea @ 2025-08-28 18:53 UTC (permalink / raw)
To: Wolfram Sang
Cc: rafael, daniel.lezcano, rui.zhang, lukasz.luba, robh, krzk+dt,
conor+dt, geert+renesas, magnus.damm, p.zabel, linux-pm,
devicetree, linux-kernel, linux-renesas-soc, linux-arm-kernel,
niklas.soderlund, Claudiu Beznea
Hi, Wolfram,
On 8/28/25 11:41, Wolfram Sang wrote:
> On Sun, Aug 10, 2025 at 03:21:21PM +0300, Claudiu wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> Hi,
>>
>> This series adds thermal support for the Renesas RZ/G3S SoC.
>>
>> Series is organized as follows:
>> - patches 1-2/4: add thermal support for RZ/G3S
>> - patches 3-4/5: add device tree support
>>
>> Merge strategy, if any:
>> - patches 1-2/4 can go through the thermal tree
>> - patches 3-4/4 can go through the Renesas tree
>
> Series applies fine; I can read the temp (36°) which increases
> reasonably over time (40°).
>
> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Thank you for checking it,
Claudiu
^ permalink raw reply [flat|nested] 7+ messages in thread