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AJvYcCVNFblsz9NOpC8SUpTjYIPzmRYiKd7s+YemX+RTBOkMahp2JJKc/22UQ2eknTKYV8rJh07I/jVE+5RsbIuZ2yE7fUWb/jWSfm0giQ== X-Gm-Message-State: AOJu0YyPoJ8VdBit63KumRYPuHrVEPdyRjHtmn+WRxyTY+DDX9qIFbDv m8gfrvpnB2wYFCV8EJT9nUkdZImAnFjaFEqap2BmElefdNJKxSGLQULSAf0fveI= X-Google-Smtp-Source: AGHT+IH1iDyN2tzMwmReFoBP6SQJJq7Vr+GdTMJIqYq1jnekXccdpbNnTxJEdOIrHFh2U6cMKFP2kA== X-Received: by 2002:a05:6358:7f0e:b0:176:92d1:568f with SMTP id p14-20020a0563587f0e00b0017692d1568fmr9886249rwn.18.1708270401977; Sun, 18 Feb 2024 07:33:21 -0800 (PST) Received: from [100.64.0.1] ([170.85.8.176]) by smtp.gmail.com with ESMTPSA id x19-20020ac87a93000000b0042de2e2195fsm1719582qtr.26.2024.02.18.07.33.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 18 Feb 2024 07:33:21 -0800 (PST) Message-ID: Date: Sun, 18 Feb 2024 09:33:20 -0600 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 5/6] dt-bindings: cache: Add SiFive Private L2 Cache controller Content-Language: en-US To: Krzysztof Kozlowski , Will Deacon , Mark Rutland , Eric Lin , Conor Dooley Cc: Palmer Dabbelt , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Paul Walmsley , linux-riscv@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org References: <20240216000837.1868917-1-samuel.holland@sifive.com> <20240216000837.1868917-6-samuel.holland@sifive.com> <7d7fc53f-1b5d-4f1f-a53f-f0863a79a79c@linaro.org> From: Samuel Holland In-Reply-To: <7d7fc53f-1b5d-4f1f-a53f-f0863a79a79c@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi Krzysztof, On 2024-02-17 3:12 AM, Krzysztof Kozlowski wrote: > On 16/02/2024 01:08, Samuel Holland wrote: >> From: Eric Lin >> >> Add YAML DT binding documentation for the SiFive Private L2 Cache >> controller. Some functionality and the corresponding register bits were >> removed in the sifive,pl2cache1 version of the hardware, which creates >> the unusual situation where the newer hardware's compatible string is >> the fallback for the older one. >> >> Signed-off-by: Eric Lin >> Co-developed-by: Samuel Holland >> Signed-off-by: Samuel Holland >> --- >> >> Changes in v1: >> - Add back select: clause to binding >> - Make sifive,pl2cache1 the fallback for sifive,pl2cache0 >> - Fix the order of the reg property declaration >> - Document the sifive,perfmon-counters property > > This is no v1. Please implement entire feedback from previous v2, v3 or > whatever it was and reference old posting or continue the numbering. The old posting is referenced in the cover letter: This series is a follow-up to Eric Lin's series "[PATCH v2 0/3] Add SiFive Private L2 cache and PMU driver": https://lore.kernel.org/linux-riscv/20230720135125.21240-1-eric.lin@sifive.com/ So these changes include implementation of the feedback from that v2. Regards, Samuel