[PATCH 0/5] arm64: DT binding/PMU updates

[PATCH 0/5] arm64: DT binding/PMU updates

[Robin Murphy]

Hi all,

Here's another bunch of PMU-related updates I've been accruing lately.
Patch #1 is rebased on Thierry's patch already adding the Cortex-A78
compatible so probably wants to go via Rob to avoid further conflicts.

Thanks,
Robin.

Robin Murphy (5):
  dt-bindings: arm: Catch up with Cortex/Neoverse CPUs again
  arm64: perf: Simplify registration boilerplate
  arm64: perf: Support new DT compatibles
  dt-bindings: perf: Convert Arm DSU to schema
  dt-bindings: perf: Add compatible for Arm DSU-110

 .../devicetree/bindings/arm/arm-dsu-pmu.txt   | 27 --------
 .../devicetree/bindings/arm/cpus.yaml         |  6 ++
 .../devicetree/bindings/arm/pmu.yaml          |  6 ++
 .../devicetree/bindings/perf/arm,dsu-pmu.yaml | 45 ++++++++++++
 arch/arm64/kernel/perf_event.c                | 68 +++++++++++++------
 5 files changed, 104 insertions(+), 48 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
 create mode 100644 Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml

-- 
2.28.0.dirty

[PATCH 1/5] dt-bindings: arm: Catch up with Cortex/Neoverse CPUs again

[Robin Murphy]

Add bindings for the 2020 and 2021 cohorts of Cortex-A and Neoverse
CPUs, now featuring their Cortex-X cousins as well.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
 Documentation/devicetree/bindings/arm/cpus.yaml | 6 ++++++
 Documentation/devicetree/bindings/arm/pmu.yaml  | 6 ++++++
 2 files changed, 12 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index 452bfd1d4ecc..e81dfb81230a 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -138,6 +138,8 @@ properties:
       - arm,cortex-a76
       - arm,cortex-a77
       - arm,cortex-a78
+      - arm,cortex-a510
+      - arm,cortex-a710
       - arm,cortex-m0
       - arm,cortex-m0+
       - arm,cortex-m1
@@ -146,8 +148,12 @@ properties:
       - arm,cortex-r4
       - arm,cortex-r5
       - arm,cortex-r7
+      - arm,cortex-x1
+      - arm,cortex-x2
       - arm,neoverse-e1
       - arm,neoverse-n1
+      - arm,neoverse-n2
+      - arm,neoverse-v1
       - brcm,brahma-b15
       - brcm,brahma-b53
       - brcm,vulcan
diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml
index e17ac049e890..541a483ec8d7 100644
--- a/Documentation/devicetree/bindings/arm/pmu.yaml
+++ b/Documentation/devicetree/bindings/arm/pmu.yaml
@@ -44,8 +44,14 @@ properties:
           - arm,cortex-a76-pmu
           - arm,cortex-a77-pmu
           - arm,cortex-a78-pmu
+          - arm,cortex-a510-pmu
+          - arm,cortex-a710-pmu
+          - arm,cortex-x1-pmu
+          - arm,cortex-x2-pmu
           - arm,neoverse-e1-pmu
           - arm,neoverse-n1-pmu
+          - arm,neoverse-n2-pmu
+          - arm,neoverse-v1-pmu
           - brcm,vulcan-pmu
           - cavium,thunder-pmu
           - qcom,krait-pmu
-- 
2.28.0.dirty

Re: [PATCH 1/5] dt-bindings: arm: Catch up with Cortex/Neoverse CPUs again

[Rob Herring]

On Tue, 07 Dec 2021 18:20:39 +0000, Robin Murphy wrote:
> Add bindings for the 2020 and 2021 cohorts of Cortex-A and Neoverse
> CPUs, now featuring their Cortex-X cousins as well.
> 
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
>  Documentation/devicetree/bindings/arm/cpus.yaml | 6 ++++++
>  Documentation/devicetree/bindings/arm/pmu.yaml  | 6 ++++++
>  2 files changed, 12 insertions(+)
> 

Applied, thanks!

[PATCH 2/5] arm64: perf: Simplify registration boilerplate

[Robin Murphy]

The arm_pmu framework requires map_event to be non-NULL, so let
armv8_pmu_init() treat NULL as a default value for the generic PMUv3
event map and simplify the boilerplate in the callers a bit.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
 arch/arm64/kernel/perf_event.c | 32 +++++++++++---------------------
 1 file changed, 11 insertions(+), 21 deletions(-)

diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index b4044469527e..57720372da62 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -1128,7 +1128,7 @@ static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name,
 	cpu_pmu->filter_match		= armv8pmu_filter_match;
 
 	cpu_pmu->name			= name;
-	cpu_pmu->map_event		= map_event;
+	cpu_pmu->map_event		= map_event ?: armv8_pmuv3_map_event;
 	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = events ?
 			events : &armv8_pmuv3_events_attr_group;
 	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = format ?
@@ -1147,14 +1147,12 @@ static int armv8_pmu_init_nogroups(struct arm_pmu *cpu_pmu, char *name,
 
 static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
 {
-	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_pmuv3",
-				       armv8_pmuv3_map_event);
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_pmuv3", NULL);
 }
 
 static int armv8_a34_pmu_init(struct arm_pmu *cpu_pmu)
 {
-	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a34",
-				       armv8_pmuv3_map_event);
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a34", NULL);
 }
 
 static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu)
@@ -1171,8 +1169,7 @@ static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
 
 static int armv8_a55_pmu_init(struct arm_pmu *cpu_pmu)
 {
-	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a55",
-				       armv8_pmuv3_map_event);
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a55", NULL);
 }
 
 static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
@@ -1183,8 +1180,7 @@ static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
 
 static int armv8_a65_pmu_init(struct arm_pmu *cpu_pmu)
 {
-	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a65",
-				       armv8_pmuv3_map_event);
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a65", NULL);
 }
 
 static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
@@ -1201,38 +1197,32 @@ static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)
 
 static int armv8_a75_pmu_init(struct arm_pmu *cpu_pmu)
 {
-	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a75",
-				       armv8_pmuv3_map_event);
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a75", NULL);
 }
 
 static int armv8_a76_pmu_init(struct arm_pmu *cpu_pmu)
 {
-	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a76",
-				       armv8_pmuv3_map_event);
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a76", NULL);
 }
 
 static int armv8_a77_pmu_init(struct arm_pmu *cpu_pmu)
 {
-	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a77",
-				       armv8_pmuv3_map_event);
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a77", NULL);
 }
 
 static int armv8_a78_pmu_init(struct arm_pmu *cpu_pmu)
 {
-	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a78",
-				       armv8_pmuv3_map_event);
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a78", NULL);
 }
 
 static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu)
 {
-	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_e1",
-				       armv8_pmuv3_map_event);
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_e1", NULL);
 }
 
 static int armv8_n1_pmu_init(struct arm_pmu *cpu_pmu)
 {
-	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_n1",
-				       armv8_pmuv3_map_event);
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_n1", NULL);
 }
 
 static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
-- 
2.28.0.dirty

Re: [PATCH 2/5] arm64: perf: Simplify registration boilerplate

[Mark Rutland]

On Tue, Dec 07, 2021 at 06:20:40PM +0000, Robin Murphy wrote:
> The arm_pmu framework requires map_event to be non-NULL, so let
> armv8_pmu_init() treat NULL as a default value for the generic PMUv3
> event map and simplify the boilerplate in the callers a bit.
> 
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
>  arch/arm64/kernel/perf_event.c | 32 +++++++++++---------------------
>  1 file changed, 11 insertions(+), 21 deletions(-)
> 
> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> index b4044469527e..57720372da62 100644
> --- a/arch/arm64/kernel/perf_event.c
> +++ b/arch/arm64/kernel/perf_event.c
> @@ -1128,7 +1128,7 @@ static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name,
>  	cpu_pmu->filter_match		= armv8pmu_filter_match;
>  
>  	cpu_pmu->name			= name;
> -	cpu_pmu->map_event		= map_event;
> +	cpu_pmu->map_event		= map_event ?: armv8_pmuv3_map_event;
>  	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = events ?
>  			events : &armv8_pmuv3_events_attr_group;
>  	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = format ?

Acked-by: Mark Rutland <mark.rutland@arm.com>

I'll leave it to will to pick this.

Mark.

> @@ -1147,14 +1147,12 @@ static int armv8_pmu_init_nogroups(struct arm_pmu *cpu_pmu, char *name,
>  
>  static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
>  {
> -	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_pmuv3",
> -				       armv8_pmuv3_map_event);
> +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_pmuv3", NULL);
>  }
>  
>  static int armv8_a34_pmu_init(struct arm_pmu *cpu_pmu)
>  {
> -	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a34",
> -				       armv8_pmuv3_map_event);
> +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a34", NULL);
>  }
>  
>  static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu)
> @@ -1171,8 +1169,7 @@ static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
>  
>  static int armv8_a55_pmu_init(struct arm_pmu *cpu_pmu)
>  {
> -	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a55",
> -				       armv8_pmuv3_map_event);
> +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a55", NULL);
>  }
>  
>  static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
> @@ -1183,8 +1180,7 @@ static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
>  
>  static int armv8_a65_pmu_init(struct arm_pmu *cpu_pmu)
>  {
> -	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a65",
> -				       armv8_pmuv3_map_event);
> +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a65", NULL);
>  }
>  
>  static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
> @@ -1201,38 +1197,32 @@ static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)
>  
>  static int armv8_a75_pmu_init(struct arm_pmu *cpu_pmu)
>  {
> -	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a75",
> -				       armv8_pmuv3_map_event);
> +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a75", NULL);
>  }
>  
>  static int armv8_a76_pmu_init(struct arm_pmu *cpu_pmu)
>  {
> -	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a76",
> -				       armv8_pmuv3_map_event);
> +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a76", NULL);
>  }
>  
>  static int armv8_a77_pmu_init(struct arm_pmu *cpu_pmu)
>  {
> -	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a77",
> -				       armv8_pmuv3_map_event);
> +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a77", NULL);
>  }
>  
>  static int armv8_a78_pmu_init(struct arm_pmu *cpu_pmu)
>  {
> -	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a78",
> -				       armv8_pmuv3_map_event);
> +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a78", NULL);
>  }
>  
>  static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu)
>  {
> -	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_e1",
> -				       armv8_pmuv3_map_event);
> +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_e1", NULL);
>  }
>  
>  static int armv8_n1_pmu_init(struct arm_pmu *cpu_pmu)
>  {
> -	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_n1",
> -				       armv8_pmuv3_map_event);
> +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_n1", NULL);
>  }
>  
>  static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
> -- 
> 2.28.0.dirty
> 

[PATCH 3/5] arm64: perf: Support new DT compatibles

[Robin Murphy]

Wire up the new DT compatibles so we can present appropriate
PMU names to userspace for the latest and greatest CPUs.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
 arch/arm64/kernel/perf_event.c | 36 ++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 57720372da62..3fe4dcfc28d4 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -1215,6 +1215,26 @@ static int armv8_a78_pmu_init(struct arm_pmu *cpu_pmu)
 	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a78", NULL);
 }
 
+static int armv9_a510_pmu_init(struct arm_pmu *cpu_pmu)
+{
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv9_cortex_a510", NULL);
+}
+
+static int armv9_a710_pmu_init(struct arm_pmu *cpu_pmu)
+{
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv9_cortex_a710", NULL);
+}
+
+static int armv8_x1_pmu_init(struct arm_pmu *cpu_pmu)
+{
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_x1", NULL);
+}
+
+static int armv9_x2_pmu_init(struct arm_pmu *cpu_pmu)
+{
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv9_cortex_x2", NULL);
+}
+
 static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu)
 {
 	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_e1", NULL);
@@ -1225,6 +1245,16 @@ static int armv8_n1_pmu_init(struct arm_pmu *cpu_pmu)
 	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_n1", NULL);
 }
 
+static int armv9_n2_pmu_init(struct arm_pmu *cpu_pmu)
+{
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv9_neoverse_n2", NULL);
+}
+
+static int armv8_v1_pmu_init(struct arm_pmu *cpu_pmu)
+{
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_v1", NULL);
+}
+
 static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
 {
 	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cavium_thunder",
@@ -1251,8 +1281,14 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = {
 	{.compatible = "arm,cortex-a76-pmu",	.data = armv8_a76_pmu_init},
 	{.compatible = "arm,cortex-a77-pmu",	.data = armv8_a77_pmu_init},
 	{.compatible = "arm,cortex-a78-pmu",	.data = armv8_a78_pmu_init},
+	{.compatible = "arm,cortex-a510-pmu",	.data = armv9_a510_pmu_init},
+	{.compatible = "arm,cortex-a710-pmu",	.data = armv9_a710_pmu_init},
+	{.compatible = "arm,cortex-x1-pmu",	.data = armv8_x1_pmu_init},
+	{.compatible = "arm,cortex-x2-pmu",	.data = armv9_x2_pmu_init},
 	{.compatible = "arm,neoverse-e1-pmu",	.data = armv8_e1_pmu_init},
 	{.compatible = "arm,neoverse-n1-pmu",	.data = armv8_n1_pmu_init},
+	{.compatible = "arm,neoverse-n2-pmu",	.data = armv9_n2_pmu_init},
+	{.compatible = "arm,neoverse-v1-pmu",	.data = armv8_v1_pmu_init},
 	{.compatible = "cavium,thunder-pmu",	.data = armv8_thunder_pmu_init},
 	{.compatible = "brcm,vulcan-pmu",	.data = armv8_vulcan_pmu_init},
 	{},
-- 
2.28.0.dirty

Re: [PATCH 3/5] arm64: perf: Support new DT compatibles

[Mark Rutland]

On Tue, Dec 07, 2021 at 06:20:41PM +0000, Robin Murphy wrote:
> Wire up the new DT compatibles so we can present appropriate
> PMU names to userspace for the latest and greatest CPUs.
> 
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
>  arch/arm64/kernel/perf_event.c | 36 ++++++++++++++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
> 
> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> index 57720372da62..3fe4dcfc28d4 100644
> --- a/arch/arm64/kernel/perf_event.c
> +++ b/arch/arm64/kernel/perf_event.c
> @@ -1215,6 +1215,26 @@ static int armv8_a78_pmu_init(struct arm_pmu *cpu_pmu)
>  	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a78", NULL);
>  }
>  
> +static int armv9_a510_pmu_init(struct arm_pmu *cpu_pmu)
> +{
> +	return armv8_pmu_init_nogroups(cpu_pmu, "armv9_cortex_a510", NULL);
> +}
> +
> +static int armv9_a710_pmu_init(struct arm_pmu *cpu_pmu)
> +{
> +	return armv8_pmu_init_nogroups(cpu_pmu, "armv9_cortex_a710", NULL);
> +}
> +
> +static int armv8_x1_pmu_init(struct arm_pmu *cpu_pmu)
> +{
> +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_x1", NULL);
> +}
> +
> +static int armv9_x2_pmu_init(struct arm_pmu *cpu_pmu)
> +{
> +	return armv8_pmu_init_nogroups(cpu_pmu, "armv9_cortex_x2", NULL);
> +}

I wonder if it'd be better to do something like:

#define PMU_INIT_SIMPLE(name)						\
static int name##_pmu_init(struct arm_pmu *cpu_pmu)			\
{
	return armv8_pmu_init_nogroups(cpu_pmu, #name, NULL);		\
}

PMU_INIT_SIMPLE(armv9_cortex_a510)
PMU_INIT_SIMPLE(armv9_cortex_a710)
PMU_INIT_SIMPLE(armv8_xortex_x1)
PMU_INIT_SIMPLE(armv9_xortex_x2)

... and fix up the armv8_pmu_of_device_ids[] table to use the longer init names
that results in?

Otherwise, looks good to me.

Thanks,
Mark.

> +
>  static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu)
>  {
>  	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_e1", NULL);
> @@ -1225,6 +1245,16 @@ static int armv8_n1_pmu_init(struct arm_pmu *cpu_pmu)
>  	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_n1", NULL);
>  }
>  
> +static int armv9_n2_pmu_init(struct arm_pmu *cpu_pmu)
> +{
> +	return armv8_pmu_init_nogroups(cpu_pmu, "armv9_neoverse_n2", NULL);
> +}
> +
> +static int armv8_v1_pmu_init(struct arm_pmu *cpu_pmu)
> +{
> +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_v1", NULL);
> +}
> +
>  static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
>  {
>  	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cavium_thunder",
> @@ -1251,8 +1281,14 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = {
>  	{.compatible = "arm,cortex-a76-pmu",	.data = armv8_a76_pmu_init},
>  	{.compatible = "arm,cortex-a77-pmu",	.data = armv8_a77_pmu_init},
>  	{.compatible = "arm,cortex-a78-pmu",	.data = armv8_a78_pmu_init},
> +	{.compatible = "arm,cortex-a510-pmu",	.data = armv9_a510_pmu_init},
> +	{.compatible = "arm,cortex-a710-pmu",	.data = armv9_a710_pmu_init},
> +	{.compatible = "arm,cortex-x1-pmu",	.data = armv8_x1_pmu_init},
> +	{.compatible = "arm,cortex-x2-pmu",	.data = armv9_x2_pmu_init},
>  	{.compatible = "arm,neoverse-e1-pmu",	.data = armv8_e1_pmu_init},
>  	{.compatible = "arm,neoverse-n1-pmu",	.data = armv8_n1_pmu_init},
> +	{.compatible = "arm,neoverse-n2-pmu",	.data = armv9_n2_pmu_init},
> +	{.compatible = "arm,neoverse-v1-pmu",	.data = armv8_v1_pmu_init},
>  	{.compatible = "cavium,thunder-pmu",	.data = armv8_thunder_pmu_init},
>  	{.compatible = "brcm,vulcan-pmu",	.data = armv8_vulcan_pmu_init},
>  	{},
> -- 
> 2.28.0.dirty
> 

Re: [PATCH 3/5] arm64: perf: Support new DT compatibles

[Robin Murphy]

On 2021-12-07 18:44, Mark Rutland wrote:
> On Tue, Dec 07, 2021 at 06:20:41PM +0000, Robin Murphy wrote:
>> Wire up the new DT compatibles so we can present appropriate
>> PMU names to userspace for the latest and greatest CPUs.
>>
>> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>> ---
>>   arch/arm64/kernel/perf_event.c | 36 ++++++++++++++++++++++++++++++++++
>>   1 file changed, 36 insertions(+)
>>
>> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
>> index 57720372da62..3fe4dcfc28d4 100644
>> --- a/arch/arm64/kernel/perf_event.c
>> +++ b/arch/arm64/kernel/perf_event.c
>> @@ -1215,6 +1215,26 @@ static int armv8_a78_pmu_init(struct arm_pmu *cpu_pmu)
>>   	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a78", NULL);
>>   }
>>   
>> +static int armv9_a510_pmu_init(struct arm_pmu *cpu_pmu)
>> +{
>> +	return armv8_pmu_init_nogroups(cpu_pmu, "armv9_cortex_a510", NULL);
>> +}
>> +
>> +static int armv9_a710_pmu_init(struct arm_pmu *cpu_pmu)
>> +{
>> +	return armv8_pmu_init_nogroups(cpu_pmu, "armv9_cortex_a710", NULL);
>> +}
>> +
>> +static int armv8_x1_pmu_init(struct arm_pmu *cpu_pmu)
>> +{
>> +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_x1", NULL);
>> +}
>> +
>> +static int armv9_x2_pmu_init(struct arm_pmu *cpu_pmu)
>> +{
>> +	return armv8_pmu_init_nogroups(cpu_pmu, "armv9_cortex_x2", NULL);
>> +}
> 
> I wonder if it'd be better to do something like:
> 
> #define PMU_INIT_SIMPLE(name)						\
> static int name##_pmu_init(struct arm_pmu *cpu_pmu)			\
> {
> 	return armv8_pmu_init_nogroups(cpu_pmu, #name, NULL);		\
> }
> 
> PMU_INIT_SIMPLE(armv9_cortex_a510)
> PMU_INIT_SIMPLE(armv9_cortex_a710)
> PMU_INIT_SIMPLE(armv8_xortex_x1)
> PMU_INIT_SIMPLE(armv9_xortex_x2)
> 
> ... and fix up the armv8_pmu_of_device_ids[] table to use the longer init names
> that results in?

Indeed I did ponder doing almost exactly that, but at that point I'd 
rather try refactoring a bit deeper to convert most of the arm_pmu init 
business to pure data, so I figured I'd chuck in the simple tweak to 
mitigate these new additions with minimal churn, then have a go at the 
bigger change in its own right.

> Otherwise, looks good to me.

Thanks!

Robin.

> 
> Thanks,
> Mark.
> 
>> +
>>   static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu)
>>   {
>>   	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_e1", NULL);
>> @@ -1225,6 +1245,16 @@ static int armv8_n1_pmu_init(struct arm_pmu *cpu_pmu)
>>   	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_n1", NULL);
>>   }
>>   
>> +static int armv9_n2_pmu_init(struct arm_pmu *cpu_pmu)
>> +{
>> +	return armv8_pmu_init_nogroups(cpu_pmu, "armv9_neoverse_n2", NULL);
>> +}
>> +
>> +static int armv8_v1_pmu_init(struct arm_pmu *cpu_pmu)
>> +{
>> +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_v1", NULL);
>> +}
>> +
>>   static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
>>   {
>>   	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cavium_thunder",
>> @@ -1251,8 +1281,14 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = {
>>   	{.compatible = "arm,cortex-a76-pmu",	.data = armv8_a76_pmu_init},
>>   	{.compatible = "arm,cortex-a77-pmu",	.data = armv8_a77_pmu_init},
>>   	{.compatible = "arm,cortex-a78-pmu",	.data = armv8_a78_pmu_init},
>> +	{.compatible = "arm,cortex-a510-pmu",	.data = armv9_a510_pmu_init},
>> +	{.compatible = "arm,cortex-a710-pmu",	.data = armv9_a710_pmu_init},
>> +	{.compatible = "arm,cortex-x1-pmu",	.data = armv8_x1_pmu_init},
>> +	{.compatible = "arm,cortex-x2-pmu",	.data = armv9_x2_pmu_init},
>>   	{.compatible = "arm,neoverse-e1-pmu",	.data = armv8_e1_pmu_init},
>>   	{.compatible = "arm,neoverse-n1-pmu",	.data = armv8_n1_pmu_init},
>> +	{.compatible = "arm,neoverse-n2-pmu",	.data = armv9_n2_pmu_init},
>> +	{.compatible = "arm,neoverse-v1-pmu",	.data = armv8_v1_pmu_init},
>>   	{.compatible = "cavium,thunder-pmu",	.data = armv8_thunder_pmu_init},
>>   	{.compatible = "brcm,vulcan-pmu",	.data = armv8_vulcan_pmu_init},
>>   	{},
>> -- 
>> 2.28.0.dirty
>>

Re: [PATCH 3/5] arm64: perf: Support new DT compatibles

[Mark Rutland]

On Tue, Dec 07, 2021 at 07:14:29PM +0000, Robin Murphy wrote:
> On 2021-12-07 18:44, Mark Rutland wrote:
> > On Tue, Dec 07, 2021 at 06:20:41PM +0000, Robin Murphy wrote:
> > > Wire up the new DT compatibles so we can present appropriate
> > > PMU names to userspace for the latest and greatest CPUs.
> > > 
> > > Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> > > ---
> > >   arch/arm64/kernel/perf_event.c | 36 ++++++++++++++++++++++++++++++++++
> > >   1 file changed, 36 insertions(+)
> > > 
> > > diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> > > index 57720372da62..3fe4dcfc28d4 100644
> > > --- a/arch/arm64/kernel/perf_event.c
> > > +++ b/arch/arm64/kernel/perf_event.c
> > > @@ -1215,6 +1215,26 @@ static int armv8_a78_pmu_init(struct arm_pmu *cpu_pmu)
> > >   	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a78", NULL);
> > >   }
> > > +static int armv9_a510_pmu_init(struct arm_pmu *cpu_pmu)
> > > +{
> > > +	return armv8_pmu_init_nogroups(cpu_pmu, "armv9_cortex_a510", NULL);
> > > +}
> > > +
> > > +static int armv9_a710_pmu_init(struct arm_pmu *cpu_pmu)
> > > +{
> > > +	return armv8_pmu_init_nogroups(cpu_pmu, "armv9_cortex_a710", NULL);
> > > +}
> > > +
> > > +static int armv8_x1_pmu_init(struct arm_pmu *cpu_pmu)
> > > +{
> > > +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_x1", NULL);
> > > +}
> > > +
> > > +static int armv9_x2_pmu_init(struct arm_pmu *cpu_pmu)
> > > +{
> > > +	return armv8_pmu_init_nogroups(cpu_pmu, "armv9_cortex_x2", NULL);
> > > +}
> > 
> > I wonder if it'd be better to do something like:
> > 
> > #define PMU_INIT_SIMPLE(name)						\
> > static int name##_pmu_init(struct arm_pmu *cpu_pmu)			\
> > {
> > 	return armv8_pmu_init_nogroups(cpu_pmu, #name, NULL);		\
> > }
> > 
> > PMU_INIT_SIMPLE(armv9_cortex_a510)
> > PMU_INIT_SIMPLE(armv9_cortex_a710)
> > PMU_INIT_SIMPLE(armv8_xortex_x1)
> > PMU_INIT_SIMPLE(armv9_xortex_x2)
> > 
> > ... and fix up the armv8_pmu_of_device_ids[] table to use the longer init names
> > that results in?
> 
> Indeed I did ponder doing almost exactly that, but at that point I'd rather
> try refactoring a bit deeper to convert most of the arm_pmu init business to
> pure data, so I figured I'd chuck in the simple tweak to mitigate these new
> additions with minimal churn, then have a go at the bigger change in its own
> right.

Sure; that makes sense to me, so for this as-is:

Acked-by: Mark Rutland <mark.rutland@arm.com>

... and I'll leave it to Will to have the final say on whether we want the
"armv9_" prefix or whether we stick with "armv8_" for consistenct, when he
chooses to pick this.

One thing I've just realised is that for the ACPI case, we're stuck with
"armv8_pmuv3_%d" regardless, which I think is fine itself, but we might want to
call that out.

Thanks,
Mark.

[PATCH 4/5] dt-bindings: perf: Convert Arm DSU to schema

[Robin Murphy]

Convert the DSU binding to schema, as one does.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
 .../devicetree/bindings/arm/arm-dsu-pmu.txt   | 27 ------------
 .../devicetree/bindings/perf/arm,dsu-pmu.yaml | 41 +++++++++++++++++++
 2 files changed, 41 insertions(+), 27 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
 create mode 100644 Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml

diff --git a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
deleted file mode 100644
index 6efabba530f1..000000000000
--- a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
-
-ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores
-with a shared L3 memory system, control logic and external interfaces to
-form a multicore cluster. The PMU enables to gather various statistics on
-the operations of the DSU. The PMU provides independent 32bit counters that
-can count any of the supported events, along with a 64bit cycle counter.
-The PMU is accessed via CPU system registers and has no MMIO component.
-
-** DSU PMU required properties:
-
-- compatible	: should be one of :
-
-		"arm,dsu-pmu"
-
-- interrupts	: Exactly 1 SPI must be listed.
-
-- cpus		: List of phandles for the CPUs connected to this DSU instance.
-
-
-** Example:
-
-dsu-pmu-0 {
-	compatible = "arm,dsu-pmu";
-	interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>;
-	cpus = <&cpu_0>, <&cpu_1>;
-};
diff --git a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
new file mode 100644
index 000000000000..b78b6b0fce66
--- /dev/null
+++ b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2021 Arm Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
+
+maintainers:
+  - Suzuki K Poulose <suzuki.poulose@arm.com>
+  - Robin Murphy <robin.murphy@arm.com>
+
+description:
+  ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores with a shared
+  L3 memory system, control logic and external interfaces to form a multicore
+  cluster. The PMU enables gathering various statistics on the operation of the
+  DSU. The PMU provides independent 32-bit counters that can count any of the
+  supported events, along with a 64-bit cycle counter. The PMU is accessed via
+  CPU system registers and has no MMIO component.
+
+properties:
+  compatible:
+    const: "arm,dsu-pmu"
+
+  interrupts:
+    items:
+      description: nCLUSTERPMUIRQ interrupt
+
+  cpus:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    minitems: 1
+    maxitems: 8
+    description: List of phandles for the CPUs connected to this DSU instance.
+
+required:
+  - compatible
+  - interrupts
+  - cpus
+
+additionalProperties: false
-- 
2.28.0.dirty

Re: [PATCH 4/5] dt-bindings: perf: Convert Arm DSU to schema

[Rob Herring]

On Tue, 07 Dec 2021 18:20:42 +0000, Robin Murphy wrote:
> Convert the DSU binding to schema, as one does.
> 
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
>  .../devicetree/bindings/arm/arm-dsu-pmu.txt   | 27 ------------
>  .../devicetree/bindings/perf/arm,dsu-pmu.yaml | 41 +++++++++++++++++++
>  2 files changed, 41 insertions(+), 27 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
>  create mode 100644 Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml: properties:cpus: 'minitems' is not one of ['$ref', 'additionalItems', 'additionalProperties', 'allOf', 'anyOf', 'const', 'contains', 'default', 'dependencies', 'dependentRequired', 'dependentSchemas', 'deprecated', 'description', 'else', 'enum', 'exclusiveMaximum', 'exclusiveMinimum', 'items', 'if', 'minItems', 'minimum', 'maxItems', 'maximum', 'multipleOf', 'not', 'oneOf', 'pattern', 'patternProperties', 'properties', 'required', 'then', 'type', 'typeSize', 'unevaluatedProperties', 'uniqueItems']
	from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml: properties:cpus: 'maxitems' is not one of ['$ref', 'additionalItems', 'additionalProperties', 'allOf', 'anyOf', 'const', 'contains', 'default', 'dependencies', 'dependentRequired', 'dependentSchemas', 'deprecated', 'description', 'else', 'enum', 'exclusiveMaximum', 'exclusiveMinimum', 'items', 'if', 'minItems', 'minimum', 'maxItems', 'maximum', 'multipleOf', 'not', 'oneOf', 'pattern', 'patternProperties', 'properties', 'required', 'then', 'type', 'typeSize', 'unevaluatedProperties', 'uniqueItems']
	from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml: ignoring, error in schema: properties: cpus
warning: no schema found in file: ./Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1564818

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

Re: [PATCH 4/5] dt-bindings: perf: Convert Arm DSU to schema

[Rob Herring]

On Tue, Dec 07, 2021 at 06:20:42PM +0000, Robin Murphy wrote:
> Convert the DSU binding to schema, as one does.
> 
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
>  .../devicetree/bindings/arm/arm-dsu-pmu.txt   | 27 ------------
>  .../devicetree/bindings/perf/arm,dsu-pmu.yaml | 41 +++++++++++++++++++
>  2 files changed, 41 insertions(+), 27 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
>  create mode 100644 Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
> 
> diff --git a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
> deleted file mode 100644
> index 6efabba530f1..000000000000
> --- a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
> +++ /dev/null
> @@ -1,27 +0,0 @@
> -* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
> -
> -ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores
> -with a shared L3 memory system, control logic and external interfaces to
> -form a multicore cluster. The PMU enables to gather various statistics on
> -the operations of the DSU. The PMU provides independent 32bit counters that
> -can count any of the supported events, along with a 64bit cycle counter.
> -The PMU is accessed via CPU system registers and has no MMIO component.
> -
> -** DSU PMU required properties:
> -
> -- compatible	: should be one of :
> -
> -		"arm,dsu-pmu"
> -
> -- interrupts	: Exactly 1 SPI must be listed.
> -
> -- cpus		: List of phandles for the CPUs connected to this DSU instance.
> -
> -
> -** Example:
> -
> -dsu-pmu-0 {
> -	compatible = "arm,dsu-pmu";
> -	interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>;
> -	cpus = <&cpu_0>, <&cpu_1>;
> -};
> diff --git a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
> new file mode 100644
> index 000000000000..b78b6b0fce66
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
> @@ -0,0 +1,41 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright 2021 Arm Ltd.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
> +
> +maintainers:
> +  - Suzuki K Poulose <suzuki.poulose@arm.com>
> +  - Robin Murphy <robin.murphy@arm.com>
> +
> +description:
> +  ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores with a shared
> +  L3 memory system, control logic and external interfaces to form a multicore
> +  cluster. The PMU enables gathering various statistics on the operation of the
> +  DSU. The PMU provides independent 32-bit counters that can count any of the
> +  supported events, along with a 64-bit cycle counter. The PMU is accessed via
> +  CPU system registers and has no MMIO component.
> +
> +properties:
> +  compatible:
> +    const: "arm,dsu-pmu"

Don't need quotes.

> +
> +  interrupts:
> +    items:
> +      description: nCLUSTERPMUIRQ interrupt

         - description: nCLUSTERPMUIRQ interrupt

> +
> +  cpus:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    minitems: 1
> +    maxitems: 8
> +    description: List of phandles for the CPUs connected to this DSU instance.
> +
> +required:
> +  - compatible
> +  - interrupts
> +  - cpus
> +
> +additionalProperties: false
> -- 
> 2.28.0.dirty
> 
> 

[PATCH 5/5] dt-bindings: perf: Add compatible for Arm DSU-110

[Robin Murphy]

DSU-110 is the newest and shiniest for Armv9. Its programmer's model is
largely identical to the previous generation of DSUs, so we can treat it
as compatible, but it does have a a handful of extra IMP-DEF PMU events
to call its own. Thanks to the new notion of core complexes, the maximum
number of supported CPUs goes up as well.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
 Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
index b78b6b0fce66..b623520ad302 100644
--- a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
+++ b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
@@ -21,7 +21,11 @@ description:
 
 properties:
   compatible:
-    const: "arm,dsu-pmu"
+    oneof:
+      const: "arm,dsu-pmu"
+      items:
+        const: "arm,dsu-110-pmu"
+        const: "arm,dsu-pmu"
 
   interrupts:
     items:
@@ -30,7 +34,7 @@ properties:
   cpus:
     $ref: /schemas/types.yaml#/definitions/phandle-array
     minitems: 1
-    maxitems: 8
+    maxitems: 12
     description: List of phandles for the CPUs connected to this DSU instance.
 
 required:
-- 
2.28.0.dirty

Re: [PATCH 5/5] dt-bindings: perf: Add compatible for Arm DSU-110

[Rob Herring]

On Tue, Dec 07, 2021 at 06:20:43PM +0000, Robin Murphy wrote:
> DSU-110 is the newest and shiniest for Armv9. Its programmer's model is
> largely identical to the previous generation of DSUs, so we can treat it
> as compatible, but it does have a a handful of extra IMP-DEF PMU events
> to call its own. Thanks to the new notion of core complexes, the maximum
> number of supported CPUs goes up as well.
> 
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
>  Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
> index b78b6b0fce66..b623520ad302 100644
> --- a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
> +++ b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
> @@ -21,7 +21,11 @@ description:
>  
>  properties:
>    compatible:
> -    const: "arm,dsu-pmu"
> +    oneof:

'oneOf' and should be a list.

jsonschema is case sensitive yet the tools are silent on wrong case (but 
handled by dtschema). 

> +      const: "arm,dsu-pmu"
> +      items:
> +        const: "arm,dsu-110-pmu"
> +        const: "arm,dsu-pmu"

'items' needs to be a list here (Use '-').

>  
>    interrupts:
>      items:
> @@ -30,7 +34,7 @@ properties:
>    cpus:
>      $ref: /schemas/types.yaml#/definitions/phandle-array
>      minitems: 1
> -    maxitems: 8
> +    maxitems: 12
>      description: List of phandles for the CPUs connected to this DSU instance.
>  
>  required:
> -- 
> 2.28.0.dirty
> 
> 

Re: [PATCH 5/5] dt-bindings: perf: Add compatible for Arm DSU-110

[Robin Murphy]

On 2021-12-08 18:21, Rob Herring wrote:
> On Tue, Dec 07, 2021 at 06:20:43PM +0000, Robin Murphy wrote:
>> DSU-110 is the newest and shiniest for Armv9. Its programmer's model is
>> largely identical to the previous generation of DSUs, so we can treat it
>> as compatible, but it does have a a handful of extra IMP-DEF PMU events
>> to call its own. Thanks to the new notion of core complexes, the maximum
>> number of supported CPUs goes up as well.
>>
>> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>> ---
>>   Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml | 8 ++++++--
>>   1 file changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
>> index b78b6b0fce66..b623520ad302 100644
>> --- a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
>> +++ b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
>> @@ -21,7 +21,11 @@ description:
>>   
>>   properties:
>>     compatible:
>> -    const: "arm,dsu-pmu"
>> +    oneof:
> 
> 'oneOf' and should be a list.
> 
> jsonschema is case sensitive yet the tools are silent on wrong case (but
> handled by dtschema).
> 
>> +      const: "arm,dsu-pmu"
>> +      items:
>> +        const: "arm,dsu-110-pmu"
>> +        const: "arm,dsu-pmu"
> 
> 'items' needs to be a list here (Use '-').

Oof, I probably deserved little more than a "go away and test these 
patches" for the monumental cock-up on show here - thanks for all the 
pointers and apologies for testing your patience. That'll be the danger 
of picking commits off an old branch in a hurry despite not remembering 
exactly how complete they were, and assuming the "WIP:" must just be 
because they still need commit messages writing...

I've stopped being a lazy git and installed the schema tooling locally 
now too.

Cheers,
Robin.

> 
>>   
>>     interrupts:
>>       items:
>> @@ -30,7 +34,7 @@ properties:
>>     cpus:
>>       $ref: /schemas/types.yaml#/definitions/phandle-array
>>       minitems: 1
>> -    maxitems: 8
>> +    maxitems: 12
>>       description: List of phandles for the CPUs connected to this DSU instance.
>>   
>>   required:
>> -- 
>> 2.28.0.dirty
>>
>>