From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69517241CB6; Thu, 24 Jul 2025 14:42:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753368167; cv=none; b=KC1vhFAqNWJYz63gPDOUg6/9auQnjeBxH0yTzlal5+Uxlezt1lTD2FfWh/DCOmdLra23xoofOuS6EbM2AWbxda5EW8ZPDd4yBeomh+qPaDNo8Kq+BjUm6b/JVAfrTDueyWmNjtYikOO6epX0di1GW5TYGu64ml8ujZ0v5jkvgmc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753368167; c=relaxed/simple; bh=KSniqmvVPop7ZBfbM76NpcruOKat+g9pCk10WcIV1OA=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=NWVWYOnGz3emYiMIla8uBBKN9+T+rz7gGd1vGFENkKlz6t26+31idk7+0IanJYzLqJ9WknTKIzHi64sl24XoPm8Qz2FWBABtRV9HEEQgookKlDpnE1XxPaT4jMprs+ztrVKH7S7kVQUVTmMXzqYvq9C3zXzbcqSzlrRTDJljkRA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=g0pozWt1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="g0pozWt1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AA7B4C4CEED; Thu, 24 Jul 2025 14:42:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753368166; bh=KSniqmvVPop7ZBfbM76NpcruOKat+g9pCk10WcIV1OA=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=g0pozWt1eUa0aQbqU6JhZ4GaxIQ00YPSgEvrGorvNEoKoReaz0o9uUGxy4TgX3eSd 5zu1HNr9wWKyX3JnbPgbuGL7V/Zqvda2D/cDjhrV4uu8sI27M/GcsfeGqVztPuAY03 Sn6E31o9Js3fZWJb0XqZPsJbVFRDy+IgCQqtliGkQF32bvxfHDVKQeprLvFRB8rC5U nZ+pv3BACCJTToNXkgbVWynDGCQ4htKDA+JsDWufJDvJSzUuqmcyf0ItgHkluI69/x 0XwZyN0Z/uAnz/31oHXLMQpD3fVAViR1s6xAgl+NaHg9ZUYd4t1zN4zDPD/6921cYh eUVuTEr7W3zvA== Message-ID: Date: Thu, 24 Jul 2025 16:42:41 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] dt-bindings: clock: qcom: Add SM8750 GPU clocks To: Konrad Dybcio , Konrad Dybcio Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250723-topic-8750_gpucc-v2-0-56c93b84c390@oss.qualcomm.com> <20250723-topic-8750_gpucc-v2-1-56c93b84c390@oss.qualcomm.com> <20250724-blazing-therapeutic-python-1e96ca@kuoka> <7d444f4c-fa1f-4436-b93a-f2d2b6d49de2@oss.qualcomm.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; keydata= xsFNBFVDQq4BEAC6KeLOfFsAvFMBsrCrJ2bCalhPv5+KQF2PS2+iwZI8BpRZoV+Bd5kWvN79 cFgcqTTuNHjAvxtUG8pQgGTHAObYs6xeYJtjUH0ZX6ndJ33FJYf5V3yXqqjcZ30FgHzJCFUu JMp7PSyMPzpUXfU12yfcRYVEMQrmplNZssmYhiTeVicuOOypWugZKVLGNm0IweVCaZ/DJDIH gNbpvVwjcKYrx85m9cBVEBUGaQP6AT7qlVCkrf50v8bofSIyVa2xmubbAwwFA1oxoOusjPIE J3iadrwpFvsZjF5uHAKS+7wHLoW9hVzOnLbX6ajk5Hf8Pb1m+VH/E8bPBNNYKkfTtypTDUCj NYcd27tjnXfG+SDs/EXNUAIRefCyvaRG7oRYF3Ec+2RgQDRnmmjCjoQNbFrJvJkFHlPeHaeS BosGY+XWKydnmsfY7SSnjAzLUGAFhLd/XDVpb1Een2XucPpKvt9ORF+48gy12FA5GduRLhQU vK4tU7ojoem/G23PcowM1CwPurC8sAVsQb9KmwTGh7rVz3ks3w/zfGBy3+WmLg++C2Wct6nM Pd8/6CBVjEWqD06/RjI2AnjIq5fSEH/BIfXXfC68nMp9BZoy3So4ZsbOlBmtAPvMYX6U8VwD TNeBxJu5Ex0Izf1NV9CzC3nNaFUYOY8KfN01X5SExAoVTr09ewARAQABzSVLcnp5c3p0b2Yg S296bG93c2tpIDxrcnprQGtlcm5lbC5vcmc+wsGVBBMBCgA/AhsDBgsJCAcDAgYVCAIJCgsE FgIDAQIeAQIXgBYhBJvQfg4MUfjVlne3VBuTQ307QWKbBQJoF1BKBQkWlnSaAAoJEBuTQ307 QWKbHukP/3t4tRp/bvDnxJfmNdNVn0gv9ep3L39IntPalBFwRKytqeQkzAju0whYWg+R/rwp +r2I1Fzwt7+PTjsnMFlh1AZxGDmP5MFkzVsMnfX1lGiXhYSOMP97XL6R1QSXxaWOpGNCDaUl ajorB0lJDcC0q3xAdwzRConxYVhlgmTrRiD8oLlSCD5baEAt5Zw17UTNDnDGmZQKR0fqLpWy 786Lm5OScb7DjEgcA2PRm17st4UQ1kF0rQHokVaotxRM74PPDB8bCsunlghJl1DRK9s1aSuN hL1Pv9VD8b4dFNvCo7b4hfAANPU67W40AaaGZ3UAfmw+1MYyo4QuAZGKzaP2ukbdCD/DYnqi tJy88XqWtyb4UQWKNoQqGKzlYXdKsldYqrLHGoMvj1UN9XcRtXHST/IaLn72o7j7/h/Ac5EL 8lSUVIG4TYn59NyxxAXa07Wi6zjVL1U11fTnFmE29ALYQEXKBI3KUO1A3p4sQWzU7uRmbuxn naUmm8RbpMcOfa9JjlXCLmQ5IP7Rr5tYZUCkZz08LIfF8UMXwH7OOEX87Y++EkAB+pzKZNNd hwoXulTAgjSy+OiaLtuCys9VdXLZ3Zy314azaCU3BoWgaMV0eAW/+gprWMXQM1lrlzvwlD/k whyy9wGf0AEPpLssLVt9VVxNjo6BIkt6d1pMg6mHsUEVzsFNBFVDXDQBEADNkrQYSREUL4D3 Gws46JEoZ9HEQOKtkrwjrzlw/tCmqVzERRPvz2Xg8n7+HRCrgqnodIYoUh5WsU84N03KlLue MNsWLJBvBaubYN4JuJIdRr4dS4oyF1/fQAQPHh8Thpiz0SAZFx6iWKB7Qrz3OrGCjTPcW6ei OMheesVS5hxietSmlin+SilmIAPZHx7n242u6kdHOh+/SyLImKn/dh9RzatVpUKbv34eP1wA GldWsRxbf3WP9pFNObSzI/Bo3kA89Xx2rO2roC+Gq4LeHvo7ptzcLcrqaHUAcZ3CgFG88CnA 6z6lBZn0WyewEcPOPdcUB2Q7D/NiUY+HDiV99rAYPJztjeTrBSTnHeSBPb+qn5ZZGQwIdUW9 YegxWKvXXHTwB5eMzo/RB6vffwqcnHDoe0q7VgzRRZJwpi6aMIXLfeWZ5Wrwaw2zldFuO4Dt 91pFzBSOIpeMtfgb/Pfe/a1WJ/GgaIRIBE+NUqckM+3zJHGmVPqJP/h2Iwv6nw8U+7Yyl6gU BLHFTg2hYnLFJI4Xjg+AX1hHFVKmvl3VBHIsBv0oDcsQWXqY+NaFahT0lRPjYtrTa1v3tem/ JoFzZ4B0p27K+qQCF2R96hVvuEyjzBmdq2esyE6zIqftdo4MOJho8uctOiWbwNNq2U9pPWmu 4vXVFBYIGmpyNPYzRm0QPwARAQABwsF8BBgBCgAmAhsMFiEEm9B+DgxR+NWWd7dUG5NDfTtB YpsFAmgXUF8FCRaWWyoACgkQG5NDfTtBYptO0w//dlXJs5/42hAXKsk+PDg3wyEFb4NpyA1v qmx7SfAzk9Hf6lWwU1O6AbqNMbh6PjEwadKUk1m04S7EjdQLsj/MBSgoQtCT3MDmWUUtHZd5 RYIPnPq3WVB47GtuO6/u375tsxhtf7vt95QSYJwCB+ZUgo4T+FV4hquZ4AsRkbgavtIzQisg Dgv76tnEv3YHV8Jn9mi/Bu0FURF+5kpdMfgo1sq6RXNQ//TVf8yFgRtTUdXxW/qHjlYURrm2 H4kutobVEIxiyu6m05q3e9eZB/TaMMNVORx+1kM3j7f0rwtEYUFzY1ygQfpcMDPl7pRYoJjB dSsm0ZuzDaCwaxg2t8hqQJBzJCezTOIkjHUsWAK+tEbU4Z4SnNpCyM3fBqsgYdJxjyC/tWVT AQ18NRLtPw7tK1rdcwCl0GFQHwSwk5pDpz1NH40e6lU+NcXSeiqkDDRkHlftKPV/dV+lQXiu jWt87ecuHlpL3uuQ0ZZNWqHgZoQLXoqC2ZV5KrtKWb/jyiFX/sxSrodALf0zf+tfHv0FZWT2 zHjUqd0t4njD/UOsuIMOQn4Ig0SdivYPfZukb5cdasKJukG1NOpbW7yRNivaCnfZz6dTawXw XRIV/KDsHQiyVxKvN73bThKhONkcX2LWuD928tAR6XMM2G5ovxLe09vuOzzfTWQDsm++9UKF a/A= In-Reply-To: <7d444f4c-fa1f-4436-b93a-f2d2b6d49de2@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 24/07/2025 12:53, Konrad Dybcio wrote: > On 7/24/25 10:18 AM, Krzysztof Kozlowski wrote: >> On Wed, Jul 23, 2025 at 10:38:48PM +0200, Konrad Dybcio wrote: >>> From: Konrad Dybcio >>> >>> The SM8750 features a "traditional" GPU_CC block, much of which is >>> controlled through the GMU microcontroller. Additionally, there's >>> an separate GX_CC block, where the GX GDSC is moved. >>> >>> Add bindings to accommodate for that. >>> >>> Signed-off-by: Konrad Dybcio >>> --- > > [...] > >>> +title: Qualcomm Graphics Clock & Reset Controller on SM8750 >> >> There is no clocks nor resets here. Only power domains. > > There are clocks and resets in this IP block (inside the register > space mentioned in the dt patch/example), but the OS is not supposed > to poke at them (it can in theory, but we have a uC - the GMU - > doing the same thing so it would be stepping on one another's toes..). > Not sure how to express that. > > I could for example add #define indices in include/dt-bindings, listing > out the clocks and never consume them. Does that sound fair? Explain that in the binding description. > >> >>> + >>> +maintainers: >>> + - Konrad Dybcio >>> + >>> +description: | >>> + Qualcomm graphics clock control module provides the clocks, resets and power >> >> Also confusing. >> >>> + domains on Qualcomm SoCs. >>> + >>> + See also: >>> + include/dt-bindings/reset/qcom,sm8750-gpucc.h >> >> reset or clock path? > > Ugh, clock > >> >>> + >>> +properties: >>> + compatible: >>> + enum: >>> + - qcom,sm8750-gxcc >>> + >>> + reg: >>> + maxItems: 1 >>> + >>> + power-domains: >>> + items: >>> + - description: GFX voltage rail >>> + - description: MX_COLLAPSIBLE voltage rail >>> + - description: GPU_CC_CX GDSC >>> + >>> + '#power-domain-cells': >>> + const: 1 >>> + >>> +required: >>> + - compatible >>> + - power-domains >>> + - '#power-domain-cells' >>> + >> >> You miss ref... or this is a bit confusing. > ref to what? qcom,gcc? I specifically omitted it, as that adds > requirements which you stated above. Yes, qcom,gcc. If that was missing intentionally, it is fine assuming you implement the rest of comments. Best regards, Krzysztof