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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id h12-20020a2ea48c000000b0026c2e0258bcsm384753lji.42.2022.10.01.02.12.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 01 Oct 2022 02:12:01 -0700 (PDT) Message-ID: Date: Sat, 1 Oct 2022 11:12:00 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.0 Subject: Re: [PATCH 01/19] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs Content-Language: en-US To: Melody Olvera , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20221001030656.29365-1-quic_molvera@quicinc.com> <20221001030656.29365-2-quic_molvera@quicinc.com> From: Krzysztof Kozlowski In-Reply-To: <20221001030656.29365-2-quic_molvera@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 01/10/2022 05:06, Melody Olvera wrote: > Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base > descriptions of CPUs, GCC, RPMHCC, UART, and interrupt-controller to > boot to shell with console on these SoCs. > > Signed-off-by: Melody Olvera > --- > arch/arm64/boot/dts/qcom/qdru1000.dtsi | 370 +++++++++++++++++++++++++ > arch/arm64/boot/dts/qcom/qdu1000.dtsi | 10 + > arch/arm64/boot/dts/qcom/qru1000.dtsi | 10 + > 3 files changed, 390 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/qdru1000.dtsi > create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi > create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi > > diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi > new file mode 100644 > index 000000000000..3610f94bef35 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi > @@ -0,0 +1,370 @@ > +// SPDX-License-Identifier: BSD-3-Clause-Clear > +/* > + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include > +#include > +#include > +#include > + > +/ { > + interrupt-parent = <&intc>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + > + chosen: chosen { }; > + > + No need for double blank line. > + clocks { > + xo_board: xo_board { > + compatible = "fixed-clock"; > + clock-frequency = <19200000>; > + clock-output-names = "xo_board"; > + #clock-cells = <0>; > + }; > + > + sleep_clk: sleep_clk { > + compatible = "fixed-clock"; > + clock-frequency = <32000>; > + #clock-cells = <0>; > + }; > + }; > + (...) > + CPU_PD3: cpu-pd3 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + domain-idle-states = <&SILVER_OFF>; > + }; > + > + CLUSTER_PD: cluster-pd { > + #power-domain-cells = <0>; > + domain-idle-states = <&CLUSTER_PWR_DN &APSS_OFF>; > + }; > + }; > + > + soc: soc@0 { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0 0 0 0 0x10 0>; > + dma-ranges = <0 0 0 0 0x10 0>; > + compatible = "simple-bus"; > + > + gcc: clock-controller@80000 { > + compatible = "qcom,gcc-qdu1000", "qcom,gcc-qru1000", "syscon"; Did you document the compatibles? > + reg = <0x0 0x80000 0x0 0x1f4200>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; > + clock-names = "bi_tcxo", "sleep_clk"; > + }; > + > + qupv3_id_0: geniqup@9c0000 { > + compatible = "qcom,geni-se-qup"; > + reg = <0x0 0x9c0000 0x0 0x2000>; > + clock-names = "m-ahb", "s-ahb"; > + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, > + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + status = "disabled"; > + > + uart7: serial@99c000 { > + compatible = "qcom,geni-debug-uart"; > + reg = <0x0 0x99c000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; > + interrupts = ; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + }; > + (...) > + arch_timer: timer { > + compatible = "arm,armv8-timer"; > + interrupts = , > + , > + , > + , > + ; > + clock-frequency = <19200000>; > + }; > + }; > +}; > diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi > new file mode 100644 > index 000000000000..ba195e7ffc38 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi > @@ -0,0 +1,10 @@ > +// SPDX-License-Identifier: BSD-3-Clause-Clear > +/* > + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include "qdru1000.dtsi" > + > +/ { > + qcom,msm-id = <545 0x10000>, <587 0x10000>; NAK. > +}; > diff --git a/arch/arm64/boot/dts/qcom/qru1000.dtsi b/arch/arm64/boot/dts/qcom/qru1000.dtsi > new file mode 100644 > index 000000000000..1639a4b3c1fb > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/qru1000.dtsi > @@ -0,0 +1,10 @@ > +// SPDX-License-Identifier: BSD-3-Clause-Clear > +/* > + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include "qdru1000.dtsi" > + > +/ { > + qcom,msm-id = <539 0x10000>, <588 0x10000>, <589 0x10000>, <590 0x10000>; Nope, property is not documented and not accepted. Efforts in documenting this property were apparently also not accepted, therefore I am not agreeing in bringing DTS with these. > +}; Best regards, Krzysztof