Re: [PATCH 1/3] drivers/edac: Add L1 and L2 error detection for A72

[Vijay Balakrishna <vijayb@linux.microsoft.com>]

On 5/20/25 02:35, Jonathan Cameron wrote:
> On Thu, 15 May 2025 17:06:11 -0700
> Vijay Balakrishna<vijayb@linux.microsoft.com>  wrote:
> 
>> From: Sascha Hauer<s.hauer@pengutronix.de>
>>
>> The Cortex A72 cores have error detection capabilities for
>> the L1/L2 Caches, this patch adds a driver for them. The selected errors
>> to detect/report are by reading CPU/L2 memory error syndrome registers.
>>
>> Unfortunately there is no robust way to inject errors into the caches,
>> so this driver doesn't contain any code to actually test it. It has
>> been tested though with code taken from an older version [1] of this
>> driver.  For reasons stated in thread [1], the error injection code is
>> not suitable for mainline, so it is removed from the driver.
>>
>> [1]https://lore.kernel.org/all/1521073067-24348-1-git-send-email-york.sun@nxp.com/#t
>>
>> Signed-off-by: Sascha Hauer<s.hauer@pengutronix.de>
>> Co-developed-by: Vijay Balakrishna<vijayb@linux.microsoft.com>
>> Signed-off-by: Vijay Balakrishna<vijayb@linux.microsoft.com>
> Hi.
> 
> Some issues with release of device_nodes in the of parsing code.

Thank you, Jonathan for review. I'm addressing your comments and posting 
next series soon.

Vijay