From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 973EEC7EE2E for ; Wed, 7 Jun 2023 18:18:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229575AbjFGSSG (ORCPT ); Wed, 7 Jun 2023 14:18:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231659AbjFGSSF (ORCPT ); Wed, 7 Jun 2023 14:18:05 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED341210B for ; Wed, 7 Jun 2023 11:17:39 -0700 (PDT) Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-977d0ee1736so643487666b.0 for ; Wed, 07 Jun 2023 11:17:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686161850; x=1688753850; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=prDRECWq9gF2HlqhPhhfLHooXy3hmv9x6uJRavIYoMM=; b=K8CKxwxxN45RRYaTH7NPm1PcmY5u9Gf+agf79C9mZHlN8CYjn0SvqEmRzpevWMmaj0 mhpDpp0KtIdV3xImPBNLj/6AalyMVyBbvf4X+LboPXyX3/mLFTSI5X+EDBye1KGVuQm2 9PLdOHTQuzN6xcm4aatFX34Swjx7jlpQ21OCyutgc/ClFDXHALAPNaF3fP8ybwDpBo4n xFAVxB5O9J9gpHslhAfiEwdyPj4h2ctQ0k2tNERAnpI6L/qkR3zQQwCh5QP7Pp1aE8n4 9znUQsLY05jSaorR006Bdcc8zqOIDdEGKP/qUY5fUyfDEkd/nBxypOV9pwbcbIbWYjk4 C39w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686161850; x=1688753850; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=prDRECWq9gF2HlqhPhhfLHooXy3hmv9x6uJRavIYoMM=; b=gtM1EUwSfHSF3kvzl8WMHCUJcEJ45ylAbYOklJVVjgB1NDhUe8AV8vAiv8rQwE14S6 ToMzLKNLdsE11/hqxD43xpzJBfUTZPfrc9ZS93RMne2cCi/KcKOVxRLVPInQnc+XsK1d GLgQfwf2DaSTLLDakMc39cjV4RY+uPavEzErpTcj0ki2ciQrI6JpUyabcx/+XyzjJGKY A+5RPKMmEnfGhOmIrnILLZjqxHSzdvnKW2ZgoBbhGx/EJKCvj3dAcONUQpet0Sq5/iT2 cnboVeHPIUFaQxim9+rwZFGgEE7fr0vM0BlrqKWcvrMCo1k5Bl84h+nipACOy6hAcjYV sO/A== X-Gm-Message-State: AC+VfDygzHB56RF193m3cXAu58Ilz8C5fwMSHGRf2ToZLoyWXL5lh1rh k475c1nUJVD4oUU+x7bMiflMqA== X-Google-Smtp-Source: ACHHUZ6yoYhGvQnkxo1NhlbZPThR0OVI8Y6NmV6ZpfuYehTZsNtv3pdMlOHWJLxpGXA/52ORFV87KQ== X-Received: by 2002:a17:907:1606:b0:94a:7b2c:205e with SMTP id hb6-20020a170907160600b0094a7b2c205emr6065400ejc.72.1686161849737; Wed, 07 Jun 2023 11:17:29 -0700 (PDT) Received: from [192.168.1.20] ([178.197.219.26]) by smtp.gmail.com with ESMTPSA id gu19-20020a170906f29300b0096a1ba4e0d1sm7262812ejb.32.2023.06.07.11.17.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 07 Jun 2023 11:17:29 -0700 (PDT) Message-ID: Date: Wed, 7 Jun 2023 20:17:26 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 Subject: Re: [PATCH v6 1/1] dt-bindings: pinctrl: Update pinctrl-single to use yaml Content-Language: en-US To: Tony Lindgren , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij Cc: linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, Nishanth Menon , Vignesh Raghavendra , devicetree@vger.kernel.org, linux-gpio@vger.kernel.org References: <20230605095216.18864-1-tony@atomide.com> From: Krzysztof Kozlowski In-Reply-To: <20230605095216.18864-1-tony@atomide.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 05/06/2023 11:52, Tony Lindgren wrote: > Update binding for yaml and remove the old related txt bindings. Note that > we are also adding the undocumented pinctrl-single,slew-rate property. And > we only use the first example from the old binding. > > Cc: Nishanth Menon > Cc: Vignesh Raghavendra > Signed-off-by: Tony Lindgren > --- > > Changes since v5: > - Fix issues noted by Krzysztof > diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml > new file mode 100644 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml > @@ -0,0 +1,206 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Pinctrl driver for hardware with a single register for one or more pins I asked to drop the driver references but it is still here. Bindings are not describing drivers. "Generic Pin Controller with a Single Register for One or More Pins" > + > +maintainers: > + - Tony Lindgren > + > +description: > + Some pin controller devices use a single register for one or more pins. The > + range of pin control registers can vary from one to many for each controller > + instance. Some SoCs from Altera, Broadcom, HiSilicon, Ralink, and TI have this > + kind of pin controller instances. > + > +properties: > + compatible: > + oneOf: > + - enum: > + - pinctrl-single > + - pinconf-single > + - items: > + - enum: > + - ti,am437-padconf > + - ti,dra7-padconf > + - ti,omap2420-padconf > + - ti,omap2430-padconf > + - ti,omap3-padconf > + - ti,omap4-padconf > + - ti,omap5-padconf > + - const: pinctrl-single > + > + reg: > + maxItems: 1 > + > + interrupt-controller: true > + > + '#interrupt-cells': > + const: 1 > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > + '#pinctrl-cells': > + description: > + Number of cells. Usually 2, consisting of register offset, pin configuration > + value, and pinmux mode. Some controllers may use 1 for just offset and value. > + enum: [ 1, 2 ] > + > + pinctrl-single,bit-per-mux: > + description: Optional flag to indicate register controls more than one pin > + type: boolean > + > + pinctrl-single,function-mask: > + description: Mask of the allowed register bits > + $ref: /schemas/types.yaml#/definitions/uint32 > + > + pinctrl-single,function-off: > + description: Optional function off mode for disabled state > + $ref: /schemas/types.yaml#/definitions/uint32 > + > + pinctrl-single,register-width: > + description: Width of pin specific bits in the register > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 8, 16, 32 ] > + > + pinctrl-single,gpio-range: > + description: Optional list of pin base, nr pins & gpio function > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + - items: > + - description: phandle of a gpio-range node > + - description: pin base > + - description: number of pins > + - description: gpio function > + > + '#gpio-range-cells': > + description: No longer needed, may exist in older files for gpio-ranges > + deprecated: true > + const: 3 > + > + gpio-range: > + description: Optional node for gpio range cells > + type: object > + additionalProperties: false > + properties: > + '#pinctrl-single,gpio-range-cells': > + description: Number of gpio range cells > + const: 3 > + $ref: /schemas/types.yaml#/definitions/uint32 > + > +patternProperties: > + '-pins$|-pin': you did not implement my comments fully, probably we misunderstood each other. Why do you allow anything after '-pin'? Let's make it pure suffix for both cases: '-pins?$' > + description: > + Pin group node name using naming ending in -pins, or having -pin > + in the node name > + type: object > + additionalProperties: false > + Best regards, Krzysztof