Re: [PATCH v8 00/15] PCI: renesas: Add RZ/G3E PCIe controller support

[Claudiu Beznea <claudiu.beznea@tuxon.dev>]

On 3/6/26 16:34, John Madieu wrote:
> The Renesas RZ/G3E SoC features a PCIe controller that shares similarities with
> the existing RZ/G3S PCIe controller, but with several key differences.
> This series adds support for the RZ/G3E PCIe controller by extending the existing
> RZ/G3S driver and device tree bindings.
> 
> Key differences between RZ/G3E and RZ/G3S PCIe controllers:
> 
> Link Speed Support:
>   - RZ/G3E: Supports PCIe Gen3 (8.0 GT/s) alongside Gen2 (5.0 GT/s)
>   - RZ/G3S: Supports PCIe Gen2 (5.0 GT/s) only
> 
> Reset Control:
>   - RZ/G3E: Uses register-based reset control mechanism
>   - RZ/G3S: Uses exclusively external reset control signals
> 
> Inbound Window Configuration:
>   - RZ/G3E: Requires precise power-of-2 window coverage with strict address
>     alignment constraints. Non-power-of-2 memory regions must be split into
>     multiple windows to avoid over-mapping, ensuring proper hardware address
>     decoding for DMA operations.
>   - RZ/G3S: Uses a simpler approach that rounds up to the next power-of-2,
>     creating single larger windows. The hardware tolerates over-mapped regions.
> 
> Class/Revision IDs:
>   - RZ/G3E: Requires explicit setting of class/revision values
>   - RZ/G3S: Has default values in hardware
> 
> Clock Naming:
>   - RZ/G3E: Uses "clkpmu" clock for power management
>   - RZ/G3S: Uses "clkl1pm" PM control clock while CLKREQ_B is deasserting
> 
> Phy Settings:
>   - RZ/G3E: Does not need PHY settings as it works with default hw values
>   - RZ/G3S: Requires explicit PHY settings
> 
> This series extends the existing driver to detect the SoC type from the device
> tree compatible string and configure the controller appropriately. The updates
> are minimal and focused on the hardware-specific differences while keeping the
> common code paths unified.
> 
> Changes:
> 
> v8:
>   - Collected additional Rb tags on remaining code patches
>   - Fixed typos in patch descriptions
>   - Fixed checkpatch warnings


I've tested this series on Renesas RZ/G3S SMARC Carrier-II board with an NVMe 
device:

root@smarc-rzg3s:/lava-testing# lspci
00:00.0 PCI bridge: Renesas Technology Corp. Device 0033
01:00.0 Non-Volatile memory controller: Transcend Information, Inc. NVMe PCIe 
SSD 110S/112S/120S/MTE300S/MTE400S/MTE652T2 (DRAM-less) (rev 03)
root@smarc-rzg3s:/lava-testing#

All looks good, thus, for all the patches in this series:

Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Thank you,
Claudiu