From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
To: Robin Murphy <robin.murphy@arm.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Cc: Madalin-cristian Bucur <madalin.bucur@nxp.com>,
Roy Pledge <roy.pledge@nxp.com>, Leo Li <leoyang.li@nxp.com>,
"shawnguo@kernel.org" <shawnguo@kernel.org>,
"davem@davemloft.net" <davem@davemloft.net>
Subject: Re: [PATCH 18/21] arm64: dts: ls104xa: set mask to drop TBU ID from StreamID
Date: Wed, 19 Sep 2018 14:06:53 +0000 [thread overview]
Message-ID: <a4324a5b-abeb-f43a-cac3-7721577e183d@nxp.com> (raw)
In-Reply-To: <fe2af486-3d7d-a38f-ef62-6754f809298f@arm.com>
Hi Robin,
On 19.09.2018 16:41, Robin Murphy wrote:
> On 19/09/18 13:36, laurentiu.tudor@nxp.com wrote:
>> From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
>>
>> The StreamID entering the SMMU is actually a concatenation of the
>> SMMU TBU ID and the ICID configured in software.
>> Since the TBU ID is internal to the SoC and since we want that the
>> actual the ICID configured in software to enter the SMMU witout any
>> additional set bits, mask out the TBU ID bits and leave only the
>> relevant ICID bits to enter SMMU.
>>
>> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
>> ---
>> arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 +
>> arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 +
>> 2 files changed, 2 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
>> b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
>> index 8b3eba167508..90296b9fb171 100644
>> --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
>> @@ -226,6 +226,7 @@
>> compatible = "arm,mmu-500";
>> reg = <0 0x9000000 0 0x400000>;
>> dma-coherent;
>> + stream-match-mask = <0x7f00>;
>
> The TBU ID only forms the top 5 bits, so also ignoring bits 9:8 raises
> an eyebrow - if the LS104x SMMU really is configured for 8-bit SID input
> then it's harmless,
On these lower-end platforms the SID input is configured and documented
as 8-bit.
> but if it's actually a 9 or 10-bit configuration
> then you probably want to avoid masking them (or at least document why)
> - IIRC there *was* stuff wired there on LS2085 at least.
Yes, on LS2s there are 2 extra-bits in there carrying some signaling.
However, on LS1s they are not present.
---
Thanks & Best Regards, Laurentiu
>
>> #global-interrupts = <2>;
>> #iommu-cells = <1>;
>> interrupts = <0 142 4>, /* global secure fault */
>> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
>> b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
>> index 06863d3e4a7d..15094dd8400e 100644
>> --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
>> @@ -232,6 +232,7 @@
>> compatible = "arm,mmu-500";
>> reg = <0 0x9000000 0 0x400000>;
>> dma-coherent;
>> + stream-match-mask = <0x7f00>;
>> #global-interrupts = <2>;
>> #iommu-cells = <1>;
>> interrupts = <0 142 4>, /* global secure fault */
>>
next prev parent reply other threads:[~2018-09-19 14:06 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-19 12:35 [PATCH 00/21] SMMU enablement for NXP LS1043A and LS1046A laurentiu.tudor
2018-09-19 12:35 ` [PATCH 01/21] soc/fsl/qman: fixup liodns only on ppc targets laurentiu.tudor
2018-09-19 12:35 ` [PATCH 02/21] soc/fsl/bman: map FBPR area in the iommu laurentiu.tudor
2018-09-19 12:35 ` [PATCH 03/21] soc/fsl/qman: map FQD and PFDR areas " laurentiu.tudor
2018-09-19 12:35 ` [PATCH 04/21] soc/fsl/qman-portal: map CENA area " laurentiu.tudor
2018-09-19 12:35 ` [PATCH 05/21] soc/fsl/qbman: add APIs to retrieve the probing status laurentiu.tudor
2018-09-19 12:35 ` [PATCH 06/21] soc/fsl/qman_portals: defer probe after qman's probe laurentiu.tudor
2018-09-19 12:35 ` [PATCH 07/21] soc/fsl/bman_portals: defer probe after bman's probe laurentiu.tudor
2018-09-19 12:36 ` [PATCH 08/21] soc/fsl/qbman_portals: add APIs to retrieve the probing status laurentiu.tudor
2018-09-19 12:36 ` [PATCH 09/21] fsl/fman: backup and restore ICID registers laurentiu.tudor
2018-09-19 12:36 ` [PATCH 10/21] fsl/fman: add API to get the device behind a fman port laurentiu.tudor
2018-09-19 12:36 ` [PATCH 11/21] dpaa_eth: defer probing after qbman laurentiu.tudor
2018-09-19 12:36 ` [PATCH 12/21] dpaa_eth: base dma mappings on the fman rx port laurentiu.tudor
2018-09-19 12:36 ` [PATCH 13/21] dpaa_eth: fix iova handling for contiguous frames laurentiu.tudor
2018-09-19 12:36 ` [PATCH 14/21] dpaa_eth: fix iova handling for sg frames laurentiu.tudor
2018-09-19 12:36 ` [PATCH 15/21] dpaa_eth: fix SG frame cleanup laurentiu.tudor
2018-09-19 12:36 ` [PATCH 16/21] arm64: dts: ls1046a: add smmu node laurentiu.tudor
2018-09-19 13:30 ` Robin Murphy
2018-09-19 13:51 ` Laurentiu Tudor
2018-09-19 12:36 ` [PATCH 17/21] arm64: dts: ls1043a: " laurentiu.tudor
2018-09-19 12:36 ` [PATCH 18/21] arm64: dts: ls104xa: set mask to drop TBU ID from StreamID laurentiu.tudor
2018-09-19 13:41 ` Robin Murphy
2018-09-19 14:06 ` Laurentiu Tudor [this message]
2018-09-19 12:36 ` [PATCH 19/21] arm64: dts: ls104x: add missing dma ranges property laurentiu.tudor
2018-09-19 12:36 ` [PATCH 20/21] arm64: dts: ls104x: add iommu-map to pci controllers laurentiu.tudor
2018-09-19 12:36 ` [PATCH 21/21] arm64: dts: ls104x: make dma-coherent global to the SoC laurentiu.tudor
2018-09-19 13:25 ` [PATCH 00/21] SMMU enablement for NXP LS1043A and LS1046A Robin Murphy
2018-09-19 14:18 ` Laurentiu Tudor
2018-09-19 14:37 ` Robin Murphy
2018-09-20 10:38 ` Laurentiu Tudor
2018-09-20 11:49 ` Robin Murphy
2018-09-20 14:33 ` Laurentiu Tudor
2018-09-20 19:07 ` Li Yang
2018-09-21 7:32 ` Laurentiu Tudor
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