From: Florian Fainelli <f.fainelli@gmail.com>
To: bcm-kernel-feedback-list@broadcom.com,
Richard Schleich <rs@noreya.tech>,
robh+dt@kernel.org, nsaenz@kernel.org,
devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] ARM: dts: bcm2837: Add the missing L1/L2 cache information
Date: Mon, 31 Jan 2022 16:29:11 -0800 [thread overview]
Message-ID: <a449c627-c036-dc72-0e90-a14f5f1c4dfe@gmail.com> (raw)
In-Reply-To: <20220201002407.426327-1-f.fainelli@gmail.com>
On 1/31/2022 4:24 PM, Florian Fainelli wrote:
> On Sat, 18 Dec 2021 21:00:09 +0100, Richard Schleich <rs@noreya.tech> wrote:
>> This patch fixes the kernel warning
>> "cacheinfo: Unable to detect cache hierarchy for CPU 0"
>> for the bcm2837 on newer kernel versions.
>>
>> Signed-off-by: Richard Schleich <rs@noreya.tech>
>> ---
>
> Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks!
I did remove the comments that were not helpful for the 'd-cache-size',
'd-cache-line-size', 'i-cache-size' and 'i-cache-line-size' since they
are self explanatory.
Thanks!
--
Florian
prev parent reply other threads:[~2022-02-01 0:29 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-18 20:00 [PATCH] ARM: dts: bcm2837: Add the missing L1/L2 cache information Richard Schleich
2021-12-28 17:52 ` Stefan Wahren
2022-02-01 0:24 ` Florian Fainelli
2022-02-01 0:29 ` Florian Fainelli [this message]
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