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Mon, 25 Nov 2024 16:26:17 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 713F240045; Mon, 25 Nov 2024 16:24:52 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A23B62A1036; Mon, 25 Nov 2024 16:23:47 +0100 (CET) Received: from [10.129.178.212] (10.129.178.212) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Mon, 25 Nov 2024 16:23:46 +0100 Message-ID: Date: Mon, 25 Nov 2024 16:23:46 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/5] dt-bindings: PCI: Add STM32MP25 PCIe root complex bindings To: Rob Herring CC: , , , , , , , , , , , , , , , , References: <20241112161925.999196-1-christian.bruel@foss.st.com> <20241112161925.999196-2-christian.bruel@foss.st.com> <20241115163603.GA3188739-robh@kernel.org> Content-Language: en-US From: Christian Bruel In-Reply-To: <20241115163603.GA3188739-robh@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 On 11/15/24 17:36, Rob Herring wrote: > On Tue, Nov 12, 2024 at 05:19:21PM +0100, Christian Bruel wrote: >> Document the bindings for STM32MP25 PCIe Controller configured in >> root complex mode. >> Supports 4 legacy interrupts and MSI interrupts from the ARM >> GICv2m controller. >> >> Allow tuning to change payload (default 128B) thanks to the >> st,max-payload-size entry. >> Can also limit the Maximum Read Request Size on downstream devices to the >> minimum possible value between 128B and 256B. >> >> STM32 PCIE may be in a power domain which is the case for the STM32MP25 >> based boards. >> Supports wake# from wake-gpios >> >> Signed-off-by: Christian Bruel >> --- >> .../bindings/pci/st,stm32-pcie-host.yaml | 149 ++++++++++++++++++ >> 1 file changed, 149 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml >> >> diff --git a/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml b/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml >> new file mode 100644 >> index 000000000000..d7d360b63a08 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml >> @@ -0,0 +1,149 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/pci/st,stm32-pcie-host.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: STM32MP25 PCIe root complex driver >> + >> +maintainers: >> + - Christian Bruel >> + >> +description: >> + PCIe root complex controller based on the Synopsys DesignWare PCIe core. >> + >> +select: >> + properties: >> + compatible: >> + const: st,stm32mp25-pcie-rc >> + required: >> + - compatible >> + >> +allOf: >> + - $ref: /schemas/pci/pci-host-bridge.yaml# >> + - $ref: /schemas/pci/snps,dw-pcie-common.yaml# > > snps,dw-pcie.yaml instead of these 2. > >> + >> +properties: >> + compatible: >> + const: st,stm32mp25-pcie-rc >> + >> + reg: >> + items: >> + - description: Data Bus Interface (DBI) registers. >> + - description: PCIe configuration registers. >> + >> + reg-names: >> + items: >> + - const: dbi >> + - const: config >> + >> + resets: >> + maxItems: 1 >> + >> + reset-names: >> + const: core > > -names with a single entry is kind of pointless. ok, will update the driver accordinly > >> + >> + clocks: >> + maxItems: 1 >> + description: PCIe system clock >> + >> + clock-names: >> + const: core >> + >> + phys: >> + maxItems: 1 >> + >> + phy-names: >> + const: pcie-phy >> + >> + num-lanes: >> + const: 1 >> + >> + msi-parent: >> + maxItems: 1 > > Just 'msi-parent: true'. It's already only ever 1 entry. > >> + >> + reset-gpios: >> + description: GPIO controlled connection to PERST# signal >> + maxItems: 1 >> + >> + wake-gpios: >> + description: GPIO controlled connection to WAKE# input signal >> + maxItems: 1 >> + > >> + st,limit-mrrs: >> + description: If present limit downstream MRRS to 256B >> + type: boolean >> + >> + st,max-payload-size: >> + description: Maximum Payload size to use >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [128, 256] >> + default: 128 > > IIRC, other hosts have similar restrictions, so you should be able to do > the same and imply it from the compatible. Though I'm open to a common > property as Bjorn suggested. > >> + >> + wakeup-source: true >> + >> + power-domains: >> + maxItems: 1 >> + >> + access-controllers: >> + maxItems: 1 >> + >> +if: >> + required: >> + - wakeup-source >> +then: >> + required: >> + - wake-gpios > > This can be just: > > dependentRequired: > wakeup-source: [ wake-gpios ] > > (dependentRequired supercedes dependencies) > >> + >> +required: >> + - interrupt-map >> + - interrupt-map-mask >> + - ranges >> + - resets >> + - reset-names >> + - clocks >> + - clock-names >> + - phys >> + - phy-names >> + >> +unevaluatedProperties: false >> + >> +examples: >> + - | >> + #include >> + #include >> + #include >> + #include >> + #include >> + >> + pcie@48400000 { >> + compatible = "st,stm32mp25-pcie-rc"; >> + device_type = "pci"; >> + num-lanes = <1>; >> + reg = <0x48400000 0x400000>, >> + <0x10000000 0x10000>; >> + reg-names = "dbi", "config"; >> + #interrupt-cells = <1>; >> + interrupt-map-mask = <0 0 0 7>; >> + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 2 &intc 0 0 GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 3 &intc 0 0 GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 4 &intc 0 0 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + ranges = <0x01000000 0 0x10010000 0x10010000 0 0x10000>, >> + <0x02000000 0 0x10020000 0x10020000 0 0x7fe0000>, >> + <0x42000000 0 0x18000000 0x18000000 0 0x8000000>; >> + bus-range = <0x00 0xff>; > > Don't need this unless it's restricted to less than bus 0-255. > >> + clocks = <&rcc CK_BUS_PCIE>; >> + clock-names = "core"; >> + phys = <&combophy PHY_TYPE_PCIE>; >> + phy-names = "pcie-phy"; >> + resets = <&rcc PCIE_R>; >> + reset-names = "core"; >> + msi-parent = <&v2m0>; >> + wakeup-source; >> + wake-gpios = <&gpioh 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; >> + access-controllers = <&rifsc 76>; >> + power-domains = <&CLUSTER_PD>; >> + }; >> -- >> 2.34.1 >> thanks