* [RFC v4 1/4] dt-bindings: pwm: Add StarFive PWM module
2023-08-25 8:13 [RFC v4 0/4] StarFive's Pulse Width Modulation driver support William Qiu
@ 2023-08-25 8:13 ` William Qiu
2023-08-25 8:13 ` [RFC v4 2/4] pwm: starfive: Add PWM driver support William Qiu
` (3 subsequent siblings)
4 siblings, 0 replies; 14+ messages in thread
From: William Qiu @ 2023-08-25 8:13 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-riscv, linux-pwm
Cc: Emil Renner Berthing, Rob Herring, Philipp Zabel, Thierry Reding,
Uwe Kleine-König, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Hal Feng, William Qiu
Add documentation to describe StarFive Pulse Width Modulation
controller driver.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
---
.../bindings/pwm/starfive,jh7100-pwm.yaml | 55 +++++++++++++++++++
1 file changed, 55 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml
diff --git a/Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml b/Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml
new file mode 100644
index 000000000000..6f1937beb962
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/starfive,jh7100-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7100 and JH7110 PWM controller
+
+maintainers:
+ - William Qiu <william.qiu@starfivetech.com>
+
+description:
+ StarFive SoCs contain PWM and when operating in PWM mode, the PTC core generates
+ binary signal with user-programmable low and high periods. Clock source for the
+ PWM can be either system clock or external clock. Each PWM timer block provides 8
+ PWM channels.
+
+allOf:
+ - $ref: pwm.yaml#
+
+properties:
+ compatible:
+ enum:
+ - starfive,jh7100-pwm
+ - starfive,jh7110-pwm
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 3
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ pwm@12490000 {
+ compatible = "starfive,jh7100-pwm";
+ reg = <0x12490000 0x10000>;
+ clocks = <&clkgen 181>;
+ resets = <&rstgen 109>;
+ #pwm-cells = <3>;
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [RFC v4 2/4] pwm: starfive: Add PWM driver support
2023-08-25 8:13 [RFC v4 0/4] StarFive's Pulse Width Modulation driver support William Qiu
2023-08-25 8:13 ` [RFC v4 1/4] dt-bindings: pwm: Add StarFive PWM module William Qiu
@ 2023-08-25 8:13 ` William Qiu
2023-09-12 15:04 ` Emil Renner Berthing
2023-08-25 8:13 ` [RFC v4 3/4] riscv: dts: starfive: jh7110: Add PWM node and pins configuration William Qiu
` (2 subsequent siblings)
4 siblings, 1 reply; 14+ messages in thread
From: William Qiu @ 2023-08-25 8:13 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-riscv, linux-pwm
Cc: Emil Renner Berthing, Rob Herring, Philipp Zabel, Thierry Reding,
Uwe Kleine-König, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Hal Feng, William Qiu
Add Pulse Width Modulation driver support for StarFive
JH7100 and JH7110 SoC.
Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
---
MAINTAINERS | 7 ++
drivers/pwm/Kconfig | 9 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-starfive-ptc.c | 192 +++++++++++++++++++++++++++++++++
4 files changed, 209 insertions(+)
create mode 100644 drivers/pwm/pwm-starfive-ptc.c
diff --git a/MAINTAINERS b/MAINTAINERS
index d590ce31aa72..0e47818c6f64 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20299,6 +20299,13 @@ F: drivers/pinctrl/starfive/pinctrl-starfive-jh71*
F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
F: include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
+STARFIVE JH71X0 PWM DRIVERS
+M: William Qiu <william.qiu@starfivetech.com>
+M: Hal Feng <hal.feng@starfivetech.com>
+S: Supported
+F: Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml
+F: drivers/pwm/pwm-starfive-ptc.c
+
STARFIVE JH71X0 RESET CONTROLLER DRIVERS
M: Emil Renner Berthing <kernel@esmil.dk>
M: Hal Feng <hal.feng@starfivetech.com>
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 6210babb0741..48800f33b5c1 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -569,6 +569,15 @@ config PWM_SPRD
To compile this driver as a module, choose M here: the module
will be called pwm-sprd.
+config PWM_STARFIVE_PTC
+ tristate "StarFive PWM PTC support"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ help
+ Generic PWM framework driver for StarFive SoCs.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-starfive-ptc.
+
config PWM_STI
tristate "STiH4xx PWM support"
depends on ARCH_STI || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index c822389c2a24..d2b2a3aeea22 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o
obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o
obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
obj-$(CONFIG_PWM_SPRD) += pwm-sprd.o
+obj-$(CONFIG_PWM_STARFIVE_PTC) += pwm-starfive-ptc.o
obj-$(CONFIG_PWM_STI) += pwm-sti.o
obj-$(CONFIG_PWM_STM32) += pwm-stm32.o
obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o
diff --git a/drivers/pwm/pwm-starfive-ptc.c b/drivers/pwm/pwm-starfive-ptc.c
new file mode 100644
index 000000000000..57b5736f6732
--- /dev/null
+++ b/drivers/pwm/pwm-starfive-ptc.c
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PWM driver for the StarFive JH71x0 SoC
+ *
+ * Copyright (C) 2018-2023 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+
+/* Access PTC register (CNTR, HRC, LRC and CTRL) */
+#define REG_PTC_BASE_ADDR_SUB(base, N) \
+((base) + (((N) > 3) ? (((N) % 4) * 0x10 + (1 << 15)) : ((N) * 0x10)))
+#define REG_PTC_RPTC_CNTR(base, N) (REG_PTC_BASE_ADDR_SUB(base, N))
+#define REG_PTC_RPTC_HRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x4)
+#define REG_PTC_RPTC_LRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x8)
+#define REG_PTC_RPTC_CTRL(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0xC)
+
+/* PTC_RPTC_CTRL register bits*/
+#define PTC_EN BIT(0)
+#define PTC_ECLK BIT(1)
+#define PTC_NEC BIT(2)
+#define PTC_OE BIT(3)
+#define PTC_SIGNLE BIT(4)
+#define PTC_INTE BIT(5)
+#define PTC_INT BIT(6)
+#define PTC_CNTRRST BIT(7)
+#define PTC_CAPTE BIT(8)
+
+struct starfive_pwm_ptc_device {
+ struct pwm_chip chip;
+ struct clk *clk;
+ struct reset_control *rst;
+ void __iomem *regs;
+ u32 clk_rate; /* PWM APB clock frequency */
+};
+
+static inline
+struct starfive_pwm_ptc_device *chip_to_starfive_ptc(struct pwm_chip *c)
+{
+ return container_of(c, struct starfive_pwm_ptc_device, chip);
+}
+
+static int starfive_pwm_ptc_get_state(struct pwm_chip *chip,
+ struct pwm_device *dev,
+ struct pwm_state *state)
+{
+ struct starfive_pwm_ptc_device *pwm = chip_to_starfive_ptc(chip);
+ u32 period_data, duty_data, ctrl_data;
+
+ period_data = readl(REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm));
+ duty_data = readl(REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm));
+ ctrl_data = readl(REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
+
+ state->period = DIV_ROUND_CLOSEST_ULL((u64)period_data * NSEC_PER_SEC, pwm->clk_rate);
+ state->duty_cycle = DIV_ROUND_CLOSEST_ULL((u64)duty_data * NSEC_PER_SEC, pwm->clk_rate);
+ state->polarity = PWM_POLARITY_INVERSED;
+ state->enabled = (ctrl_data & PTC_EN) ? true : false;
+
+ return 0;
+}
+
+static int starfive_pwm_ptc_apply(struct pwm_chip *chip,
+ struct pwm_device *dev,
+ const struct pwm_state *state)
+{
+ struct starfive_pwm_ptc_device *pwm = chip_to_starfive_ptc(chip);
+ u32 period_data, duty_data, ctrl_data = 0;
+
+ if (state->polarity != PWM_POLARITY_INVERSED)
+ return -EINVAL;
+
+ period_data = DIV_ROUND_CLOSEST_ULL(state->period * pwm->clk_rate,
+ NSEC_PER_SEC);
+ duty_data = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * pwm->clk_rate,
+ NSEC_PER_SEC);
+
+ writel(period_data, REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm));
+ writel(duty_data, REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm));
+ writel(0, REG_PTC_RPTC_CNTR(pwm->regs, dev->hwpwm));
+
+ ctrl_data = readl(REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
+ if (state->enabled)
+ writel(ctrl_data | PTC_EN | PTC_OE, REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
+ else
+ writel(ctrl_data & ~(PTC_EN | PTC_OE), REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
+
+ return 0;
+}
+
+static const struct pwm_ops starfive_pwm_ptc_ops = {
+ .get_state = starfive_pwm_ptc_get_state,
+ .apply = starfive_pwm_ptc_apply,
+ .owner = THIS_MODULE,
+};
+
+static int starfive_pwm_ptc_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct starfive_pwm_ptc_device *pwm;
+ struct pwm_chip *chip;
+ int ret;
+
+ pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL);
+ if (!pwm)
+ return -ENOMEM;
+
+ chip = &pwm->chip;
+ chip->dev = dev;
+ chip->ops = &starfive_pwm_ptc_ops;
+ chip->npwm = 8;
+ chip->of_pwm_n_cells = 3;
+
+ pwm->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(pwm->regs))
+ return dev_err_probe(dev, PTR_ERR(pwm->regs),
+ "Unable to map IO resources\n");
+
+ pwm->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(pwm->clk))
+ return dev_err_probe(dev, PTR_ERR(pwm->clk),
+ "Unable to get pwm's clock\n");
+
+ pwm->rst = devm_reset_control_get_exclusive(dev, NULL);
+ if (IS_ERR(pwm->rst))
+ return dev_err_probe(dev, PTR_ERR(pwm->rst),
+ "Unable to get pwm's reset\n");
+
+ ret = clk_prepare_enable(pwm->clk);
+ if (ret) {
+ dev_err(dev,
+ "Failed to enable clock for pwm: %d\n", ret);
+ return ret;
+ }
+
+ reset_control_deassert(pwm->rst);
+
+ pwm->clk_rate = clk_get_rate(pwm->clk);
+ if (pwm->clk_rate <= 0) {
+ dev_warn(dev, "Failed to get APB clock rate\n");
+ return -EINVAL;
+ }
+
+ ret = devm_pwmchip_add(dev, chip);
+ if (ret < 0) {
+ dev_err(dev, "Cannot register PTC: %d\n", ret);
+ clk_disable_unprepare(pwm->clk);
+ reset_control_assert(pwm->rst);
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, pwm);
+
+ return 0;
+}
+
+static int starfive_pwm_ptc_remove(struct platform_device *dev)
+{
+ struct starfive_pwm_ptc_device *pwm = platform_get_drvdata(dev);
+
+ reset_control_assert(pwm->rst);
+ clk_disable_unprepare(pwm->clk);
+
+ return 0;
+}
+
+static const struct of_device_id starfive_pwm_ptc_of_match[] = {
+ { .compatible = "starfive,jh7100-pwm" },
+ { .compatible = "starfive,jh7110-pwm" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, starfive_pwm_ptc_of_match);
+
+static struct platform_driver starfive_pwm_ptc_driver = {
+ .probe = starfive_pwm_ptc_probe,
+ .remove = starfive_pwm_ptc_remove,
+ .driver = {
+ .name = "pwm-starfive-ptc",
+ .of_match_table = starfive_pwm_ptc_of_match,
+ },
+};
+module_platform_driver(starfive_pwm_ptc_driver);
+
+MODULE_AUTHOR("Jieqin Chen");
+MODULE_AUTHOR("Hal Feng <hal.feng@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive PWM PTC driver");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [RFC v4 2/4] pwm: starfive: Add PWM driver support
2023-08-25 8:13 ` [RFC v4 2/4] pwm: starfive: Add PWM driver support William Qiu
@ 2023-09-12 15:04 ` Emil Renner Berthing
2023-09-13 10:57 ` William Qiu
0 siblings, 1 reply; 14+ messages in thread
From: Emil Renner Berthing @ 2023-09-12 15:04 UTC (permalink / raw)
To: William Qiu, devicetree, linux-kernel, linux-riscv, linux-pwm
Cc: Emil Renner Berthing, Rob Herring, Philipp Zabel, Thierry Reding,
Uwe Kleine-König, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Hal Feng
William Qiu wrote:
> Add Pulse Width Modulation driver support for StarFive
> JH7100 and JH7110 SoC.
>
> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> ---
> MAINTAINERS | 7 ++
> drivers/pwm/Kconfig | 9 ++
> drivers/pwm/Makefile | 1 +
> drivers/pwm/pwm-starfive-ptc.c | 192 +++++++++++++++++++++++++++++++++
> 4 files changed, 209 insertions(+)
> create mode 100644 drivers/pwm/pwm-starfive-ptc.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index d590ce31aa72..0e47818c6f64 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -20299,6 +20299,13 @@ F: drivers/pinctrl/starfive/pinctrl-starfive-jh71*
> F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
> F: include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
>
> +STARFIVE JH71X0 PWM DRIVERS
> +M: William Qiu <william.qiu@starfivetech.com>
> +M: Hal Feng <hal.feng@starfivetech.com>
> +S: Supported
> +F: Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml
> +F: drivers/pwm/pwm-starfive-ptc.c
> +
> STARFIVE JH71X0 RESET CONTROLLER DRIVERS
> M: Emil Renner Berthing <kernel@esmil.dk>
> M: Hal Feng <hal.feng@starfivetech.com>
> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> index 6210babb0741..48800f33b5c1 100644
> --- a/drivers/pwm/Kconfig
> +++ b/drivers/pwm/Kconfig
> @@ -569,6 +569,15 @@ config PWM_SPRD
> To compile this driver as a module, choose M here: the module
> will be called pwm-sprd.
>
> +config PWM_STARFIVE_PTC
> + tristate "StarFive PWM PTC support"
> + depends on ARCH_STARFIVE || COMPILE_TEST
> + help
> + Generic PWM framework driver for StarFive SoCs.
> +
> + To compile this driver as a module, choose M here: the module
> + will be called pwm-starfive-ptc.
What is PTC short for? Are there other PWM peripherals on the JH7100 or JH7110
that are not PTCs?
If there are both PTC and non-PTC PWMs on these SoCs then the device tree
compatible strings should reflect that.
If not, maybe just call this driver pwm-starfive / PWM_STARFIVE, or maybe
pwm-starfive-jh7100 / PWM_STARFIVE_JH7110 if you already know the PWMs on the
JH81xx will be different.
> +
> config PWM_STI
> tristate "STiH4xx PWM support"
> depends on ARCH_STI || COMPILE_TEST
> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> index c822389c2a24..d2b2a3aeea22 100644
> --- a/drivers/pwm/Makefile
> +++ b/drivers/pwm/Makefile
> @@ -52,6 +52,7 @@ obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o
> obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o
> obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
> obj-$(CONFIG_PWM_SPRD) += pwm-sprd.o
> +obj-$(CONFIG_PWM_STARFIVE_PTC) += pwm-starfive-ptc.o
> obj-$(CONFIG_PWM_STI) += pwm-sti.o
> obj-$(CONFIG_PWM_STM32) += pwm-stm32.o
> obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o
> diff --git a/drivers/pwm/pwm-starfive-ptc.c b/drivers/pwm/pwm-starfive-ptc.c
> new file mode 100644
> index 000000000000..57b5736f6732
> --- /dev/null
> +++ b/drivers/pwm/pwm-starfive-ptc.c
> @@ -0,0 +1,192 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * PWM driver for the StarFive JH71x0 SoC
> + *
> + * Copyright (C) 2018-2023 StarFive Technology Co., Ltd.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/pwm.h>
> +#include <linux/reset.h>
> +#include <linux/slab.h>
> +
> +/* Access PTC register (CNTR, HRC, LRC and CTRL) */
> +#define REG_PTC_BASE_ADDR_SUB(base, N) \
> +((base) + (((N) > 3) ? (((N) % 4) * 0x10 + (1 << 15)) : ((N) * 0x10)))
Please indent the line above.
> +#define REG_PTC_RPTC_CNTR(base, N) (REG_PTC_BASE_ADDR_SUB(base, N))
> +#define REG_PTC_RPTC_HRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x4)
> +#define REG_PTC_RPTC_LRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x8)
> +#define REG_PTC_RPTC_CTRL(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0xC)
> +
> +/* PTC_RPTC_CTRL register bits*/
> +#define PTC_EN BIT(0)
> +#define PTC_ECLK BIT(1)
> +#define PTC_NEC BIT(2)
> +#define PTC_OE BIT(3)
> +#define PTC_SIGNLE BIT(4)
> +#define PTC_INTE BIT(5)
> +#define PTC_INT BIT(6)
> +#define PTC_CNTRRST BIT(7)
> +#define PTC_CAPTE BIT(8)
> +
> +struct starfive_pwm_ptc_device {
> + struct pwm_chip chip;
> + struct clk *clk;
> + struct reset_control *rst;
> + void __iomem *regs;
> + u32 clk_rate; /* PWM APB clock frequency */
> +};
> +
> +static inline
> +struct starfive_pwm_ptc_device *chip_to_starfive_ptc(struct pwm_chip *c)
This looks weird. Either just put it on a single line or split between the type
and function name. Also there was recently a patch to always name pwm_chip
variables "chip". Eg.
static inline struct starfive_pwm_ptc_device *
chip_to_starfive_ptc(struct pwm_chip *chip)
{
> +{
> + return container_of(c, struct starfive_pwm_ptc_device, chip);
> +}
> +
> +static int starfive_pwm_ptc_get_state(struct pwm_chip *chip,
> + struct pwm_device *dev,
> + struct pwm_state *state)
> +{
> + struct starfive_pwm_ptc_device *pwm = chip_to_starfive_ptc(chip);
> + u32 period_data, duty_data, ctrl_data;
> +
> + period_data = readl(REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm));
> + duty_data = readl(REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm));
> + ctrl_data = readl(REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
> +
> + state->period = DIV_ROUND_CLOSEST_ULL((u64)period_data * NSEC_PER_SEC, pwm->clk_rate);
> + state->duty_cycle = DIV_ROUND_CLOSEST_ULL((u64)duty_data * NSEC_PER_SEC, pwm->clk_rate);
> + state->polarity = PWM_POLARITY_INVERSED;
> + state->enabled = (ctrl_data & PTC_EN) ? true : false;
> +
> + return 0;
> +}
> +
> +static int starfive_pwm_ptc_apply(struct pwm_chip *chip,
> + struct pwm_device *dev,
> + const struct pwm_state *state)
> +{
> + struct starfive_pwm_ptc_device *pwm = chip_to_starfive_ptc(chip);
> + u32 period_data, duty_data, ctrl_data = 0;
> +
> + if (state->polarity != PWM_POLARITY_INVERSED)
> + return -EINVAL;
> +
> + period_data = DIV_ROUND_CLOSEST_ULL(state->period * pwm->clk_rate,
> + NSEC_PER_SEC);
> + duty_data = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * pwm->clk_rate,
> + NSEC_PER_SEC);
> +
> + writel(period_data, REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm));
> + writel(duty_data, REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm));
> + writel(0, REG_PTC_RPTC_CNTR(pwm->regs, dev->hwpwm));
> +
> + ctrl_data = readl(REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
> + if (state->enabled)
> + writel(ctrl_data | PTC_EN | PTC_OE, REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
> + else
> + writel(ctrl_data & ~(PTC_EN | PTC_OE), REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
> +
> + return 0;
> +}
> +
> +static const struct pwm_ops starfive_pwm_ptc_ops = {
> + .get_state = starfive_pwm_ptc_get_state,
> + .apply = starfive_pwm_ptc_apply,
> + .owner = THIS_MODULE,
> +};
> +
> +static int starfive_pwm_ptc_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct starfive_pwm_ptc_device *pwm;
> + struct pwm_chip *chip;
> + int ret;
> +
> + pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL);
> + if (!pwm)
> + return -ENOMEM;
> +
> + chip = &pwm->chip;
> + chip->dev = dev;
> + chip->ops = &starfive_pwm_ptc_ops;
> + chip->npwm = 8;
> + chip->of_pwm_n_cells = 3;
> +
> + pwm->regs = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(pwm->regs))
> + return dev_err_probe(dev, PTR_ERR(pwm->regs),
> + "Unable to map IO resources\n");
> +
> + pwm->clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(pwm->clk))
> + return dev_err_probe(dev, PTR_ERR(pwm->clk),
> + "Unable to get pwm's clock\n");
I think you can use devm_clk_get_enabled() here and drop the .clk field and
clk_prepare_enable() and clk_disable_unprepare() calls below.
> +
> + pwm->rst = devm_reset_control_get_exclusive(dev, NULL);
> + if (IS_ERR(pwm->rst))
> + return dev_err_probe(dev, PTR_ERR(pwm->rst),
> + "Unable to get pwm's reset\n");
> +
> + ret = clk_prepare_enable(pwm->clk);
> + if (ret) {
> + dev_err(dev,
> + "Failed to enable clock for pwm: %d\n", ret);
> + return ret;
> + }
> +
> + reset_control_deassert(pwm->rst);
This returns an int that you ignore. Please don't do that.
> +
> + pwm->clk_rate = clk_get_rate(pwm->clk);
> + if (pwm->clk_rate <= 0) {
> + dev_warn(dev, "Failed to get APB clock rate\n");
> + return -EINVAL;
> + }
> +
> + ret = devm_pwmchip_add(dev, chip);
> + if (ret < 0) {
> + dev_err(dev, "Cannot register PTC: %d\n", ret);
> + clk_disable_unprepare(pwm->clk);
> + reset_control_assert(pwm->rst);
> + return ret;
> + }
> +
> + platform_set_drvdata(pdev, pwm);
> +
> + return 0;
> +}
> +
> +static int starfive_pwm_ptc_remove(struct platform_device *dev)
> +{
> + struct starfive_pwm_ptc_device *pwm = platform_get_drvdata(dev);
> +
> + reset_control_assert(pwm->rst);
> + clk_disable_unprepare(pwm->clk);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id starfive_pwm_ptc_of_match[] = {
> + { .compatible = "starfive,jh7100-pwm" },
> + { .compatible = "starfive,jh7110-pwm" },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, starfive_pwm_ptc_of_match);
> +
> +static struct platform_driver starfive_pwm_ptc_driver = {
> + .probe = starfive_pwm_ptc_probe,
> + .remove = starfive_pwm_ptc_remove,
> + .driver = {
> + .name = "pwm-starfive-ptc",
> + .of_match_table = starfive_pwm_ptc_of_match,
> + },
> +};
> +module_platform_driver(starfive_pwm_ptc_driver);
> +
> +MODULE_AUTHOR("Jieqin Chen");
> +MODULE_AUTHOR("Hal Feng <hal.feng@starfivetech.com>");
> +MODULE_DESCRIPTION("StarFive PWM PTC driver");
> +MODULE_LICENSE("GPL");
> --
> 2.34.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [RFC v4 2/4] pwm: starfive: Add PWM driver support
2023-09-12 15:04 ` Emil Renner Berthing
@ 2023-09-13 10:57 ` William Qiu
0 siblings, 0 replies; 14+ messages in thread
From: William Qiu @ 2023-09-13 10:57 UTC (permalink / raw)
To: Emil Renner Berthing, devicetree, linux-kernel, linux-riscv,
linux-pwm
Cc: Emil Renner Berthing, Rob Herring, Philipp Zabel, Thierry Reding,
Uwe Kleine-König, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Hal Feng
On 2023/9/12 23:04, Emil Renner Berthing wrote:
> William Qiu wrote:
>> Add Pulse Width Modulation driver support for StarFive
>> JH7100 and JH7110 SoC.
>>
>> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> ---
>> MAINTAINERS | 7 ++
>> drivers/pwm/Kconfig | 9 ++
>> drivers/pwm/Makefile | 1 +
>> drivers/pwm/pwm-starfive-ptc.c | 192 +++++++++++++++++++++++++++++++++
>> 4 files changed, 209 insertions(+)
>> create mode 100644 drivers/pwm/pwm-starfive-ptc.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index d590ce31aa72..0e47818c6f64 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -20299,6 +20299,13 @@ F: drivers/pinctrl/starfive/pinctrl-starfive-jh71*
>> F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
>> F: include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
>>
>> +STARFIVE JH71X0 PWM DRIVERS
>> +M: William Qiu <william.qiu@starfivetech.com>
>> +M: Hal Feng <hal.feng@starfivetech.com>
>> +S: Supported
>> +F: Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml
>> +F: drivers/pwm/pwm-starfive-ptc.c
>> +
>> STARFIVE JH71X0 RESET CONTROLLER DRIVERS
>> M: Emil Renner Berthing <kernel@esmil.dk>
>> M: Hal Feng <hal.feng@starfivetech.com>
>> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
>> index 6210babb0741..48800f33b5c1 100644
>> --- a/drivers/pwm/Kconfig
>> +++ b/drivers/pwm/Kconfig
>> @@ -569,6 +569,15 @@ config PWM_SPRD
>> To compile this driver as a module, choose M here: the module
>> will be called pwm-sprd.
>>
>> +config PWM_STARFIVE_PTC
>> + tristate "StarFive PWM PTC support"
>> + depends on ARCH_STARFIVE || COMPILE_TEST
>> + help
>> + Generic PWM framework driver for StarFive SoCs.
>> +
>> + To compile this driver as a module, choose M here: the module
>> + will be called pwm-starfive-ptc.
>
> What is PTC short for? Are there other PWM peripherals on the JH7100 or JH7110
> that are not PTCs?
>
> If there are both PTC and non-PTC PWMs on these SoCs then the device tree
> compatible strings should reflect that.
>
> If not, maybe just call this driver pwm-starfive / PWM_STARFIVE, or maybe
> pwm-starfive-jh7100 / PWM_STARFIVE_JH7110 if you already know the PWMs on the
> JH81xx will be different.
>
Will update.
>> +
>> config PWM_STI
>> tristate "STiH4xx PWM support"
>> depends on ARCH_STI || COMPILE_TEST
>> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
>> index c822389c2a24..d2b2a3aeea22 100644
>> --- a/drivers/pwm/Makefile
>> +++ b/drivers/pwm/Makefile
>> @@ -52,6 +52,7 @@ obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o
>> obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o
>> obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
>> obj-$(CONFIG_PWM_SPRD) += pwm-sprd.o
>> +obj-$(CONFIG_PWM_STARFIVE_PTC) += pwm-starfive-ptc.o
>> obj-$(CONFIG_PWM_STI) += pwm-sti.o
>> obj-$(CONFIG_PWM_STM32) += pwm-stm32.o
>> obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o
>> diff --git a/drivers/pwm/pwm-starfive-ptc.c b/drivers/pwm/pwm-starfive-ptc.c
>> new file mode 100644
>> index 000000000000..57b5736f6732
>> --- /dev/null
>> +++ b/drivers/pwm/pwm-starfive-ptc.c
>> @@ -0,0 +1,192 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * PWM driver for the StarFive JH71x0 SoC
>> + *
>> + * Copyright (C) 2018-2023 StarFive Technology Co., Ltd.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/io.h>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/pwm.h>
>> +#include <linux/reset.h>
>> +#include <linux/slab.h>
>> +
>> +/* Access PTC register (CNTR, HRC, LRC and CTRL) */
>> +#define REG_PTC_BASE_ADDR_SUB(base, N) \
>> +((base) + (((N) > 3) ? (((N) % 4) * 0x10 + (1 << 15)) : ((N) * 0x10)))
>
> Please indent the line above.
>
Will update.
>> +#define REG_PTC_RPTC_CNTR(base, N) (REG_PTC_BASE_ADDR_SUB(base, N))
>> +#define REG_PTC_RPTC_HRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x4)
>> +#define REG_PTC_RPTC_LRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x8)
>> +#define REG_PTC_RPTC_CTRL(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0xC)
>> +
>> +/* PTC_RPTC_CTRL register bits*/
>> +#define PTC_EN BIT(0)
>> +#define PTC_ECLK BIT(1)
>> +#define PTC_NEC BIT(2)
>> +#define PTC_OE BIT(3)
>> +#define PTC_SIGNLE BIT(4)
>> +#define PTC_INTE BIT(5)
>> +#define PTC_INT BIT(6)
>> +#define PTC_CNTRRST BIT(7)
>> +#define PTC_CAPTE BIT(8)
>> +
>> +struct starfive_pwm_ptc_device {
>> + struct pwm_chip chip;
>> + struct clk *clk;
>> + struct reset_control *rst;
>> + void __iomem *regs;
>> + u32 clk_rate; /* PWM APB clock frequency */
>> +};
>> +
>> +static inline
>> +struct starfive_pwm_ptc_device *chip_to_starfive_ptc(struct pwm_chip *c)
>
> This looks weird. Either just put it on a single line or split between the type
> and function name. Also there was recently a patch to always name pwm_chip
> variables "chip". Eg.
>
> static inline struct starfive_pwm_ptc_device *
> chip_to_starfive_ptc(struct pwm_chip *chip)
> {
>
Will update.
>
>> +{
>> + return container_of(c, struct starfive_pwm_ptc_device, chip);
>> +}
>> +
>> +static int starfive_pwm_ptc_get_state(struct pwm_chip *chip,
>> + struct pwm_device *dev,
>> + struct pwm_state *state)
>> +{
>> + struct starfive_pwm_ptc_device *pwm = chip_to_starfive_ptc(chip);
>> + u32 period_data, duty_data, ctrl_data;
>> +
>> + period_data = readl(REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm));
>> + duty_data = readl(REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm));
>> + ctrl_data = readl(REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
>> +
>> + state->period = DIV_ROUND_CLOSEST_ULL((u64)period_data * NSEC_PER_SEC, pwm->clk_rate);
>> + state->duty_cycle = DIV_ROUND_CLOSEST_ULL((u64)duty_data * NSEC_PER_SEC, pwm->clk_rate);
>> + state->polarity = PWM_POLARITY_INVERSED;
>> + state->enabled = (ctrl_data & PTC_EN) ? true : false;
>> +
>> + return 0;
>> +}
>> +
>> +static int starfive_pwm_ptc_apply(struct pwm_chip *chip,
>> + struct pwm_device *dev,
>> + const struct pwm_state *state)
>> +{
>> + struct starfive_pwm_ptc_device *pwm = chip_to_starfive_ptc(chip);
>> + u32 period_data, duty_data, ctrl_data = 0;
>> +
>> + if (state->polarity != PWM_POLARITY_INVERSED)
>> + return -EINVAL;
>> +
>> + period_data = DIV_ROUND_CLOSEST_ULL(state->period * pwm->clk_rate,
>> + NSEC_PER_SEC);
>> + duty_data = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * pwm->clk_rate,
>> + NSEC_PER_SEC);
>> +
>> + writel(period_data, REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm));
>> + writel(duty_data, REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm));
>> + writel(0, REG_PTC_RPTC_CNTR(pwm->regs, dev->hwpwm));
>> +
>> + ctrl_data = readl(REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
>> + if (state->enabled)
>> + writel(ctrl_data | PTC_EN | PTC_OE, REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
>> + else
>> + writel(ctrl_data & ~(PTC_EN | PTC_OE), REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
>> +
>> + return 0;
>> +}
>> +
>> +static const struct pwm_ops starfive_pwm_ptc_ops = {
>> + .get_state = starfive_pwm_ptc_get_state,
>> + .apply = starfive_pwm_ptc_apply,
>> + .owner = THIS_MODULE,
>> +};
>> +
>> +static int starfive_pwm_ptc_probe(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct starfive_pwm_ptc_device *pwm;
>> + struct pwm_chip *chip;
>> + int ret;
>> +
>> + pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL);
>> + if (!pwm)
>> + return -ENOMEM;
>> +
>> + chip = &pwm->chip;
>> + chip->dev = dev;
>> + chip->ops = &starfive_pwm_ptc_ops;
>> + chip->npwm = 8;
>> + chip->of_pwm_n_cells = 3;
>> +
>> + pwm->regs = devm_platform_ioremap_resource(pdev, 0);
>> + if (IS_ERR(pwm->regs))
>> + return dev_err_probe(dev, PTR_ERR(pwm->regs),
>> + "Unable to map IO resources\n");
>> +
>> + pwm->clk = devm_clk_get(dev, NULL);
>> + if (IS_ERR(pwm->clk))
>> + return dev_err_probe(dev, PTR_ERR(pwm->clk),
>> + "Unable to get pwm's clock\n");
>
> I think you can use devm_clk_get_enabled() here and drop the .clk field and
> clk_prepare_enable() and clk_disable_unprepare() calls below.
>
Will update.
Thanks for taking time to review this patch series.
Best Regards,
William
>> +
>> + pwm->rst = devm_reset_control_get_exclusive(dev, NULL);
>> + if (IS_ERR(pwm->rst))
>> + return dev_err_probe(dev, PTR_ERR(pwm->rst),
>> + "Unable to get pwm's reset\n");
>> +
>> + ret = clk_prepare_enable(pwm->clk);
>> + if (ret) {
>> + dev_err(dev,
>> + "Failed to enable clock for pwm: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + reset_control_deassert(pwm->rst);
>
> This returns an int that you ignore. Please don't do that.
>
>> +
>> + pwm->clk_rate = clk_get_rate(pwm->clk);
>> + if (pwm->clk_rate <= 0) {
>> + dev_warn(dev, "Failed to get APB clock rate\n");
>> + return -EINVAL;
>> + }
>> +
>> + ret = devm_pwmchip_add(dev, chip);
>> + if (ret < 0) {
>> + dev_err(dev, "Cannot register PTC: %d\n", ret);
>> + clk_disable_unprepare(pwm->clk);
>> + reset_control_assert(pwm->rst);
>> + return ret;
>> + }
>> +
>> + platform_set_drvdata(pdev, pwm);
>> +
>> + return 0;
>> +}
>> +
>> +static int starfive_pwm_ptc_remove(struct platform_device *dev)
>> +{
>> + struct starfive_pwm_ptc_device *pwm = platform_get_drvdata(dev);
>> +
>> + reset_control_assert(pwm->rst);
>> + clk_disable_unprepare(pwm->clk);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id starfive_pwm_ptc_of_match[] = {
>> + { .compatible = "starfive,jh7100-pwm" },
>> + { .compatible = "starfive,jh7110-pwm" },
>> + { /* sentinel */ }
>> +};
>> +MODULE_DEVICE_TABLE(of, starfive_pwm_ptc_of_match);
>> +
>> +static struct platform_driver starfive_pwm_ptc_driver = {
>> + .probe = starfive_pwm_ptc_probe,
>> + .remove = starfive_pwm_ptc_remove,
>> + .driver = {
>> + .name = "pwm-starfive-ptc",
>> + .of_match_table = starfive_pwm_ptc_of_match,
>> + },
>> +};
>> +module_platform_driver(starfive_pwm_ptc_driver);
>> +
>> +MODULE_AUTHOR("Jieqin Chen");
>> +MODULE_AUTHOR("Hal Feng <hal.feng@starfivetech.com>");
>> +MODULE_DESCRIPTION("StarFive PWM PTC driver");
>> +MODULE_LICENSE("GPL");
>> --
>> 2.34.1
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 14+ messages in thread
* [RFC v4 3/4] riscv: dts: starfive: jh7110: Add PWM node and pins configuration
2023-08-25 8:13 [RFC v4 0/4] StarFive's Pulse Width Modulation driver support William Qiu
2023-08-25 8:13 ` [RFC v4 1/4] dt-bindings: pwm: Add StarFive PWM module William Qiu
2023-08-25 8:13 ` [RFC v4 2/4] pwm: starfive: Add PWM driver support William Qiu
@ 2023-08-25 8:13 ` William Qiu
2023-08-25 8:13 ` [RFC v4 4/4] riscv: dts: starfive: jh7100: " William Qiu
2023-08-25 15:06 ` [RFC v4 0/4] StarFive's Pulse Width Modulation driver support Conor Dooley
4 siblings, 0 replies; 14+ messages in thread
From: William Qiu @ 2023-08-25 8:13 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-riscv, linux-pwm
Cc: Emil Renner Berthing, Rob Herring, Philipp Zabel, Thierry Reding,
Uwe Kleine-König, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Hal Feng, William Qiu
Add StarFive JH7110 PWM controller node and add PWM pins configuration
on VisionFive 2 board.
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
---
.../jh7110-starfive-visionfive-2.dtsi | 22 +++++++++++++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 ++++++++
2 files changed, 31 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index fa0061eb33a7..eba7331e1fe1 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -143,6 +143,12 @@ &i2c6 {
status = "okay";
};
+&ptc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pins>;
+ status = "okay";
+};
+
&sysgpio {
i2c0_pins: i2c0-0 {
i2c-pins {
@@ -200,6 +206,22 @@ GPOEN_SYS_I2C6_DATA,
};
};
+ pwm_pins: pwm-0 {
+ pwm-pins {
+ pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
+ GPOEN_SYS_PWM0_CHANNEL0,
+ GPI_NONE)>,
+ <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
+ GPOEN_SYS_PWM0_CHANNEL1,
+ GPI_NONE)>;
+ bias-disable;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
uart0_pins: uart0-0 {
tx-pins {
pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index ec2e70011a73..2c808ea3ed40 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -473,6 +473,15 @@ i2c6: i2c@12060000 {
status = "disabled";
};
+ ptc: pwm@120d0000 {
+ compatible = "starfive,jh7110-pwm";
+ reg = <0x0 0x120d0000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
+ resets = <&syscrg JH7110_SYSRST_PWM_APB>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
syscrg: clock-controller@13020000 {
compatible = "starfive,jh7110-syscrg";
reg = <0x0 0x13020000 0x0 0x10000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [RFC v4 4/4] riscv: dts: starfive: jh7100: Add PWM node and pins configuration
2023-08-25 8:13 [RFC v4 0/4] StarFive's Pulse Width Modulation driver support William Qiu
` (2 preceding siblings ...)
2023-08-25 8:13 ` [RFC v4 3/4] riscv: dts: starfive: jh7110: Add PWM node and pins configuration William Qiu
@ 2023-08-25 8:13 ` William Qiu
2023-08-29 7:44 ` Hal Feng
2023-08-29 9:38 ` Emil Renner Berthing
2023-08-25 15:06 ` [RFC v4 0/4] StarFive's Pulse Width Modulation driver support Conor Dooley
4 siblings, 2 replies; 14+ messages in thread
From: William Qiu @ 2023-08-25 8:13 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-riscv, linux-pwm
Cc: Emil Renner Berthing, Rob Herring, Philipp Zabel, Thierry Reding,
Uwe Kleine-König, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Hal Feng, William Qiu
Add StarFive JH7100 PWM controller node and add PWM pins configuration
on VisionFive 2 board.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
---
.../boot/dts/starfive/jh7100-common.dtsi | 24 +++++++++++++++++++
arch/riscv/boot/dts/starfive/jh7100.dtsi | 9 +++++++
2 files changed, 33 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
index b93ce351a90f..746867b882b0 100644
--- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
@@ -84,6 +84,24 @@ GPO_I2C2_PAD_SDA_OEN,
};
};
+ pwm_pins: pwm-0 {
+ pwm-pins {
+ pinmux = <GPIOMUX(7,
+ GPO_PWM_PAD_OUT_BIT0,
+ GPO_PWM_PAD_OE_N_BIT0,
+ GPI_NONE)>,
+ <GPIOMUX(5,
+ GPO_PWM_PAD_OUT_BIT1,
+ GPO_PWM_PAD_OE_N_BIT1,
+ GPI_NONE)>;
+ bias-disable;
+ drive-strength = <35>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
uart3_pins: uart3-0 {
rx-pins {
pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
@@ -154,6 +172,12 @@ &osc_aud {
clock-frequency = <27000000>;
};
+&ptc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pins>;
+ status = "okay";
+};
+
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 4218621ea3b9..7f5bb19e636e 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -248,5 +248,14 @@ watchdog@12480000 {
resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
<&rstgen JH7100_RSTN_WDT>;
};
+
+ ptc: pwm@12490000 {
+ compatible = "starfive,jh7100-pwm";
+ reg = <0x0 0x12490000 0x0 0x10000>;
+ clocks = <&clkgen JH7100_CLK_PWM_APB>;
+ resets = <&rstgen JH7100_RSTN_PWM_APB>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
};
};
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [RFC v4 4/4] riscv: dts: starfive: jh7100: Add PWM node and pins configuration
2023-08-25 8:13 ` [RFC v4 4/4] riscv: dts: starfive: jh7100: " William Qiu
@ 2023-08-29 7:44 ` Hal Feng
2023-08-29 9:38 ` Emil Renner Berthing
1 sibling, 0 replies; 14+ messages in thread
From: Hal Feng @ 2023-08-29 7:44 UTC (permalink / raw)
To: William Qiu, devicetree, linux-kernel, linux-riscv, linux-pwm
Cc: Emil Renner Berthing, Rob Herring, Philipp Zabel, Thierry Reding,
Uwe Kleine-König, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou
On Fri, 25 Aug 2023 16:13:28 +0800, William Qiu wrote:
> Add StarFive JH7100 PWM controller node and add PWM pins configuration
> on VisionFive 2 board.
>
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [RFC v4 4/4] riscv: dts: starfive: jh7100: Add PWM node and pins configuration
2023-08-25 8:13 ` [RFC v4 4/4] riscv: dts: starfive: jh7100: " William Qiu
2023-08-29 7:44 ` Hal Feng
@ 2023-08-29 9:38 ` Emil Renner Berthing
2023-08-29 9:41 ` William Qiu
1 sibling, 1 reply; 14+ messages in thread
From: Emil Renner Berthing @ 2023-08-29 9:38 UTC (permalink / raw)
To: William Qiu
Cc: devicetree, linux-kernel, linux-riscv, linux-pwm,
Emil Renner Berthing, Rob Herring, Philipp Zabel, Thierry Reding,
Uwe Kleine-König, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Hal Feng
On Fri, 25 Aug 2023 at 10:16, William Qiu <william.qiu@starfivetech.com> wrote:
> Add StarFive JH7100 PWM controller node and add PWM pins configuration
> on VisionFive 2 board.
Hi William,
This is the VisionFive V1 board right?
/Emil
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> ---
> .../boot/dts/starfive/jh7100-common.dtsi | 24 +++++++++++++++++++
> arch/riscv/boot/dts/starfive/jh7100.dtsi | 9 +++++++
> 2 files changed, 33 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
> index b93ce351a90f..746867b882b0 100644
> --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
> @@ -84,6 +84,24 @@ GPO_I2C2_PAD_SDA_OEN,
> };
> };
>
> + pwm_pins: pwm-0 {
> + pwm-pins {
> + pinmux = <GPIOMUX(7,
> + GPO_PWM_PAD_OUT_BIT0,
> + GPO_PWM_PAD_OE_N_BIT0,
> + GPI_NONE)>,
> + <GPIOMUX(5,
> + GPO_PWM_PAD_OUT_BIT1,
> + GPO_PWM_PAD_OE_N_BIT1,
> + GPI_NONE)>;
> + bias-disable;
> + drive-strength = <35>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> + };
> +
> uart3_pins: uart3-0 {
> rx-pins {
> pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
> @@ -154,6 +172,12 @@ &osc_aud {
> clock-frequency = <27000000>;
> };
>
> +&ptc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm_pins>;
> + status = "okay";
> +};
> +
> &uart3 {
> pinctrl-names = "default";
> pinctrl-0 = <&uart3_pins>;
> diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
> index 4218621ea3b9..7f5bb19e636e 100644
> --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
> @@ -248,5 +248,14 @@ watchdog@12480000 {
> resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
> <&rstgen JH7100_RSTN_WDT>;
> };
> +
> + ptc: pwm@12490000 {
> + compatible = "starfive,jh7100-pwm";
> + reg = <0x0 0x12490000 0x0 0x10000>;
> + clocks = <&clkgen JH7100_CLK_PWM_APB>;
> + resets = <&rstgen JH7100_RSTN_PWM_APB>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> };
> };
> --
> 2.34.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [RFC v4 4/4] riscv: dts: starfive: jh7100: Add PWM node and pins configuration
2023-08-29 9:38 ` Emil Renner Berthing
@ 2023-08-29 9:41 ` William Qiu
0 siblings, 0 replies; 14+ messages in thread
From: William Qiu @ 2023-08-29 9:41 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: devicetree, linux-kernel, linux-riscv, linux-pwm,
Emil Renner Berthing, Rob Herring, Philipp Zabel, Thierry Reding,
Uwe Kleine-König, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Hal Feng
On 2023/8/29 17:38, Emil Renner Berthing wrote:
> On Fri, 25 Aug 2023 at 10:16, William Qiu <william.qiu@starfivetech.com> wrote:
>> Add StarFive JH7100 PWM controller node and add PWM pins configuration
>> on VisionFive 2 board.
>
> Hi William,
>
> This is the VisionFive V1 board right?
>
> /Emil
>
Hi Emil,
Yes， it's VisionFive V1, I wrote it wrong.
B.R.
William
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> ---
>> .../boot/dts/starfive/jh7100-common.dtsi | 24 +++++++++++++++++++
>> arch/riscv/boot/dts/starfive/jh7100.dtsi | 9 +++++++
>> 2 files changed, 33 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
>> index b93ce351a90f..746867b882b0 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
>> @@ -84,6 +84,24 @@ GPO_I2C2_PAD_SDA_OEN,
>> };
>> };
>>
>> + pwm_pins: pwm-0 {
>> + pwm-pins {
>> + pinmux = <GPIOMUX(7,
>> + GPO_PWM_PAD_OUT_BIT0,
>> + GPO_PWM_PAD_OE_N_BIT0,
>> + GPI_NONE)>,
>> + <GPIOMUX(5,
>> + GPO_PWM_PAD_OUT_BIT1,
>> + GPO_PWM_PAD_OE_N_BIT1,
>> + GPI_NONE)>;
>> + bias-disable;
>> + drive-strength = <35>;
>> + input-disable;
>> + input-schmitt-disable;
>> + slew-rate = <0>;
>> + };
>> + };
>> +
>> uart3_pins: uart3-0 {
>> rx-pins {
>> pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
>> @@ -154,6 +172,12 @@ &osc_aud {
>> clock-frequency = <27000000>;
>> };
>>
>> +&ptc {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pwm_pins>;
>> + status = "okay";
>> +};
>> +
>> &uart3 {
>> pinctrl-names = "default";
>> pinctrl-0 = <&uart3_pins>;
>> diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
>> index 4218621ea3b9..7f5bb19e636e 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
>> @@ -248,5 +248,14 @@ watchdog@12480000 {
>> resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
>> <&rstgen JH7100_RSTN_WDT>;
>> };
>> +
>> + ptc: pwm@12490000 {
>> + compatible = "starfive,jh7100-pwm";
>> + reg = <0x0 0x12490000 0x0 0x10000>;
>> + clocks = <&clkgen JH7100_CLK_PWM_APB>;
>> + resets = <&rstgen JH7100_RSTN_PWM_APB>;
>> + #pwm-cells = <3>;
>> + status = "disabled";
>> + };
>> };
>> };
>> --
>> 2.34.1
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [RFC v4 0/4] StarFive's Pulse Width Modulation driver support
2023-08-25 8:13 [RFC v4 0/4] StarFive's Pulse Width Modulation driver support William Qiu
` (3 preceding siblings ...)
2023-08-25 8:13 ` [RFC v4 4/4] riscv: dts: starfive: jh7100: " William Qiu
@ 2023-08-25 15:06 ` Conor Dooley
2023-08-28 7:12 ` Hal Feng
4 siblings, 1 reply; 14+ messages in thread
From: Conor Dooley @ 2023-08-25 15:06 UTC (permalink / raw)
To: William Qiu
Cc: devicetree, linux-kernel, linux-riscv, linux-pwm,
Emil Renner Berthing, Rob Herring, Philipp Zabel, Thierry Reding,
Uwe Kleine-König, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Hal Feng
[-- Attachment #1: Type: text/plain, Size: 1260 bytes --]
On Fri, Aug 25, 2023 at 04:13:24PM +0800, William Qiu wrote:
> Hi,
>
> This patchset adds initial rudimentary support for the StarFive
> Pulse Width Modulation controller driver. And this driver will
> be used in StarFive's VisionFive 2 board.The first patch add
> Documentations for the device and Patch 2 adds device probe for
> the module.
>
> Changes v3->v4:
> - Rebased to v6.5rc7.
> - Sorted the header files in alphabetic order.
> - Changed iowrite32() to writel().
> - Added a way to turn off.
> - Moified polarity inversion implementation.
> - Added 7100 support.
> - Added dts patches.
> - Used the various helpers in linux/math.h.
> - Corrected formatting problems.
> - Renamed dtbinding to 'starfive,jh7100-pwm.yaml'.
> - Dropped the redundant code.
>
> Changes v2->v3:
> - Fixed some formatting issues.
>
> Changes v1->v2:
> - Renamed the dt-binding 'pwm-starfive.yaml' to 'starfive,jh7110-pwm.yaml'.
> - Dropped the compatible's Items.
> - Dropped the unuse defines.
> - Modified the code to follow the Linux coding style.
> - Changed return value to dev_err_probe.
> - Dropped the unnecessary local variable.
>
> The patch series is based on v6.5rc7.
Out of curiosity, why is this series still an RFC?
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [RFC v4 0/4] StarFive's Pulse Width Modulation driver support
2023-08-25 15:06 ` [RFC v4 0/4] StarFive's Pulse Width Modulation driver support Conor Dooley
@ 2023-08-28 7:12 ` Hal Feng
2023-08-28 7:16 ` Krzysztof Kozlowski
0 siblings, 1 reply; 14+ messages in thread
From: Hal Feng @ 2023-08-28 7:12 UTC (permalink / raw)
To: Conor Dooley, William Qiu
Cc: devicetree, linux-kernel, linux-riscv, linux-pwm,
Emil Renner Berthing, Rob Herring, Philipp Zabel, Thierry Reding,
Uwe Kleine-König, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou
On Fri, 25 Aug 2023 16:06:12 +0100, Conor Dooley wrote:
> On Fri, Aug 25, 2023 at 04:13:24PM +0800, William Qiu wrote:
>> Hi,
>>
>> This patchset adds initial rudimentary support for the StarFive
>> Pulse Width Modulation controller driver. And this driver will
>> be used in StarFive's VisionFive 2 board.The first patch add
>> Documentations for the device and Patch 2 adds device probe for
>> the module.
>>
>> Changes v3->v4:
>> - Rebased to v6.5rc7.
>> - Sorted the header files in alphabetic order.
>> - Changed iowrite32() to writel().
>> - Added a way to turn off.
>> - Moified polarity inversion implementation.
>> - Added 7100 support.
>> - Added dts patches.
>> - Used the various helpers in linux/math.h.
>> - Corrected formatting problems.
>> - Renamed dtbinding to 'starfive,jh7100-pwm.yaml'.
>> - Dropped the redundant code.
>>
>> Changes v2->v3:
>> - Fixed some formatting issues.
>>
>> Changes v1->v2:
>> - Renamed the dt-binding 'pwm-starfive.yaml' to 'starfive,jh7110-pwm.yaml'.
>> - Dropped the compatible's Items.
>> - Dropped the unuse defines.
>> - Modified the code to follow the Linux coding style.
>> - Changed return value to dev_err_probe.
>> - Dropped the unnecessary local variable.
>>
>> The patch series is based on v6.5rc7.
>
> Out of curiosity, why is this series still an RFC?
There was no comments received in v4. So William resend it and
request for comments.
Best regards,
Hal
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [RFC v4 0/4] StarFive's Pulse Width Modulation driver support
2023-08-28 7:12 ` Hal Feng
@ 2023-08-28 7:16 ` Krzysztof Kozlowski
2023-08-28 7:47 ` Hal Feng
0 siblings, 1 reply; 14+ messages in thread
From: Krzysztof Kozlowski @ 2023-08-28 7:16 UTC (permalink / raw)
To: Hal Feng, Conor Dooley, William Qiu
Cc: devicetree, linux-kernel, linux-riscv, linux-pwm,
Emil Renner Berthing, Rob Herring, Philipp Zabel, Thierry Reding,
Uwe Kleine-König, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou
On 28/08/2023 09:12, Hal Feng wrote:
> On Fri, 25 Aug 2023 16:06:12 +0100, Conor Dooley wrote:
>> On Fri, Aug 25, 2023 at 04:13:24PM +0800, William Qiu wrote:
>>> Hi,
>>>
>>> This patchset adds initial rudimentary support for the StarFive
>>> Pulse Width Modulation controller driver. And this driver will
>>> be used in StarFive's VisionFive 2 board.The first patch add
>>> Documentations for the device and Patch 2 adds device probe for
>>> the module.
>>>
>>> Changes v3->v4:
>>> - Rebased to v6.5rc7.
>>> - Sorted the header files in alphabetic order.
>>> - Changed iowrite32() to writel().
>>> - Added a way to turn off.
>>> - Moified polarity inversion implementation.
>>> - Added 7100 support.
>>> - Added dts patches.
>>> - Used the various helpers in linux/math.h.
>>> - Corrected formatting problems.
>>> - Renamed dtbinding to 'starfive,jh7100-pwm.yaml'.
>>> - Dropped the redundant code.
>>>
>>> Changes v2->v3:
>>> - Fixed some formatting issues.
>>>
>>> Changes v1->v2:
>>> - Renamed the dt-binding 'pwm-starfive.yaml' to 'starfive,jh7110-pwm.yaml'.
>>> - Dropped the compatible's Items.
>>> - Dropped the unuse defines.
>>> - Modified the code to follow the Linux coding style.
>>> - Changed return value to dev_err_probe.
>>> - Dropped the unnecessary local variable.
>>>
>>> The patch series is based on v6.5rc7.
>>
>> Out of curiosity, why is this series still an RFC?
>
> There was no comments received in v4. So William resend it and
> request for comments.
The question was: why he requests for comments?
RFC means *it should not be merged, it is not ready*.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [RFC v4 0/4] StarFive's Pulse Width Modulation driver support
2023-08-28 7:16 ` Krzysztof Kozlowski
@ 2023-08-28 7:47 ` Hal Feng
0 siblings, 0 replies; 14+ messages in thread
From: Hal Feng @ 2023-08-28 7:47 UTC (permalink / raw)
To: Krzysztof Kozlowski, Conor Dooley, William Qiu
Cc: devicetree, linux-kernel, linux-riscv, linux-pwm,
Emil Renner Berthing, Rob Herring, Philipp Zabel, Thierry Reding,
Uwe Kleine-König, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou
On 8/28/2023 3:16 PM, Krzysztof Kozlowski wrote:
> On 28/08/2023 09:12, Hal Feng wrote:
>> On Fri, 25 Aug 2023 16:06:12 +0100, Conor Dooley wrote:
>>> On Fri, Aug 25, 2023 at 04:13:24PM +0800, William Qiu wrote:
>>>> Hi,
>>>>
>>>> This patchset adds initial rudimentary support for the StarFive
>>>> Pulse Width Modulation controller driver. And this driver will
>>>> be used in StarFive's VisionFive 2 board.The first patch add
>>>> Documentations for the device and Patch 2 adds device probe for
>>>> the module.
>>>>
>>>> Changes v3->v4:
>>>> - Rebased to v6.5rc7.
>>>> - Sorted the header files in alphabetic order.
>>>> - Changed iowrite32() to writel().
>>>> - Added a way to turn off.
>>>> - Moified polarity inversion implementation.
>>>> - Added 7100 support.
>>>> - Added dts patches.
>>>> - Used the various helpers in linux/math.h.
>>>> - Corrected formatting problems.
>>>> - Renamed dtbinding to 'starfive,jh7100-pwm.yaml'.
>>>> - Dropped the redundant code.
>>>>
>>>> Changes v2->v3:
>>>> - Fixed some formatting issues.
>>>>
>>>> Changes v1->v2:
>>>> - Renamed the dt-binding 'pwm-starfive.yaml' to 'starfive,jh7110-pwm.yaml'.
>>>> - Dropped the compatible's Items.
>>>> - Dropped the unuse defines.
>>>> - Modified the code to follow the Linux coding style.
>>>> - Changed return value to dev_err_probe.
>>>> - Dropped the unnecessary local variable.
>>>>
>>>> The patch series is based on v6.5rc7.
>>>
>>> Out of curiosity, why is this series still an RFC?
>>
>> There was no comments received in v4. So William resend it and
>> request for comments.
>
> The question was: why he requests for comments?
>
> RFC means *it should not be merged, it is not ready*.
Oh, it was misunderstood by William and me.
So this series is not a RFC.
Best regards,
Hal
^ permalink raw reply [flat|nested] 14+ messages in thread