[PATCH v2 0/2] Update DSS EDP integration configuration register

[PATCH v2 0/2] Update DSS EDP integration configuration register

[Harikrishna Shenoy]

This series fixes the size of EDP integration connfiguration register space
for K3 J7-family of SoC's.

Changelog v1 -> v2:
- Removed extra line from commit message.
- Added Reviewed-by tag.
- Added fix for j784s4 as well.

Link v1: https://lore.kernel.org/all/20250904050940.2913567-1-h-shenoy@ti.com

Harikrishna Shenoy (2):
  arm64: dts: ti: k3-j721e-main: Update DSS EDP integration
    configuration register
  arm64: dts: ti: k3-j784s4-j742s2-main-common: Update DSS EDP
    integration configuration register

 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi                | 2 +-
 arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

-- 
2.34.1

[PATCH v2 1/2] arm64: dts: ti: k3-j721e-main: Update DSS EDP integration configuration register

[Harikrishna Shenoy]

Fix size of DSS_EDP0_INT_CFG_VP to 256B as stated in
TRM Table 2-1 MAIN Domain Memory Map.
Link: https://www.ti.com/lit/zip/spruil1/SPRUIL_DRA829_TDA4VM

Fixes: 92c996f4ceab ("arm64: dts: ti: k3-j721e-*: add DP & DP PHY")
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Signed-off-by: Harikrishna Shenoy <h-shenoy@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index ab3666ff4297..3fa7537d5414 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -1863,7 +1863,7 @@ mhdp: dp-bridge@a000000 {
 		 * the PHY driver.
 		 */
 		reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
-		      <0x00 0x04f40000 0x00 0x20>;    /* DSS_EDP0_INTG_CFG_VP */
+		      <0x00 0x04f40000 0x00 0x100>;    /* DSS_EDP0_INTG_CFG_VP */
 		reg-names = "mhdptx", "j721e-intg";
 
 		clocks = <&k3_clks 151 36>;
-- 
2.34.1

Re: [PATCH v2 1/2] arm64: dts: ti: k3-j721e-main: Update DSS EDP integration configuration register

[Beleswar Prasad Padhi]

On 07/09/25 23:58, Harikrishna Shenoy wrote:
> Fix size of DSS_EDP0_INT_CFG_VP to 256B as stated in
> TRM Table 2-1 MAIN Domain Memory Map.
> Link: https://www.ti.com/lit/zip/spruil1/SPRUIL_DRA829_TDA4VM


Gives a 404 on the above link?

Thanks,
Beleswar

>
> Fixes: 92c996f4ceab ("arm64: dts: ti: k3-j721e-*: add DP & DP PHY")
> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
> Signed-off-by: Harikrishna Shenoy <h-shenoy@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> index ab3666ff4297..3fa7537d5414 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> @@ -1863,7 +1863,7 @@ mhdp: dp-bridge@a000000 {
>  		 * the PHY driver.
>  		 */
>  		reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
> -		      <0x00 0x04f40000 0x00 0x20>;    /* DSS_EDP0_INTG_CFG_VP */
> +		      <0x00 0x04f40000 0x00 0x100>;    /* DSS_EDP0_INTG_CFG_VP */
>  		reg-names = "mhdptx", "j721e-intg";
>  
>  		clocks = <&k3_clks 151 36>;

Re: [PATCH v2 1/2] arm64: dts: ti: k3-j721e-main: Update DSS EDP integration configuration register

[Harikrishna Shenoy]

On 9/8/25 10:04, Beleswar Prasad Padhi wrote:
> On 07/09/25 23:58, Harikrishna Shenoy wrote:
>> Fix size of DSS_EDP0_INT_CFG_VP to 256B as stated in
>> TRM Table 2-1 MAIN Domain Memory Map.
>> Link: https://www.ti.com/lit/zip/spruil1/SPRUIL_DRA829_TDA4VM
>
> Gives a 404 on the above link?

https://www.ti.com/lit/zip/spruil1 this downalods the zip, refer SPRUIL_DRA829_TDA4VM file.

>
> Thanks,
> Beleswar
>
>> Fixes: 92c996f4ceab ("arm64: dts: ti: k3-j721e-*: add DP & DP PHY")
>> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
>> Signed-off-by: Harikrishna Shenoy <h-shenoy@ti.com>
>> ---
>>   arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> index ab3666ff4297..3fa7537d5414 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> @@ -1863,7 +1863,7 @@ mhdp: dp-bridge@a000000 {
>>   		 * the PHY driver.
>>   		 */
>>   		reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
>> -		      <0x00 0x04f40000 0x00 0x20>;    /* DSS_EDP0_INTG_CFG_VP */
>> +		      <0x00 0x04f40000 0x00 0x100>;    /* DSS_EDP0_INTG_CFG_VP */
>>   		reg-names = "mhdptx", "j721e-intg";
>>   
>>   		clocks = <&k3_clks 151 36>;

Re: [PATCH v2 1/2] arm64: dts: ti: k3-j721e-main: Update DSS EDP integration configuration register

[Tomi Valkeinen]

Hi,

On 07/09/2025 21:28, Harikrishna Shenoy wrote:
> Fix size of DSS_EDP0_INT_CFG_VP to 256B as stated in
> TRM Table 2-1 MAIN Domain Memory Map.
> Link: https://www.ti.com/lit/zip/spruil1/SPRUIL_DRA829_TDA4VM

What issues does this cause?

 Tomi

> Fixes: 92c996f4ceab ("arm64: dts: ti: k3-j721e-*: add DP & DP PHY")
> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
> Signed-off-by: Harikrishna Shenoy <h-shenoy@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> index ab3666ff4297..3fa7537d5414 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> @@ -1863,7 +1863,7 @@ mhdp: dp-bridge@a000000 {
>  		 * the PHY driver.
>  		 */
>  		reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
> -		      <0x00 0x04f40000 0x00 0x20>;    /* DSS_EDP0_INTG_CFG_VP */
> +		      <0x00 0x04f40000 0x00 0x100>;    /* DSS_EDP0_INTG_CFG_VP */
>  		reg-names = "mhdptx", "j721e-intg";
>  
>  		clocks = <&k3_clks 151 36>;

Re: [PATCH v2 1/2] arm64: dts: ti: k3-j721e-main: Update DSS EDP integration configuration register

[Harikrishna Shenoy]

On 9/8/25 11:46, Tomi Valkeinen wrote:
> Hi,
>
> On 07/09/2025 21:28, Harikrishna Shenoy wrote:
>> Fix size of DSS_EDP0_INT_CFG_VP to 256B as stated in
>> TRM Table 2-1 MAIN Domain Memory Map.
>> Link: https://www.ti.com/lit/zip/spruil1/SPRUIL_DRA829_TDA4VM
> What issues does this cause?
>
>   Tomi

Hi Tomi,

No issues seen in driver functionality yet, but it might when we enable 
HDCP,MST which driver supports but not enabled yet.

so thought it is better to align as per TRM, hence aligning the size as 
per TRM.

>> Fixes: 92c996f4ceab ("arm64: dts: ti: k3-j721e-*: add DP & DP PHY")
>> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
>> Signed-off-by: Harikrishna Shenoy <h-shenoy@ti.com>
>> ---
>>   arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> index ab3666ff4297..3fa7537d5414 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> @@ -1863,7 +1863,7 @@ mhdp: dp-bridge@a000000 {
>>   		 * the PHY driver.
>>   		 */
>>   		reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
>> -		      <0x00 0x04f40000 0x00 0x20>;    /* DSS_EDP0_INTG_CFG_VP */
>> +		      <0x00 0x04f40000 0x00 0x100>;    /* DSS_EDP0_INTG_CFG_VP */
>>   		reg-names = "mhdptx", "j721e-intg";
>>   
>>   		clocks = <&k3_clks 151 36>;

Re: [PATCH v2 1/2] arm64: dts: ti: k3-j721e-main: Update DSS EDP integration configuration register

[Tomi Valkeinen]

On 08/09/2025 09:20, Harikrishna Shenoy wrote:
> 
> On 9/8/25 11:46, Tomi Valkeinen wrote:
>> Hi,
>>
>> On 07/09/2025 21:28, Harikrishna Shenoy wrote:
>>> Fix size of DSS_EDP0_INT_CFG_VP to 256B as stated in
>>> TRM Table 2-1 MAIN Domain Memory Map.
>>> Link: https://www.ti.com/lit/zip/spruil1/SPRUIL_DRA829_TDA4VM
>> What issues does this cause?
>>
>>   Tomi
> 
> Hi Tomi,
> 
> No issues seen in driver functionality yet, but it might when we enable
> HDCP,MST which driver supports but not enabled yet.
> 
> so thought it is better to align as per TRM, hence aligning the size as
> per TRM.

You need to explain this in the patch message. What is the current
behavior/issue, how does this fix it, what are the effects, etc...

Also, here I think it's good to consider what this means for the future
HDCP, MST work you refer to. Is HDCP/MST just adding driver code, no new
DT properties or such needed? If so, what happens when a user runs the
new code with the old dtb, which contains a too small register range?

 Tomi

> 
>>> Fixes: 92c996f4ceab ("arm64: dts: ti: k3-j721e-*: add DP & DP PHY")
>>> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
>>> Signed-off-by: Harikrishna Shenoy <h-shenoy@ti.com>
>>> ---
>>>   arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 +-
>>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/
>>> boot/dts/ti/k3-j721e-main.dtsi
>>> index ab3666ff4297..3fa7537d5414 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>> @@ -1863,7 +1863,7 @@ mhdp: dp-bridge@a000000 {
>>>            * the PHY driver.
>>>            */
>>>           reg = <0x00 0x0a000000 0x00 0x030a00>, /*
>>> DSS_EDP0_V2A_CORE_VP_REGS_APB */
>>> -              <0x00 0x04f40000 0x00 0x20>;    /*
>>> DSS_EDP0_INTG_CFG_VP */
>>> +              <0x00 0x04f40000 0x00 0x100>;    /*
>>> DSS_EDP0_INTG_CFG_VP */
>>>           reg-names = "mhdptx", "j721e-intg";
>>>             clocks = <&k3_clks 151 36>;

Re: [PATCH v2 1/2] arm64: dts: ti: k3-j721e-main: Update DSS EDP integration configuration register

[Kumar, Udit]

On 9/8/2025 11:58 AM, Tomi Valkeinen wrote:
> On 08/09/2025 09:20, Harikrishna Shenoy wrote:
>> On 9/8/25 11:46, Tomi Valkeinen wrote:
>>> Hi,
>>>
>>> On 07/09/2025 21:28, Harikrishna Shenoy wrote:
>>>> Fix size of DSS_EDP0_INT_CFG_VP to 256B as stated in
>>>> TRM Table 2-1 MAIN Domain Memory Map.
>>>> Link: https://www.ti.com/lit/zip/spruil1/SPRUIL_DRA829_TDA4VM
>>> What issues does this cause?
>>>
>>>    Tomi
>> Hi Tomi,
>>
>> No issues seen in driver functionality yet, but it might when we enable
>> HDCP,MST which driver supports but not enabled yet.
>>
>> so thought it is better to align as per TRM, hence aligning the size as
>> per TRM.
> You need to explain this in the patch message. What is the current
> behavior/issue, how does this fix it, what are the effects, etc...
>
> Also, here I think it's good to consider what this means for the future
> HDCP, MST work you refer to. Is HDCP/MST just adding driver code, no new
> DT properties or such needed? If so, what happens when a user runs the
> new code with the old dtb, which contains a too small register range?


we can keep to 256 bytes for completeness, but i don't think registers 
are defined beyond 0x20.


>
>   Tomi
>
>>>> Fixes: 92c996f4ceab ("arm64: dts: ti: k3-j721e-*: add DP & DP PHY")
>>>> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
>>>> Signed-off-by: Harikrishna Shenoy <h-shenoy@ti.com>
>>>> ---
>>>>    arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 +-
>>>>    1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/
>>>> boot/dts/ti/k3-j721e-main.dtsi
>>>> index ab3666ff4297..3fa7537d5414 100644
>>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>>> @@ -1863,7 +1863,7 @@ mhdp: dp-bridge@a000000 {
>>>>             * the PHY driver.
>>>>             */
>>>>            reg = <0x00 0x0a000000 0x00 0x030a00>, /*
>>>> DSS_EDP0_V2A_CORE_VP_REGS_APB */
>>>> -              <0x00 0x04f40000 0x00 0x20>;    /*
>>>> DSS_EDP0_INTG_CFG_VP */
>>>> +              <0x00 0x04f40000 0x00 0x100>;    /*
>>>> DSS_EDP0_INTG_CFG_VP */
>>>>            reg-names = "mhdptx", "j721e-intg";
>>>>              clocks = <&k3_clks 151 36>;

[PATCH v2 2/2] arm64: dts: ti: k3-j784s4-j742s2-main-common: Update DSS EDP integration configuration register

[Harikrishna Shenoy]

Fix size of DSS_EDP0_INT_CFG_VP to 256B as stated in
TRM Table 2-1 MAIN Domain Memory Map.
Link:https://www.ti.com/lit/zip/spruj52/SPRUJ52-J84S4 AM69A TRM

Fixes: 9cc161a4509c ("arm64: dts: ti: Refactor J784s4 SoC files to a common file")
Signed-off-by: Harikrishna Shenoy <h-shenoy@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
index fbbe768e7a30..f0cda14c2530 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
@@ -2573,7 +2573,7 @@ port@1 {
 	mhdp: bridge@a000000 {
 		compatible = "ti,j721e-mhdp8546";
 		reg = <0x0 0xa000000 0x0 0x30a00>,
-		      <0x0 0x4f40000 0x0 0x20>;
+		      <0x0 0x4f40000 0x0 0x100>;
 		reg-names = "mhdptx", "j721e-intg";
 		clocks = <&k3_clks 217 11>;
 		interrupt-parent = <&gic500>;
-- 
2.34.1

Re: [PATCH v2 2/2] arm64: dts: ti: k3-j784s4-j742s2-main-common: Update DSS EDP integration configuration register

[Beleswar Prasad Padhi]

On 07/09/25 23:58, Harikrishna Shenoy wrote:
> Fix size of DSS_EDP0_INT_CFG_VP to 256B as stated in
> TRM Table 2-1 MAIN Domain Memory Map.
> Link:https://www.ti.com/lit/zip/spruj52/SPRUJ52-J84S4 AM69A TRM


Broken link

>
> Fixes: 9cc161a4509c ("arm64: dts: ti: Refactor J784s4 SoC files to a common file")


Above commit only refactored the changes and carried the bug.
The commit that introduced this bug should be:

603669b16701 arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node

Thanks,
Beleswar

> Signed-off-by: Harikrishna Shenoy <h-shenoy@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
> index fbbe768e7a30..f0cda14c2530 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
> @@ -2573,7 +2573,7 @@ port@1 {
>  	mhdp: bridge@a000000 {
>  		compatible = "ti,j721e-mhdp8546";
>  		reg = <0x0 0xa000000 0x0 0x30a00>,
> -		      <0x0 0x4f40000 0x0 0x20>;
> +		      <0x0 0x4f40000 0x0 0x100>;
>  		reg-names = "mhdptx", "j721e-intg";
>  		clocks = <&k3_clks 217 11>;
>  		interrupt-parent = <&gic500>;

Re: [PATCH v2 2/2] arm64: dts: ti: k3-j784s4-j742s2-main-common: Update DSS EDP integration configuration register

[Harikrishna Shenoy]

On 9/8/25 10:07, Beleswar Prasad Padhi wrote:
> On 07/09/25 23:58, Harikrishna Shenoy wrote:
>> Fix size of DSS_EDP0_INT_CFG_VP to 256B as stated in
>> TRM Table 2-1 MAIN Domain Memory Map.
>> Link:https://www.ti.com/lit/zip/spruj52/SPRUJ52-J84S4 AM69A TRM
>
> Broken link

https://www.ti.com/lit/zip/spruj52 , this link will download the zip and refer the SPRUJ52-J84S4 AM69A TRM.

>
>> Fixes: 9cc161a4509c ("arm64: dts: ti: Refactor J784s4 SoC files to a common file")
>
> Above commit only refactored the changes and carried the bug.
> The commit that introduced this bug should be:
>
> 603669b16701 arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node
>
> Thanks,
> Beleswar
Noted
>> Signed-off-by: Harikrishna Shenoy <h-shenoy@ti.com>
>> ---
>>   arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
>> index fbbe768e7a30..f0cda14c2530 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
>> @@ -2573,7 +2573,7 @@ port@1 {
>>   	mhdp: bridge@a000000 {
>>   		compatible = "ti,j721e-mhdp8546";
>>   		reg = <0x0 0xa000000 0x0 0x30a00>,
>> -		      <0x0 0x4f40000 0x0 0x20>;
>> +		      <0x0 0x4f40000 0x0 0x100>;
>>   		reg-names = "mhdptx", "j721e-intg";
>>   		clocks = <&k3_clks 217 11>;
>>   		interrupt-parent = <&gic500>;

Re: [PATCH v2 2/2] arm64: dts: ti: k3-j784s4-j742s2-main-common: Update DSS EDP integration configuration register

[Beleswar Prasad Padhi]

On 08/09/25 10:20, Harikrishna Shenoy wrote:
>
> On 9/8/25 10:07, Beleswar Prasad Padhi wrote:
>> On 07/09/25 23:58, Harikrishna Shenoy wrote:
>>> Fix size of DSS_EDP0_INT_CFG_VP to 256B as stated in
>>> TRM Table 2-1 MAIN Domain Memory Map.
>>> Link:https://www.ti.com/lit/zip/spruj52/SPRUJ52-J84S4 AM69A TRM
>>
>> Broken link
>
> https://www.ti.com/lit/zip/spruj52 , this link will download the zip 


Then maybe put that part only in the link. Otherwise it just shows 404

> and refer the SPRUJ52-J84S4 AM69A TRM.


and put this in the commit message.


Thanks,
Beleswar

>
>>
>>> Fixes: 9cc161a4509c ("arm64: dts: ti: Refactor J784s4 SoC files to a common file")
>>
>> Above commit only refactored the changes and carried the bug.
>> The commit that introduced this bug should be:
>>
>> 603669b16701 arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node
>>
>> Thanks,
>> Beleswar
> Noted
>>> Signed-off-by: Harikrishna Shenoy <h-shenoy@ti.com>
>>> ---
>>>   arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 2 +-
>>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
>>> index fbbe768e7a30..f0cda14c2530 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
>>> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
>>> @@ -2573,7 +2573,7 @@ port@1 {
>>>       mhdp: bridge@a000000 {
>>>           compatible = "ti,j721e-mhdp8546";
>>>           reg = <0x0 0xa000000 0x0 0x30a00>,
>>> -              <0x0 0x4f40000 0x0 0x20>;
>>> +              <0x0 0x4f40000 0x0 0x100>;
>>>           reg-names = "mhdptx", "j721e-intg";
>>>           clocks = <&k3_clks 217 11>;
>>>           interrupt-parent = <&gic500>;