From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CEDA182AE for ; Wed, 4 Oct 2023 14:18:30 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 58743AB; Wed, 4 Oct 2023 07:18:28 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6C5C7DA7; Wed, 4 Oct 2023 07:19:06 -0700 (PDT) Received: from [10.1.196.40] (e121345-lin.cambridge.arm.com [10.1.196.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8454B3F59C; Wed, 4 Oct 2023 07:18:24 -0700 (PDT) Message-ID: Date: Wed, 4 Oct 2023 15:18:23 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux aarch64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH 0/6] RISC-V: Add eMMC support for TH1520 boards Content-Language: en-GB To: Icenowy Zheng , "Lad, Prabhakar" , Jisheng Zhang Cc: Drew Fustini , Christoph Hellwig , Lad Prabhakar , Robert Nelson , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Adrian Hunter , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Jason Kridner , Xi Ruoyao , Han Gao , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Alexandre Ghiti , Linux-MM References: <20230921-th1520-mmc-v1-0-49f76c274fb3@baylibre.com> From: Robin Murphy In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3.4 required=5.0 tests=BAYES_00,NICE_REPLY_A, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net On 04/10/2023 3:02 pm, Icenowy Zheng wrote: [...] >>>> I believe commit 484861e09f3e ("soc: renesas: Kconfig: Select the >>>> required configs for RZ/Five SoC") can cause regression on all >>>> non-dma-coherent riscv platforms with generic defconfig. This is >>>> a common issue. The logic here is: generic riscv defconfig >>>> selects >>>> ARCH_R9A07G043 which selects DMA_GLOBAL_POOL, which assumes all >>>> non-dma-coherent riscv platforms have a dma global pool, this >>>> assumption >>>> seems not correct. And I believe DMA_GLOBAL_POOL should not be >>>> selected by ARCH_SOCFAMILIY, instead, only ARCH under some >>>> specific >>>> conditions can select it globaly, for example NOMMU ARM and so >>>> on. >>>> >>>> Since this is a regression, what's proper fix? any suggestion is >>>> appreciated. >> >> I think the answer is to not select DMA_GLOBAL_POOL, since that is >> only > > Well I think for RISC-V, it's not NOMMU only but applicable for every > core that does not support Svpbmt or vendor-specific alternatives, > because the original RISC-V priv spec does not define memory attributes > in page table entries. > > For the Renesas/Andes case I think a pool is set by OpenSBI with > vendor-specific M-mode facility and then passed in DT, and the S-mode > (which MMU is enabled in) just sees fixed memory attributes, in this > case I think DMA_GLOBAL_POOL is needed. Oh wow, is that really a thing? In that case, either you just can't support this platform in a multi-platform kernel, or someone needs to do some fiddly work in dma-direct to a) introduce the notion of an optional global pool, and b) make it somehow cope with DMA_DIRECT_REMAP being enabled but non-functional. Thanks, Robin.