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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa6260891e4sm120870066b.144.2024.12.05.09.40.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Dec 2024 09:40:53 -0800 (PST) Message-ID: Date: Thu, 5 Dec 2024 18:40:50 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 6/8] arm64: dts: qcom: qcs8300: enable pcie0 for qcs8300 soc To: Ziyue Zhang , vkoul@kernel.org, kishon@kernel.org, robh+dt@kernel.org, manivannan.sadhasivam@linaro.org, bhelgaas@google.com, kw@linux.com, lpieralisi@kernel.org, quic_qianyu@quicinc.com, conor+dt@kernel.org, neil.armstrong@linaro.org, andersson@kernel.org, konradybcio@kernel.org Cc: quic_tsoni@quicinc.com, quic_shashim@quicinc.com, quic_kaushalk@quicinc.com, quic_tdas@quicinc.com, quic_tingweiz@quicinc.com, quic_aiquny@quicinc.com, kernel@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org References: <20241128081056.1361739-1-quic_ziyuzhan@quicinc.com> <20241128081056.1361739-7-quic_ziyuzhan@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20241128081056.1361739-7-quic_ziyuzhan@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: r7IyXlcDkU2-X-YP3iDWaVcF1C1e-grl X-Proofpoint-GUID: r7IyXlcDkU2-X-YP3iDWaVcF1C1e-grl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxscore=0 impostorscore=0 adultscore=0 priorityscore=1501 clxscore=1015 lowpriorityscore=0 suspectscore=0 mlxlogscore=999 malwarescore=0 bulkscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412050129 On 28.11.2024 9:10 AM, Ziyue Zhang wrote: > Add configurations in devicetree for PCIe0, including registers, clocks, > interrupts and phy setting sequence. > > Signed-off-by: Ziyue Zhang > --- > arch/arm64/boot/dts/qcom/qcs8300.dtsi | 175 ++++++++++++++++++++++++++ > 1 file changed, 175 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi > index 2c35f96c3f28..952a84b065c3 100644 > --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi > @@ -637,6 +637,181 @@ mmss_noc: interconnect@17a0000 { > qcom,bcm-voters = <&apps_bcm_voter>; > }; > > + pcie0: pci@1c00000 { > + device_type = "pci"; > + compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; > + reg = <0x0 0x01c00000 0x0 0x3000>, > + <0x0 0x40000000 0x0 0xf20>, > + <0x0 0x40000f20 0x0 0xa8>, > + <0x0 0x40001000 0x0 0x4000>, > + <0x0 0x40100000 0x0 0x100000>, > + <0x0 0x01c03000 0x0 0x1000>; > + reg-names = "parf", > + "dbi", > + "elbi", > + "atu", > + "config", > + "mhi"; > + > + #address-cells = <3>; > + #size-cells = <2>; > + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, > + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; > + bus-range = <0x00 0xff>; > + > + dma-coherent; > + > + linux,pci-domain = <0>; > + num-lanes = <2>; > + > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + ; Weird indent > + Stray newline > + interrupt-names = "msi0", > + "msi1", > + "msi2", > + "msi3", > + "msi4", > + "msi5", > + "msi6", > + "msi7", > + "global"; > + > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0x7>; > + interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, > + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, > + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, > + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, > + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; > + Ditto > + clock-names = "aux", > + "cfg", > + "bus_master", > + "bus_slave", > + "slave_q2a"; > + > + assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; > + assigned-clock-rates = <19200000>; > + > + interconnects = <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; QCOM_ICC_TAG_ACTIVE_ONLY for the cpu-pcie path, both endpoints > + interconnect-names = "pcie-mem", "cpu-pcie"; [...] > + pcie0_phy: phy@1c04000 { > + compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy"; > + reg = <0x0 0x1c04000 0x0 0x2000>; Please pad the address part to 8 hex digits with leading zeroes > + > + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, > + <&gcc GCC_PCIE_CLKREF_EN>, > + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, > + <&gcc GCC_PCIE_0_PIPE_CLK>, > + <&gcc GCC_PCIE_0_PIPEDIV2_CLK>, > + <&gcc GCC_PCIE_0_PHY_AUX_CLK>; > + Ditto > + clock-names = "cfg_ahb", > + "ref", > + "rchng", > + "pipe", > + "pipediv2", > + The same for pcie1 Konrad