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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ade1d754632sm722896866b.26.2025.06.10.06.24.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Jun 2025 06:24:15 -0700 (PDT) Message-ID: Date: Tue, 10 Jun 2025 15:24:13 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: qcom: qcs615: disable the CTI device of the camera block To: Jie Gan , Jie Gan , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Tingwei Zhang , Jinlong Mao , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250527015224.7343-1-jie.gan@oss.qualcomm.com> <5fbb515a-c3d0-4bbe-a689-41e730ecd952@oss.qualcomm.com> <9a156925-cf7b-4d2e-88a8-fdfed5528553@quicinc.com> <1fef810c-47fe-4f6d-95bc-0d72dbd63bf0@oss.qualcomm.com> <79f5e42f-f857-4247-abf9-d0f3f5c1a498@quicinc.com> <405f0432-3f07-45be-8511-06235dcd84d0@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <405f0432-3f07-45be-8511-06235dcd84d0@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: tOXGYxr2WBUk19s2WTkjeXwSIrSfW0Fh X-Authority-Analysis: v=2.4 cv=TsLmhCXh c=1 sm=1 tr=0 ts=68483202 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=P-IC7800AAAA:8 a=jKJs8sBhnlDJ8AvWEW4A:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=d3PnA9EDa4IxuAV0gXij:22 X-Proofpoint-GUID: tOXGYxr2WBUk19s2WTkjeXwSIrSfW0Fh X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjEwMDEwNSBTYWx0ZWRfX9QfARq1b1J22 1fVdR25gUCUZh80afQ86sSbEh1eHg3e5zuURXmFnkpdR3H7kw8swRyVEu6FlNuZKBJzHQ+dCuSR L6QhYSZTl/gpdtYgxhYOFDbTiMunFdNUUS0QaTnagIwsclLngqnrxLMerPYh2cxrrTHXkkxPDue PyBgxMt1c+WQhFqeRoZb7bZYtmX/qjHY4qnMkzjBb5u5KTGivqgWQN1VK8MySFkS8A8Uy68RLT0 bx4ZauJEHciGVUmLIh2WycdNHADs6VZH5ipHC7TRcoW3+cwnVlL8Z1Otz0tr/rvLID7D0V73fbq 0ssGI4xmgnOrDhrIEBQCTcF37weqHFPOQhnsFVKFgZZQ5YpObEG22MfxCDLOkoYP/bMKrjT3R52 FzZ8o9qsai93ZK3QWi7Njq1jg5JhY0FuJNwZVEL6p/8/+Fc+vEVYtW7mQs2kx7d9YGFRyE27 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-10_05,2025-06-10_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 spamscore=0 mlxlogscore=947 impostorscore=0 priorityscore=1501 bulkscore=0 adultscore=0 clxscore=1015 mlxscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506100105 On 6/3/25 5:17 AM, Jie Gan wrote: > > > On 5/31/2025 7:05 AM, Konrad Dybcio wrote: >> On 5/28/25 5:02 AM, Jie Gan wrote: >>> >>> >>> On 5/27/2025 6:41 PM, Konrad Dybcio wrote: >>>> On 5/27/25 12:32 PM, Jie Gan wrote: >>>>> >>>>> >>>>> On 5/27/2025 6:23 PM, Konrad Dybcio wrote: >>>>>> On 5/27/25 3:52 AM, Jie Gan wrote: >>>>>>> Disable the CTI device of the camera block to prevent potential NoC errors >>>>>>> during AMBA bus device matching. >>>>>>> >>>>>>> The clocks for the Qualcomm Debug Subsystem (QDSS) are managed by aoss_qmp >>>>>>> through a mailbox. However, the camera block resides outside the AP domain, >>>>>>> meaning its QDSS clock cannot be controlled via aoss_qmp. >>>>>> >>>>>> Which clock drives it then? >>>>> >>>>> It's qcom,aoss-qmp. >>>>> >>>>> clk_prepare->qmp_qdss_clk_prepare >>>>> https://elixir.bootlin.com/linux/v6.15-rc7/source/drivers/soc/qcom/qcom_aoss.c#L280 >>>> >>>> I'm confused about this part: >>>> >>>>> However, the camera block resides outside the AP domain, >>>>> meaning its QDSS clock cannot be controlled via aoss_qmp. >>>> >>>> Do we need to poke the QMP of another DRV? >>> >>> The AOSS has a clock control register for all QDSS clocks. when we vote the qdss clock, the aoss_qmp driver will send a message to AOSS to enable the clock control register, then the clock control register will enable all QDSS clocks. >>> >>> The QDSS clock is not a single clock source, it is a term that representing all the clock sources utilized by the QDSS. >> >> What I'm trying to ask is, is there any way we could enable that >> clock from Linux? Can the camera hw turn these on? Maybe we could >> trick it into enabling them? > > There is a power issue if we keep the debug clock on with a long time. > > We had a discussion with AOP to check if possible to add the debug clock of titan to the QDSS clock list, but they need time to evaluate it. Changing the firmware is a band-aid solution, as the update will never reach millions of devices on the market. I'm curious in whether there's any way (or os-accessible debug register) to manage the necessary clocks from Linux, as a workaround. > From Coresight view, what we can do by now is disable it in DT to prevent the unexpected NoC error. How about something like this: diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index bb8b6c3ebd03..fc2ab750f2cd 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -2461,6 +2461,9 @@ cti@6c13000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + + /* Not all required clocks can be enabled from the OS */ + status = "fail"; }; cti@6c20000 { Konrad