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[188.155.201.27]) by smtp.googlemail.com with ESMTPSA id v2-20020a509d02000000b00412d53177a6sm3179787ede.20.2022.03.25.10.34.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 25 Mar 2022 10:34:30 -0700 (PDT) Message-ID: Date: Fri, 25 Mar 2022 18:34:29 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH 1/2] dt-bindings: arm: add corstone1000 platform Content-Language: en-US To: Rui Miguel Silva , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org References: <20220325133655.4177977-1-rui.silva@linaro.org> <20220325133655.4177977-2-rui.silva@linaro.org> From: Krzysztof Kozlowski In-Reply-To: <20220325133655.4177977-2-rui.silva@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 25/03/2022 14:36, Rui Miguel Silva wrote: > Add bindings to describe the FPGA in a prototyping board > (MPS3) implementation and the Fixed Virtual Platform > implementation of the ARM Corstone1000 platform. > > Signed-off-by: Rui Miguel Silva > --- > .../bindings/arm/arm,corstone1000.yaml | 45 +++++++++++++++++++ > 1 file changed, 45 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/arm,corstone1000.yaml > > diff --git a/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml > new file mode 100644 > index 000000000000..a77f88223801 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml > @@ -0,0 +1,45 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/arm,corstone1000.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ARM Corstone1000 Device Tree Bindings > + > +maintainers: > + - Vishnu Banavath > + - Rui Miguel Silva > + > +description: |+ > + ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that > + provides a flexible compute architecture that combines Cortex‑A and Cortex‑M > + processors. > + > + Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion > + systems for M-Class (or other) processors for adding sensors, connectivity, > + video, audio and machine learning at the edge System and security IPs to build > + a secure SoC for a range of rich IoT applications, for example gateways, smart > + cameras and embedded systems. > + > + Integrated Secure Enclave providing hardware Root of Trust and supporting > + seamless integration of the optional CryptoCell™-312 cryptographic > + accelerator. > + > +properties: > + $nodename: > + const: '/' > + compatible: > + oneOf: > + - description: Corstone1000 MPS3 it has 1 Cortex-A35 CPU core in a FPGA > + implementation of the Corstone1000 in the MPS3 prototyping board. See > + ARM document DAI0550. > + items: > + - const: arm,corstone1000-mps3 If I understood correctly your description and DAI0550, the MPS3 board is a board with Corstone 100, so you miss here compatible for the chip (e.g. arm,corstone1000). I guess similar pattern for the FVP, so both should be combined within an enum (skipping all this description). Best regards, Krzysztof