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[83.9.31.184]) by smtp.gmail.com with ESMTPSA id b11-20020a056512070b00b004a45edc1de2sm2209319lfs.239.2022.12.27.04.08.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 27 Dec 2022 04:08:57 -0800 (PST) Message-ID: Date: Tue, 27 Dec 2022 13:08:55 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [RFC PATCH 12/12] ARM: dts: qcom: apq8084: add clocks and clock-names to gcc device Content-Language: en-US To: Dmitry Baryshkov , Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org References: <20221227013225.2847382-1-dmitry.baryshkov@linaro.org> <20221227013225.2847382-13-dmitry.baryshkov@linaro.org> From: Konrad Dybcio In-Reply-To: <20221227013225.2847382-13-dmitry.baryshkov@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 27.12.2022 02:32, Dmitry Baryshkov wrote: > Add clocks and clock-names nodes to the gcc device to bind clocks using > the DT links. > > Signed-off-by: Dmitry Baryshkov > --- Reviewed-by: Konrad Dybcio Though - again at the end of reviewing - I noticed you could have gone .index instead, like with qcs404. Konrad > arch/arm/boot/dts/qcom-apq8084.dtsi | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi > index fe30abfff90a..815b6c53f7b8 100644 > --- a/arch/arm/boot/dts/qcom-apq8084.dtsi > +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi > @@ -388,6 +388,24 @@ gcc: clock-controller@fc400000 { > #reset-cells = <1>; > #power-domain-cells = <1>; > reg = <0xfc400000 0x4000>; > + clocks = <&xo_board>, > + <&sleep_clk>, > + <0>, /* ufs */ > + <0>, > + <0>, > + <0>, > + <0>, /* sata */ > + <0>, > + <0>; /* pcie */ > + clock-names = "xo", > + "sleep_clk", > + "ufs_rx_symbol_0_clk_src", > + "ufs_rx_symbol_1_clk_src", > + "ufs_tx_symbol_0_clk_src", > + "ufs_tx_symbol_1_clk_src", > + "sata_asic0_clk", > + "sata_rx_clk", > + "pcie_pipe"; > }; > > tcsr_mutex: hwlock@fd484000 {