From: Xingyu Wu <xingyu.wu@starfivetech.com>
To: Conor Dooley <conor@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>
Cc: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
<mturquette@baylibre.com>, <sboyd@kernel.org>,
<p.zabel@pengutronix.de>, <kernel@esmil.dk>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>, <aou@eecs.berkeley.edu>,
<hal.feng@starfivetech.com>, <linux-kernel@vger.kernel.org>,
<linux-clk@vger.kernel.org>
Subject: Re: [PATCH v7 0/9] Add STG/ISP/VOUT clock and reset drivers for StarFive JH7110
Date: Thu, 13 Jul 2023 11:43:02 +0800 [thread overview]
Message-ID: <a6bdf17f-dd05-0237-92f4-7fc5115e4bef@starfivetech.com> (raw)
In-Reply-To: <20230712-unsold-impound-02608d701dfb@spud>
On 2023/7/13 1:01, Conor Dooley wrote:
> On Wed, Jul 12, 2023 at 09:50:37AM -0700, Palmer Dabbelt wrote:
>> On Wed, 12 Jul 2023 02:19:58 PDT (-0700), xingyu.wu@starfivetech.com wrote:
>> > This patch serises are base on the basic JH7110 SYSCRG/AONCRG
>> > drivers and add new partial clock drivers and reset supports
>> > about System-Top-Group(STG), Image-Signal-Process(ISP)
>> > and Video-Output(VOUT) for the StarFive JH7110 RISC-V SoC. These
>> > clocks and resets could be used by DMA, VIN and Display modules.
>
>> Happy to take it through the RISC-V tree if folks want, but IMO it's
>> probably better aimed at the clock/reset folks. Either way I'd want to give
>> them a chance to ack/review it, so I'm going to drop it from my list.
>>
>> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
>
> I had a look through it & I am generally happy with it - everything has
> either an R-b from DT folk or Hal on the drivers.
> I was going to propose the same thing as the PLL patchset - if Emil is
> happy with it, then I intend sending Stephen a PR for the drivers &
> bindings.
>
Thanks, I will send a new version soon with some modification from Emil's comments.
Best regards,
Xingyu Wu
prev parent reply other threads:[~2023-07-13 3:46 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-12 9:19 [PATCH v7 0/9] Add STG/ISP/VOUT clock and reset drivers for StarFive JH7110 Xingyu Wu
2023-07-12 9:19 ` [PATCH v7 1/9] dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator Xingyu Wu
2023-07-12 17:49 ` Emil Renner Berthing
2023-07-12 9:20 ` [PATCH v7 2/9] clk: starfive: Add StarFive JH7110 System-Top-Group clock driver Xingyu Wu
2023-07-12 17:50 ` Emil Renner Berthing
2023-07-13 9:54 ` Xingyu Wu
2023-07-13 10:05 ` Emil Renner Berthing
2023-07-12 9:20 ` [PATCH v7 3/9] dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator Xingyu Wu
2023-07-12 17:51 ` Emil Renner Berthing
2023-07-12 9:20 ` [PATCH v7 4/9] clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver Xingyu Wu
2023-07-12 17:59 ` Emil Renner Berthing
2023-07-13 2:12 ` Xingyu Wu
2023-07-12 9:20 ` [PATCH v7 5/9] dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator Xingyu Wu
2023-07-12 17:48 ` Emil Renner Berthing
2023-07-12 9:20 ` [PATCH v7 6/9] clk: starfive: Add StarFive JH7110 Video-Output clock driver Xingyu Wu
2023-07-12 18:08 ` Emil Renner Berthing
2023-07-13 2:14 ` Xingyu Wu
2023-07-12 9:20 ` [PATCH v7 7/9] reset: starfive: jh7110: Add StarFive STG/ISP/VOUT resets support Xingyu Wu
2023-07-12 18:09 ` Emil Renner Berthing
2023-07-12 9:20 ` [PATCH v7 8/9] riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks Xingyu Wu
2023-07-12 18:10 ` Emil Renner Berthing
2023-07-12 9:20 ` [PATCH v7 9/9] riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes Xingyu Wu
2023-07-12 18:11 ` Emil Renner Berthing
2023-07-12 16:50 ` [PATCH v7 0/9] Add STG/ISP/VOUT clock and reset drivers for StarFive JH7110 Palmer Dabbelt
2023-07-12 17:01 ` Conor Dooley
2023-07-13 3:43 ` Xingyu Wu [this message]
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