[net-next PATCH 0/3] net: mdio-ipq4019: fix wrong default MDC rate

[net-next PATCH 0/3] net: mdio-ipq4019: fix wrong default MDC rate

[Christian Marangi]

This was a long journey to arrive and discover this problem.

To not waste too much char, there is a race problem with PHY and driver
probe. This was observed with Aquantia PHY firmware loading.

With some hacks the race problem was workarounded but an interesting
thing was notice. It took more than a minute for the firmware to load
via MDIO.

This was strange as the same operation was done by UBoot in at max 5
second and the same data was loaded.

A similar problem was observed on a mtk board that also had an
Aquantia PHY where the load was very slow. It was notice that the cause
was the MDIO bus running at a very low speed and the firmware
was missing a property (present in mtk sdk) that set the right frequency
to the MDIO bus.

It was fun to find that THE VERY SAME PROBLEM is present on IPQ in a
different form. The MDIO apply internally a division to the feed clock
resulting in the bus running at 390KHz instead of 6.25Mhz.

Searching around the web for some documentation and some include and
analyzing the uboot codeflow resulted in the divider being set wrongly
at /256 instead of /16 as the value was actually never set.
Applying the value restore the original load time for the Aquantia PHY.

This series mainly handle this by adding support for the "clock-frequency"
property.

Christian Marangi (3):
  dt-bindings: net: ipq4019-mdio: document now supported clock-frequency
  net: mdio: ipq4019: add support for clock-frequency property
  arm64: dts: qcom: ipq8074: add clock-frequency to MDIO node

 .../bindings/net/qcom,ipq4019-mdio.yaml       | 10 +++
 arch/arm64/boot/dts/qcom/ipq8074.dtsi         |  2 +
 drivers/net/mdio/mdio-ipq4019.c               | 68 +++++++++++++++++--
 3 files changed, 75 insertions(+), 5 deletions(-)

-- 
2.43.0

[net-next PATCH 1/3] dt-bindings: net: ipq4019-mdio: document now supported clock-frequency

[Christian Marangi]

Document support for clock-frequency and add details on why this
property is needed and what values are supported.

From internal documentation, while other values are supported, the
correct function of the MDIO bus is not assured hence add only the
suggested supported values to the property enum.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 .../devicetree/bindings/net/qcom,ipq4019-mdio.yaml     | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml b/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml
index 3407e909e8a7..603dbfb95ac9 100644
--- a/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml
+++ b/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml
@@ -44,6 +44,16 @@ properties:
     items:
       - const: gcc_mdio_ahb_clk
 
+  clock-frequency:
+    description:
+      The MDIO bus clock that must be output by the MDIO bus hardware, if
+      absent, the default hardware values are used.
+
+      MDC rate is feed by an external clock (fixed 100MHz) and is divider
+      internally. The default divider is /256 resulting in the default rate
+      applied of 390KHz.
+    enum: [ 390625, 781250, 1562500, 3125000, 6250000, 12500000 ]
+
 required:
   - compatible
   - reg
-- 
2.43.0

Re: [net-next PATCH 1/3] dt-bindings: net: ipq4019-mdio: document now supported clock-frequency

[Andrew Lunn]

> +  clock-frequency:
> +    description:
> +      The MDIO bus clock that must be output by the MDIO bus hardware, if
> +      absent, the default hardware values are used.
> +
> +      MDC rate is feed by an external clock (fixed 100MHz) and is divider
> +      internally. The default divider is /256 resulting in the default rate
> +      applied of 390KHz.
> +    enum: [ 390625, 781250, 1562500, 3125000, 6250000, 12500000 ]

Hi Christian

802.3 says the clock should be up to 2.5MHz by default. So the nearest
would be 1562500. Please document that if not set, it defaults to
this. And make the driver actually default to that.

	Andrew

Re: [net-next PATCH 1/3] dt-bindings: net: ipq4019-mdio: document now supported clock-frequency

[Christian Marangi]

On Wed, Jan 24, 2024 at 11:23:05PM +0100, Andrew Lunn wrote:
> > +  clock-frequency:
> > +    description:
> > +      The MDIO bus clock that must be output by the MDIO bus hardware, if
> > +      absent, the default hardware values are used.
> > +
> > +      MDC rate is feed by an external clock (fixed 100MHz) and is divider
> > +      internally. The default divider is /256 resulting in the default rate
> > +      applied of 390KHz.
> > +    enum: [ 390625, 781250, 1562500, 3125000, 6250000, 12500000 ]
> 
> Hi Christian
> 
> 802.3 says the clock should be up to 2.5MHz by default. So the nearest
> would be 1562500. Please document that if not set, it defaults to
> this. And make the driver actually default to that.
>

As I said, this is very fk up and default value is 390KHz unless anyone
in the chain sets it (sometime uboot does it but it's not that common...
default qsdk uboot doesn't do that for example)... Ok I have to change
this to default to 1562500.

-- 
	Ansuel

Re: [net-next PATCH 1/3] dt-bindings: net: ipq4019-mdio: document now supported clock-frequency

[Andrew Lunn]

On Wed, Jan 24, 2024 at 11:27:20PM +0100, Christian Marangi wrote:
> On Wed, Jan 24, 2024 at 11:23:05PM +0100, Andrew Lunn wrote:
> > > +  clock-frequency:
> > > +    description:
> > > +      The MDIO bus clock that must be output by the MDIO bus hardware, if
> > > +      absent, the default hardware values are used.
> > > +
> > > +      MDC rate is feed by an external clock (fixed 100MHz) and is divider
> > > +      internally. The default divider is /256 resulting in the default rate
> > > +      applied of 390KHz.
> > > +    enum: [ 390625, 781250, 1562500, 3125000, 6250000, 12500000 ]
> > 
> > Hi Christian
> > 
> > 802.3 says the clock should be up to 2.5MHz by default. So the nearest
> > would be 1562500. Please document that if not set, it defaults to
> > this. And make the driver actually default to that.
> >
> 
> As I said, this is very fk up and default value is 390KHz unless anyone
> in the chain sets it (sometime uboot does it but it's not that common...
> default qsdk uboot doesn't do that for example)... Ok I have to change
> this to default to 1562500.

I doubt you will cause any regression by defaulting to 2.5HHz
instead. That is what the standard says it should be. All devices on
the bus should support that.

    Andrew

Re: [net-next PATCH 1/3] dt-bindings: net: ipq4019-mdio: document now supported clock-frequency

[Krzysztof Kozlowski]

On 24/01/2024 22:36, Christian Marangi wrote:
> Document support for clock-frequency and add details on why this
> property is needed and what values are supported.


...

> +  clock-frequency:
> +    description:
> +      The MDIO bus clock that must be output by the MDIO bus hardware, if
> +      absent, the default hardware values are used.
> +
> +      MDC rate is feed by an external clock (fixed 100MHz) and is divider
> +      internally. The default divider is /256 resulting in the default rate
> +      applied of 390KHz.
> +    enum: [ 390625, 781250, 1562500, 3125000, 6250000, 12500000 ]

default: 390625

Best regards,
Krzysztof

[net-next PATCH 2/3] net: mdio: ipq4019: add support for clock-frequency property

[Christian Marangi]

The IPQ4019 MDIO internally divide the clock feed by AHB based on the
MDIO_MODE reg. On reset or power up, the default value for the
divider is 0xff that reflect the divider set to /256.

This makes the MDC run at a very low rate, that is, considering AHB is
always fixed to 100Mhz, a value of 390KHz.

This hasn't have been a problem as MDIO wasn't used for time sensitive
operation, it is now that on IPQ807x is usually mounted with PHY that
requires MDIO to load their firmware (example Aquantia PHY).

To handle this problem and permit to set the correct designed MDC
frequency for the SoC add support for the standard "clock-frequency"
property for the MDIO node.

The divider supports value from /1 to /256 and the common value are to
set it to /16 to reflect 6.25Mhz or to /8 on newer platform to reflect
12.5Mhz.

To scan if the requested rate is supported by the divider, loop with
each supported divider and stop when the requested rate match the final
rate with the current divider. An error is returned if the rate doesn't
match any value.

On MDIO reset, the divider is restored to the requested value to prevent
any kind of downclocking caused by the divider reverting to a default
value.

While at is also document other bits of the MDIO_MODE reg to have a
clear idea of what is actually applied there.

Documentation of some BITs is skipped as they are marked as reserved and
their usage is not clear (RES 11:9 GENPHY 16:13 RES1 19:17)

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/net/mdio/mdio-ipq4019.c | 68 ++++++++++++++++++++++++++++++---
 1 file changed, 63 insertions(+), 5 deletions(-)

diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c
index abd8b508ec16..a4c6cf901ac2 100644
--- a/drivers/net/mdio/mdio-ipq4019.c
+++ b/drivers/net/mdio/mdio-ipq4019.c
@@ -14,6 +14,20 @@
 #include <linux/clk.h>
 
 #define MDIO_MODE_REG				0x40
+#define   MDIO_MODE_MDC_MODE			BIT(12)
+/* 0 = Clause 22, 1 = Clause 45 */
+#define   MDIO_MODE_C45				BIT(8)
+#define   MDIO_MODE_DIV_MASK			GENMASK(7, 0)
+#define     MDIO_MODE_DIV(x)			FIELD_PREP(MDIO_MODE_DIV_MASK, (x) - 1)
+#define     MDIO_MODE_DIV_1			FIELD_PREP(MDIO_MODE_DIV_MASK, 0x0)
+#define     MDIO_MODE_DIV_2			FIELD_PREP(MDIO_MODE_DIV_MASK, 0x1)
+#define     MDIO_MODE_DIV_4			FIELD_PREP(MDIO_MODE_DIV_MASK, 0x3)
+#define     MDIO_MODE_DIV_8			FIELD_PREP(MDIO_MODE_DIV_MASK, 0x7)
+#define     MDIO_MODE_DIV_16			FIELD_PREP(MDIO_MODE_DIV_MASK, 0xf)
+#define     MDIO_MODE_DIV_32			FIELD_PREP(MDIO_MODE_DIV_MASK, 0x1f)
+#define     MDIO_MODE_DIV_64			FIELD_PREP(MDIO_MODE_DIV_MASK, 0x3f)
+#define     MDIO_MODE_DIV_128			FIELD_PREP(MDIO_MODE_DIV_MASK, 0x7f)
+#define     MDIO_MODE_DIV_256			FIELD_PREP(MDIO_MODE_DIV_MASK, 0xff)
 #define MDIO_ADDR_REG				0x44
 #define MDIO_DATA_WRITE_REG			0x48
 #define MDIO_DATA_READ_REG			0x4c
@@ -26,9 +40,6 @@
 #define MDIO_CMD_ACCESS_CODE_C45_WRITE	1
 #define MDIO_CMD_ACCESS_CODE_C45_READ	2
 
-/* 0 = Clause 22, 1 = Clause 45 */
-#define MDIO_MODE_C45				BIT(8)
-
 #define IPQ4019_MDIO_TIMEOUT	10000
 #define IPQ4019_MDIO_SLEEP		10
 
@@ -41,6 +52,7 @@ struct ipq4019_mdio_data {
 	void __iomem	*membase;
 	void __iomem *eth_ldo_rdy;
 	struct clk *mdio_clk;
+	unsigned int mdc_rate;
 };
 
 static int ipq4019_mdio_wait_busy(struct mii_bus *bus)
@@ -203,6 +215,38 @@ static int ipq4019_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum,
 	return 0;
 }
 
+static int ipq4019_mdio_set_div(struct ipq4019_mdio_data *priv)
+{
+	unsigned long ahb_rate;
+	int div;
+	u32 val;
+
+	/* If we don't have a clock for AHB use the fixed value */
+	ahb_rate = IPQ_MDIO_CLK_RATE;
+	if (priv->mdio_clk)
+		ahb_rate = clk_get_rate(priv->mdio_clk);
+
+	/* MDC rate is ahb_rate/(MDIO_MODE_DIV + 1)
+	 * While supported, internal documentation doesn't
+	 * assure correct functionality of the MDIO bus
+	 * with divider of 1, 2 or 4.
+	 */
+	for (div = 8; div <= 256; div *= 2) {
+		/* The requested rate is supported by the div */
+		if (priv->mdc_rate == ahb_rate / div) {
+			val = readl(priv->membase + MDIO_MODE_REG);
+			val &= ~MDIO_MODE_DIV_MASK;
+			val |= MDIO_MODE_DIV(div);
+			writel(val, priv->membase + MDIO_MODE_REG);
+
+			return 0;
+		}
+	}
+
+	/* The requested rate is not supported */
+	return -EINVAL;
+}
+
 static int ipq_mdio_reset(struct mii_bus *bus)
 {
 	struct ipq4019_mdio_data *priv = bus->priv;
@@ -225,8 +269,14 @@ static int ipq_mdio_reset(struct mii_bus *bus)
 		return ret;
 
 	ret = clk_prepare_enable(priv->mdio_clk);
-	if (ret == 0)
-		mdelay(10);
+	if (ret)
+		return ret;
+
+	mdelay(10);
+
+	/* Restore MDC rate if previously set */
+	if (priv->mdc_rate)
+		ret = ipq4019_mdio_set_div(priv);
 
 	return ret;
 }
@@ -252,6 +302,14 @@ static int ipq4019_mdio_probe(struct platform_device *pdev)
 	if (IS_ERR(priv->mdio_clk))
 		return PTR_ERR(priv->mdio_clk);
 
+	priv->mdc_rate = 0;
+	if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
+				  &priv->mdc_rate)) {
+		ret = ipq4019_mdio_set_div(priv);
+		if (ret)
+			return ret;
+	}
+
 	/* The platform resource is provided on the chipset IPQ5018 */
 	/* This resource is optional */
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-- 
2.43.0

[net-next PATCH 3/3] arm64: dts: qcom: ipq8074: add clock-frequency to MDIO node

[Christian Marangi]

Add clock-frequency to MDIO node to set the MDC rate to 6.25Mhz instead
of using the default value of 390KHz from MDIO default divider.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 2f275c84e566..08ddfeece043 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -264,6 +264,8 @@ mdio: mdio@90000 {
 			clocks = <&gcc GCC_MDIO_AHB_CLK>;
 			clock-names = "gcc_mdio_ahb_clk";
 
+			clock-frequency = <6250000>;
+
 			status = "disabled";
 		};
 
-- 
2.43.0

Re: [net-next PATCH 0/3] net: mdio-ipq4019: fix wrong default MDC rate

[Jie Luo]

On 1/25/2024 5:36 AM, Christian Marangi wrote:
> This was a long journey to arrive and discover this problem.
> 
> To not waste too much char, there is a race problem with PHY and driver
> probe. This was observed with Aquantia PHY firmware loading.
> 
> With some hacks the race problem was workarounded but an interesting
> thing was notice. It took more than a minute for the firmware to load
> via MDIO.
> 
> This was strange as the same operation was done by UBoot in at max 5
> second and the same data was loaded.
> 
> A similar problem was observed on a mtk board that also had an
> Aquantia PHY where the load was very slow. It was notice that the cause
> was the MDIO bus running at a very low speed and the firmware
> was missing a property (present in mtk sdk) that set the right frequency
> to the MDIO bus.
> 
> It was fun to find that THE VERY SAME PROBLEM is present on IPQ in a
> different form. The MDIO apply internally a division to the feed clock
> resulting in the bus running at 390KHz instead of 6.25Mhz.
> 
> Searching around the web for some documentation and some include and
> analyzing the uboot codeflow resulted in the divider being set wrongly
> at /256 instead of /16 as the value was actually never set.
> Applying the value restore the original load time for the Aquantia PHY.
> 
> This series mainly handle this by adding support for the "clock-frequency"
> property.
> 
> Christian Marangi (3):
>    dt-bindings: net: ipq4019-mdio: document now supported clock-frequency
>    net: mdio: ipq4019: add support for clock-frequency property
>    arm64: dts: qcom: ipq8074: add clock-frequency to MDIO node
> 
>   .../bindings/net/qcom,ipq4019-mdio.yaml       | 10 +++
>   arch/arm64/boot/dts/qcom/ipq8074.dtsi         |  2 +
>   drivers/net/mdio/mdio-ipq4019.c               | 68 +++++++++++++++++--
>   3 files changed, 75 insertions(+), 5 deletions(-)
> 

Hi Christian,
Just a gentle reminder.

The MDIO frequency config is already added by the following patch series.
https://lore.kernel.org/netdev/28c8b31c-8dcb-4a19-9084-22c77a74b9a1@linaro.org/T/#m840cb8d269dca133c3ad3da3d112c63382ec2058

This MDIO patch series will be updated to just keep the MDIO frequency
patch and DT document for this MDIO frequency property added.

For CMN PLL config will be moved to the CMN PLL clock driver and the 
UNIPHY clock config will be moved the uniphy driver as suggested by
Sergey's suggestions.

Thanks.

Re: [net-next PATCH 0/3] net: mdio-ipq4019: fix wrong default MDC rate

[Christian Marangi]

On Thu, Jan 25, 2024 at 01:57:20PM +0800, Jie Luo wrote:
> 
> 
> On 1/25/2024 5:36 AM, Christian Marangi wrote:
> > This was a long journey to arrive and discover this problem.
> > 
> > To not waste too much char, there is a race problem with PHY and driver
> > probe. This was observed with Aquantia PHY firmware loading.
> > 
> > With some hacks the race problem was workarounded but an interesting
> > thing was notice. It took more than a minute for the firmware to load
> > via MDIO.
> > 
> > This was strange as the same operation was done by UBoot in at max 5
> > second and the same data was loaded.
> > 
> > A similar problem was observed on a mtk board that also had an
> > Aquantia PHY where the load was very slow. It was notice that the cause
> > was the MDIO bus running at a very low speed and the firmware
> > was missing a property (present in mtk sdk) that set the right frequency
> > to the MDIO bus.
> > 
> > It was fun to find that THE VERY SAME PROBLEM is present on IPQ in a
> > different form. The MDIO apply internally a division to the feed clock
> > resulting in the bus running at 390KHz instead of 6.25Mhz.
> > 
> > Searching around the web for some documentation and some include and
> > analyzing the uboot codeflow resulted in the divider being set wrongly
> > at /256 instead of /16 as the value was actually never set.
> > Applying the value restore the original load time for the Aquantia PHY.
> > 
> > This series mainly handle this by adding support for the "clock-frequency"
> > property.
> > 
> > Christian Marangi (3):
> >    dt-bindings: net: ipq4019-mdio: document now supported clock-frequency
> >    net: mdio: ipq4019: add support for clock-frequency property
> >    arm64: dts: qcom: ipq8074: add clock-frequency to MDIO node
> > 
> >   .../bindings/net/qcom,ipq4019-mdio.yaml       | 10 +++
> >   arch/arm64/boot/dts/qcom/ipq8074.dtsi         |  2 +
> >   drivers/net/mdio/mdio-ipq4019.c               | 68 +++++++++++++++++--
> >   3 files changed, 75 insertions(+), 5 deletions(-)
> > 
> 
> Hi Christian,
> Just a gentle reminder.
>

Hi Jie,
hope you can understand my reason.

> The MDIO frequency config is already added by the following patch series.
> https://lore.kernel.org/netdev/28c8b31c-8dcb-4a19-9084-22c77a74b9a1@linaro.org/T/#m840cb8d269dca133c3ad3da3d112c63382ec2058
> 

Wasn't aware of this, as I said in the cover letter this all comes by a
problem we notice in the Aquantia firmware load that was slow as hell
and we just notice the misconfiguration of the divisor.

The feature in this series is really a simple one and almost ready (I
already have v2 ready for the request from Andrew to follow 802.3 spec)
and we really need it ASAP as we are trying to move our ipq807x targets to
upstream driver and finally start using the integrated firmware loading
for Aquantia PHY.

Also I can see some fundamental difference between the 2 patch, mainly
in how the value is applied and setting a sane divisor by default
instead of using 0xff. (probably Andrew would have pointed out the same
thing in some later revision to your series)

Looking at the linked series I notice there are still some thing to
polish and to clarify with DT and driver and I think it's only
beneficial if this feature is worked separately as it's not only needed
for ipq50xx but affects every user of this (ipq40xx, ipq807x, ipq60xx)
and it would be a pitty to wait the entire ipq50xx series to be handled
just to fix a long lasting misconfiguration on various SoC family.

Hope you can understand these reasons, it's all for the sake of making
this driver more mature quicker.

> This MDIO patch series will be updated to just keep the MDIO frequency
> patch and DT document for this MDIO frequency property added.
> 
> For CMN PLL config will be moved to the CMN PLL clock driver and the UNIPHY
> clock config will be moved the uniphy driver as suggested by
> Sergey's suggestions.
> 
> Thanks.
> 
> 

-- 
	Ansuel

Re: [net-next PATCH 0/3] net: mdio-ipq4019: fix wrong default MDC rate

[Andrew Lunn]

> Hi Christian,
> Just a gentle reminder.
> 
> The MDIO frequency config is already added by the following patch series.
> https://lore.kernel.org/netdev/28c8b31c-8dcb-4a19-9084-22c77a74b9a1@linaro.org/T/#m840cb8d269dca133c3ad3da3d112c63382ec2058

I admit this version was posted first. However, its embedded in a
patch series which is not making much progress, and i doubt will make
progress any time soon.

If you really want your version to be used, please split it out into a
standalone patch series adding just MDIO clock-frequency support, with
its binding, and nothing else.

    Andrew

Re: [net-next PATCH 0/3] net: mdio-ipq4019: fix wrong default MDC rate

[Jie Luo]

On 1/26/2024 1:18 AM, Andrew Lunn wrote:
>> Hi Christian,
>> Just a gentle reminder.
>>
>> The MDIO frequency config is already added by the following patch series.
>> https://lore.kernel.org/netdev/28c8b31c-8dcb-4a19-9084-22c77a74b9a1@linaro.org/T/#m840cb8d269dca133c3ad3da3d112c63382ec2058
> 
> I admit this version was posted first. However, its embedded in a
> patch series which is not making much progress, and i doubt will make
> progress any time soon.
> 
> If you really want your version to be used, please split it out into a
> standalone patch series adding just MDIO clock-frequency support, with
> its binding, and nothing else.
> 
>      Andrew

Hi Andrew,
We will rework the patch series to include only MDIO frequency related
function and frequency dt binding, and post the updated patch series
on the Monday/Tuesday of next week. We will work with Christian to 
ensure he can re-use this patch as well.

Thanks

Re: [net-next PATCH 0/3] net: mdio-ipq4019: fix wrong default MDC rate

[Dmitry Baryshkov]

On Fri, 26 Jan 2024 at 18:03, Jie Luo <quic_luoj@quicinc.com> wrote:
>
>
>
> On 1/26/2024 1:18 AM, Andrew Lunn wrote:
> >> Hi Christian,
> >> Just a gentle reminder.
> >>
> >> The MDIO frequency config is already added by the following patch series.
> >> https://lore.kernel.org/netdev/28c8b31c-8dcb-4a19-9084-22c77a74b9a1@linaro.org/T/#m840cb8d269dca133c3ad3da3d112c63382ec2058
> >
> > I admit this version was posted first. However, its embedded in a
> > patch series which is not making much progress, and i doubt will make
> > progress any time soon.
> >
> > If you really want your version to be used, please split it out into a
> > standalone patch series adding just MDIO clock-frequency support, with
> > its binding, and nothing else.
> >
> >      Andrew
>
> Hi Andrew,
> We will rework the patch series to include only MDIO frequency related
> function and frequency dt binding, and post the updated patch series
> on the Monday/Tuesday of next week. We will work with Christian to
> ensure he can re-use this patch as well.

Can you do the other way around: rebase your patches on top of Chritian's work?

-- 
With best wishes
Dmitry

Re: [net-next PATCH 0/3] net: mdio-ipq4019: fix wrong default MDC rate

[Christian Marangi]

On Fri, Jan 26, 2024 at 07:20:03PM +0200, Dmitry Baryshkov wrote:
> On Fri, 26 Jan 2024 at 18:03, Jie Luo <quic_luoj@quicinc.com> wrote:
> >
> >
> >
> > On 1/26/2024 1:18 AM, Andrew Lunn wrote:
> > >> Hi Christian,
> > >> Just a gentle reminder.
> > >>
> > >> The MDIO frequency config is already added by the following patch series.
> > >> https://lore.kernel.org/netdev/28c8b31c-8dcb-4a19-9084-22c77a74b9a1@linaro.org/T/#m840cb8d269dca133c3ad3da3d112c63382ec2058
> > >
> > > I admit this version was posted first. However, its embedded in a
> > > patch series which is not making much progress, and i doubt will make
> > > progress any time soon.
> > >
> > > If you really want your version to be used, please split it out into a
> > > standalone patch series adding just MDIO clock-frequency support, with
> > > its binding, and nothing else.
> > >
> > >      Andrew
> >
> > Hi Andrew,
> > We will rework the patch series to include only MDIO frequency related
> > function and frequency dt binding, and post the updated patch series
> > on the Monday/Tuesday of next week. We will work with Christian to
> > ensure he can re-use this patch as well.
> 
> Can you do the other way around: rebase your patches on top of Chritian's work?
>

Would be ideal, also I have to send v2 that handle the 802.3 suggested
MDC rate (ready I just need to send after this has been handled).

Also I can see some problem with Lui patch where the divisor
value is not reapplied after MDIO reset effectively reverting to the
default value.

If it's a credits problem I can totally change the from or add
Co-devloped, I just need the feature since the thing is broken from a
looong time on ipq40xx and ipq807x.

-- 
	Ansuel

Re: [net-next PATCH 0/3] net: mdio-ipq4019: fix wrong default MDC rate

[Jie Luo]

On 1/27/2024 1:33 AM, Christian Marangi wrote:
> On Fri, Jan 26, 2024 at 07:20:03PM +0200, Dmitry Baryshkov wrote:
>> On Fri, 26 Jan 2024 at 18:03, Jie Luo <quic_luoj@quicinc.com> wrote:
>>>
>>>
>>>
>>> On 1/26/2024 1:18 AM, Andrew Lunn wrote:
>>>>> Hi Christian,
>>>>> Just a gentle reminder.
>>>>>
>>>>> The MDIO frequency config is already added by the following patch series.
>>>>> https://lore.kernel.org/netdev/28c8b31c-8dcb-4a19-9084-22c77a74b9a1@linaro.org/T/#m840cb8d269dca133c3ad3da3d112c63382ec2058
>>>>
>>>> I admit this version was posted first. However, its embedded in a
>>>> patch series which is not making much progress, and i doubt will make
>>>> progress any time soon.
>>>>
>>>> If you really want your version to be used, please split it out into a
>>>> standalone patch series adding just MDIO clock-frequency support, with
>>>> its binding, and nothing else.
>>>>
>>>>       Andrew
>>>
>>> Hi Andrew,
>>> We will rework the patch series to include only MDIO frequency related
>>> function and frequency dt binding, and post the updated patch series
>>> on th/Tuesdae Mondayy of next week. We will work with Christian to
>>> ensure he can re-use this patch as well.
>>
>> Can you do the other way around: rebase your patches on top of Chritian's work?

Hi Dmitry,
Sure, we can take this approach if fine by Andrew as well.

>>
> 
> Would be ideal, also I have to send v2 that handle the 802.3 suggested
> MDC rate (ready I just need to send after this has been handled).
> 
> Also I can see some problem with Lui patch where thse divior
> value is not reapplied after MDIO reset effectively reverting to the
> default value.

Hi Christian,
In my version, the divisor is programmed in every MDIO operation and 
hence I did not add the code to revert to configured value in reset 
function. But sure. we can program it once during the probe/reset and 
avoid doing it during read/write ops.

In addition, the MDIO divisor 1, 2 and 4 are not supported by the MDIO
hardware block, maybe we can remove these macros to avoid confusion, or 
add a comment mentioning that these are not supported.

> 
> If it's a credits problem I can totally change the from or add
> Co-devloped, I just need the feature since the thing is broken from a
> looong time on ipq40xx and ipq807x.
> 

Re: [net-next PATCH 0/3] net: mdio-ipq4019: fix wrong default MDC rate

[Christian Marangi]

On Mon, Jan 29, 2024 at 09:59:03PM +0800, Jie Luo wrote:
> 
> 
> On 1/27/2024 1:33 AM, Christian Marangi wrote:
> > On Fri, Jan 26, 2024 at 07:20:03PM +0200, Dmitry Baryshkov wrote:
> > > On Fri, 26 Jan 2024 at 18:03, Jie Luo <quic_luoj@quicinc.com> wrote:
> > > > 
> > > > 
> > > > 
> > > > On 1/26/2024 1:18 AM, Andrew Lunn wrote:
> > > > > > Hi Christian,
> > > > > > Just a gentle reminder.
> > > > > > 
> > > > > > The MDIO frequency config is already added by the following patch series.
> > > > > > https://lore.kernel.org/netdev/28c8b31c-8dcb-4a19-9084-22c77a74b9a1@linaro.org/T/#m840cb8d269dca133c3ad3da3d112c63382ec2058
> > > > > 
> > > > > I admit this version was posted first. However, its embedded in a
> > > > > patch series which is not making much progress, and i doubt will make
> > > > > progress any time soon.
> > > > > 
> > > > > If you really want your version to be used, please split it out into a
> > > > > standalone patch series adding just MDIO clock-frequency support, with
> > > > > its binding, and nothing else.
> > > > > 
> > > > >       Andrew
> > > > 
> > > > Hi Andrew,
> > > > We will rework the patch series to include only MDIO frequency related
> > > > function and frequency dt binding, and post the updated patch series
> > > > on th/Tuesdae Mondayy of next week. We will work with Christian to
> > > > ensure he can re-use this patch as well.
> > > 
> > > Can you do the other way around: rebase your patches on top of Chritian's work?
> 
> Hi Dmitry,
> Sure, we can take this approach if fine by Andrew as well.
> 
> > > 
> > 
> > Would be ideal, also I have to send v2 that handle the 802.3 suggested
> > MDC rate (ready I just need to send after this has been handled).
> > 
> > Also I can see some problem with Lui patch where thse divior
> > value is not reapplied after MDIO reset effectively reverting to the
> > default value.
> 
> Hi Christian,
> In my version, the divisor is programmed in every MDIO operation and hence I
> did not add the code to revert to configured value in reset function. But
> sure. we can program it once during the probe/reset and avoid doing it
> during read/write ops.
> 
> In addition, the MDIO divisor 1, 2 and 4 are not supported by the MDIO
> hardware block, maybe we can remove these macros to avoid confusion, or add
> a comment mentioning that these are not supported.
>

Hi, thanks for confirming it! In v2 I already changed the logic to start
looping from divisor 8 and added comments in DT and driver about not
assuring correct funcionality with those divisor.

> > 
> > If it's a credits problem I can totally change the from or add
> > Co-devloped, I just need the feature since the thing is broken from a
> > looong time on ipq40xx and ipq807x.
> > 

-- 
	Ansuel

Re: [net-next PATCH 0/3] net: mdio-ipq4019: fix wrong default MDC rate

[Andrew Lunn]

On Mon, Jan 29, 2024 at 03:25:09PM +0100, Christian Marangi wrote:
> On Mon, Jan 29, 2024 at 09:59:03PM +0800, Jie Luo wrote:
> > 
> > 
> > On 1/27/2024 1:33 AM, Christian Marangi wrote:
> > > On Fri, Jan 26, 2024 at 07:20:03PM +0200, Dmitry Baryshkov wrote:
> > > > On Fri, 26 Jan 2024 at 18:03, Jie Luo <quic_luoj@quicinc.com> wrote:
> > > > > 
> > > > > 
> > > > > 
> > > > > On 1/26/2024 1:18 AM, Andrew Lunn wrote:
> > > > > > > Hi Christian,
> > > > > > > Just a gentle reminder.
> > > > > > > 
> > > > > > > The MDIO frequency config is already added by the following patch series.
> > > > > > > https://lore.kernel.org/netdev/28c8b31c-8dcb-4a19-9084-22c77a74b9a1@linaro.org/T/#m840cb8d269dca133c3ad3da3d112c63382ec2058
> > > > > > 
> > > > > > I admit this version was posted first. However, its embedded in a
> > > > > > patch series which is not making much progress, and i doubt will make
> > > > > > progress any time soon.
> > > > > > 
> > > > > > If you really want your version to be used, please split it out into a
> > > > > > standalone patch series adding just MDIO clock-frequency support, with
> > > > > > its binding, and nothing else.
> > > > > > 
> > > > > >       Andrew
> > > > > 
> > > > > Hi Andrew,
> > > > > We will rework the patch series to include only MDIO frequency related
> > > > > function and frequency dt binding, and post the updated patch series
> > > > > on th/Tuesdae Mondayy of next week. We will work with Christian to
> > > > > ensure he can re-use this patch as well.
> > > > 
> > > > Can you do the other way around: rebase your patches on top of Chritian's work?
> > 
> > Hi Dmitry,
> > Sure, we can take this approach if fine by Andrew as well.
> > 
> > > > 
> > > 
> > > Would be ideal, also I have to send v2 that handle the 802.3 suggested
> > > MDC rate (ready I just need to send after this has been handled).
> > > 
> > > Also I can see some problem with Lui patch where thse divior
> > > value is not reapplied after MDIO reset effectively reverting to the
> > > default value.
> > 
> > Hi Christian,
> > In my version, the divisor is programmed in every MDIO operation and hence I
> > did not add the code to revert to configured value in reset function. But
> > sure. we can program it once during the probe/reset and avoid doing it
> > during read/write ops.
> > 
> > In addition, the MDIO divisor 1, 2 and 4 are not supported by the MDIO
> > hardware block, maybe we can remove these macros to avoid confusion, or add
> > a comment mentioning that these are not supported.
> >
> 
> Hi, thanks for confirming it! In v2 I already changed the logic to start
> looping from divisor 8 and added comments in DT and driver about not
> assuring correct funcionality with those divisor.

Hi Christian

Lets go with your version. Please post V2 whenever you are ready.

Jie, please spend some time reviewing to patches, make any comments
you have, and if everything is O.K, you can add a Reviewed-by:

    Andrew