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Wed, 22 Feb 2023 01:09:55 -0800 (PST) Received: from [192.168.1.109] ([178.197.216.144]) by smtp.gmail.com with ESMTPSA id u4-20020adfed44000000b002c706c754fesm3425292wro.32.2023.02.22.01.09.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 22 Feb 2023 01:09:55 -0800 (PST) Message-ID: Date: Wed, 22 Feb 2023 10:09:53 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v1 3/3] riscv: dts: starfive: jh7110: Add PLL clock node Content-Language: en-US To: Xingyu Wu , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Philipp Zabel , Emil Renner Berthing Cc: Rob Herring , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Hal Feng , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org References: <20230221141147.303642-1-xingyu.wu@starfivetech.com> <20230221141147.303642-4-xingyu.wu@starfivetech.com> From: Krzysztof Kozlowski In-Reply-To: <20230221141147.303642-4-xingyu.wu@starfivetech.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 21/02/2023 15:11, Xingyu Wu wrote: > Add the PLL clock node for the Starfive JH7110 SoC and > modify the SYSCRG node to add PLL clocks. > > Signed-off-by: Xingyu Wu > --- > arch/riscv/boot/dts/starfive/jh7110.dtsi | 15 +++++++++++++-- > 1 file changed, 13 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > index b6612c53d0d2..0cb8d86ebce5 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > @@ -461,12 +461,16 @@ syscrg: clock-controller@13020000 { > <&gmac1_rgmii_rxin>, > <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, > <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, > - <&tdm_ext>, <&mclk_ext>; > + <&tdm_ext>, <&mclk_ext>, > + <&pllclk JH7110_CLK_PLL0_OUT>, > + <&pllclk JH7110_CLK_PLL1_OUT>, > + <&pllclk JH7110_CLK_PLL2_OUT>; > clock-names = "osc", "gmac1_rmii_refin", > "gmac1_rgmii_rxin", > "i2stx_bclk_ext", "i2stx_lrck_ext", > "i2srx_bclk_ext", "i2srx_lrck_ext", > - "tdm_ext", "mclk_ext"; > + "tdm_ext", "mclk_ext", > + "pll0_out", "pll1_out", "pll2_out"; > #clock-cells = <1>; > #reset-cells = <1>; > }; > @@ -476,6 +480,13 @@ sys_syscon: syscon@13030000 { > reg = <0x0 0x13030000 0x0 0x1000>; > }; > > + pllclk: pll-clock-controller { Does not look like you tested the DTS against bindings. Please run `make dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst for instructions). You should see here warnings of mixing non-MMIO nodes in MMIO-bus. Best regards, Krzysztof