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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id k14-20020aa7c04e000000b00431962fe5d4sm10849901edo.77.2022.06.28.23.33.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 28 Jun 2022 23:33:20 -0700 (PDT) Message-ID: Date: Wed, 29 Jun 2022 08:33:19 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH V3 04/11] dt-bindings: PCI: tegra234: Add schema for tegra234 endpoint mode Content-Language: en-US To: Vidya Sagar , bhelgaas@google.com, lorenzo.pieralisi@arm.com, robh+dt@kernel.org, thierry.reding@gmail.com, jonathanh@nvidia.com Cc: kishon@ti.com, vkoul@kernel.org, kw@linux.com, p.zabel@pengutronix.de, mperttunen@nvidia.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, kthota@nvidia.com, mmaddireddy@nvidia.com, sagar.tv@gmail.com References: <20220629060435.25297-1-vidyas@nvidia.com> <20220629060435.25297-5-vidyas@nvidia.com> From: Krzysztof Kozlowski In-Reply-To: <20220629060435.25297-5-vidyas@nvidia.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 29/06/2022 08:04, Vidya Sagar wrote: > Add support for PCIe controllers that operate in the endpoint mode > in tegra234 chipset. > > Signed-off-by: Vidya Sagar > --- > V3: > * New patch in this series > > .../bindings/pci/nvidia,tegra194-pcie-ep.yaml | 141 +++++++++++++++++- > 1 file changed, 136 insertions(+), 5 deletions(-) > All comments from patch #3 apply. > diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml > index 4f7cb7fe378e..11778eb92c47 100644 > --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml > +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml > @@ -17,6 +17,7 @@ description: | > in they can work either in root port mode or endpoint mode but one at a time. > > On Tegra194, controllers C0, C4 and C5 support endpoint mode. > + On Tegra234, controllers C5, C6, C7 and C10 support endpoint mode. > > Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to operate in the > endpoint mode because of the way the platform is designed. > @@ -25,6 +26,7 @@ properties: > compatible: > enum: > - nvidia,tegra194-pcie-ep > + - nvidia,tegra234-pcie-ep > > reg: (...) > + - if: > + properties: > + compatible: > + contains: > + enum: > + - nvidia,tegra234-pcie > + then: > + properties: > + nvidia,bpmp: > + items: > + - items: > + - minimum: 0 > + maximum: 0xffffffff > + - enum: [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 ] > + > unevaluatedProperties: false > > required: > @@ -174,6 +245,7 @@ required: > - power-domains > - reset-gpios > - num-lanes > + - vddio-pex-ctl-supply This is unexpected and looks unrelated. Best regards, Krzysztof