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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id z8-20020a1cf408000000b003942a244ecdsm948690wma.18.2022.05.05.01.43.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 May 2022 01:43:18 -0700 (PDT) Message-ID: Date: Thu, 5 May 2022 10:43:17 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.8.1 Subject: Re: [PATCH v2 2/4] dt-bindings: cpufreq: apple,soc-cpufreq: Add binding for Apple SoC cpufreq Content-Language: en-US To: Hector Martin , "Rafael J. Wysocki" , Viresh Kumar Cc: Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Stephen Boyd , Ulf Hansson , Marc Zyngier , Mark Kettenis , linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20220504075153.185208-1-marcan@marcan.st> <20220504075153.185208-3-marcan@marcan.st> From: Krzysztof Kozlowski In-Reply-To: <20220504075153.185208-3-marcan@marcan.st> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 04/05/2022 09:51, Hector Martin wrote: > This binding represents the cpufreq/DVFS hardware present in Apple SoCs. > The hardware has an independent controller per CPU cluster, but we > represent them as a single cpufreq node since there can only be one > systemwide cpufreq device (and since in the future, interactions with > memory controller performance states will also involve cooperation > between multiple frequency domains). > > Signed-off-by: Hector Martin > --- > .../bindings/cpufreq/apple,soc-cpufreq.yaml | 121 ++++++++++++++++++ > 1 file changed, 121 insertions(+) > create mode 100644 Documentation/devicetree/bindings/cpufreq/apple,soc-cpufreq.yaml > > diff --git a/Documentation/devicetree/bindings/cpufreq/apple,soc-cpufreq.yaml b/Documentation/devicetree/bindings/cpufreq/apple,soc-cpufreq.yaml > new file mode 100644 > index 000000000000..f398c1bd5de5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/cpufreq/apple,soc-cpufreq.yaml > @@ -0,0 +1,121 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/cpufreq/apple,soc-cpufreq.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Apple SoC cpufreq device > + > +maintainers: > + - Hector Martin > + > +description: | > + Apple SoCs (e.g. M1) have a per-cpu-cluster DVFS controller that is part of > + the cluster management register block. This binding uses the standard > + operating-points-v2 table to define the CPU performance states, with the > + opp-level property specifying the hardware p-state index for that level. > + > +properties: > + compatible: > + items: > + - enum: > + - apple,t8103-soc-cpufreq > + - apple,t6000-soc-cpufreq > + - const: apple,soc-cpufreq > + > + reg: > + minItems: 1 > + maxItems: 6 Is the number of clusters fixed for t8103 and t6000? Are these compatibles strictly related to some specific M1 SoC? If yes, then you should have constraints in allOf:if:then. Best regards, Krzysztof