Re: [PATCH v1 1/3] clk: qcom: clk-alpha-pll: Add support for controlling Agera PLLs

[Taniya Das <tdas@codeaurora.org>]

Thanks for the review Stephen.

On 9/15/2020 5:43 AM, Stephen Boyd wrote:
> Quoting Taniya Das (2020-09-08 10:07:26)
>> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
>> index 26139ef..fb27fcf 100644
>> --- a/drivers/clk/qcom/clk-alpha-pll.c
>> +++ b/drivers/clk/qcom/clk-alpha-pll.c
>> @@ -1561,3 +1571,75 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
>>          .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
>>   };
>>   EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);
>> +
>> +void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
>> +                       const struct alpha_pll_config *config)
>> +{
>> +       if (config->l)
>> +               regmap_write(regmap, PLL_L_VAL(pll), config->l);
>> +
>> +       if (config->alpha)
>> +               regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
>> +
>> +       if (config->user_ctl_val)
>> +               regmap_write(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
>> +
>> +       if (config->config_ctl_val)
>> +               regmap_write(regmap, PLL_CONFIG_CTL(pll),
>> +                                               config->config_ctl_val);
>> +
>> +       if (config->config_ctl_hi_val)
>> +               regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
>> +                                               config->config_ctl_hi_val);
>> +
>> +       if (config->test_ctl_val)
>> +               regmap_write(regmap, PLL_TEST_CTL(pll),
>> +                                               config->test_ctl_val);
>> +
>> +       if (config->test_ctl_hi_val)
>> +               regmap_write(regmap,  PLL_TEST_CTL_U(pll),
>> +                                               config->test_ctl_hi_val);
>> +}
>> +EXPORT_SYMBOL_GPL(clk_agera_pll_configure);
>> +
>> +static int alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate,
> 
> Why not clk_alpha_pll prefix? We should prefix the other PLL functions
> in here with clk_alpha_ like trion and fabia
> 

Yes, I will update this in the next patch.

>> +                                                       unsigned long prate)
>> +{
>> +       struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
>> +       u32 l, alpha_width = pll_alpha_width(pll);
>> +       unsigned long rrate;
>> +       u64 a;
>> +
>> +       rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
>> +
>> +       /*
>> +        * Due to limited number of bits for fractional rate programming, the
>> +        * rounded up rate could be marginally higher than the requested rate.
>> +        */
>> +       if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) {
>> +               pr_err("Call set rate on the PLL with rounded rates!\n");
>> +               return -EINVAL;
>> +       }
> 
> See commit f78f29079327 ("clk: qcom: alpha-pll: Make error prints more
> informative") where I tried to make this better. Can you extract this
> check into a function that helps us understand the error better?
> 

Updated to follow the same.

>> +
>> +       /* change L_VAL without having to go through the power on sequence */
>> +       regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
>> +       regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
>> +
>> +       /* Ensure that the write above goes through before proceeding. */
>> +       mb();
> 
> regmap has an mb() in it. Remove this?
> 

Yes, will remove it.

>> +
>> +       if (clk_hw_is_enabled(hw))
>> +               return wait_for_pll_enable_lock(pll);
>> +
>> +       return 0;
>> +}
>> +
>> +const struct clk_ops clk_alpha_pll_agera_ops = {
>> +       .enable = clk_alpha_pll_enable,
>> +       .disable = clk_alpha_pll_disable,
>> +       .is_enabled = clk_alpha_pll_is_enabled,
>> +       .recalc_rate = alpha_pll_fabia_recalc_rate,
>> +       .round_rate = clk_alpha_pll_round_rate,
>> +       .set_rate = alpha_pll_agera_set_rate,
>> +};
>> +EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops);

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