From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dmitry Osipenko Subject: Re: [PATCH v8 01/21] pinctrl: tegra: Fix write barrier placement in pmx_writel Date: Fri, 9 Aug 2019 14:38:54 +0300 Message-ID: References: <1565308020-31952-1-git-send-email-skomatineni@nvidia.com> <1565308020-31952-2-git-send-email-skomatineni@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <1565308020-31952-2-git-send-email-skomatineni@nvidia.com> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Sowjanya Komatineni , thierry.reding@gmail.com, jonathanh@nvidia.com, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, linus.walleij@linaro.org, stefan@agner.ch, mark.rutland@arm.com Cc: pdeschrijver@nvidia.com, pgaikwad@nvidia.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, jckuo@nvidia.com, josephl@nvidia.com, talho@nvidia.com, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, mperttunen@nvidia.com, spatra@nvidia.com, robh+dt@kernel.org, devicetree@vger.kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org, linux-pm@vger.kernel.org List-Id: devicetree@vger.kernel.org 09.08.2019 2:46, Sowjanya Komatineni пишет: > pmx_writel uses writel which inserts write barrier before the > register write rather. > > This patch has fix to replace writel with writel_relaxed followed > by a write barrier to ensure write operation before the barrier > is completed for successful pinctrl change. > > Signed-off-by: Sowjanya Komatineni > --- > drivers/pinctrl/tegra/pinctrl-tegra.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c > index e3a237534281..982ee634b3b1 100644 > --- a/drivers/pinctrl/tegra/pinctrl-tegra.c > +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c > @@ -32,7 +32,9 @@ static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg) > > static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg) > { > - writel(val, pmx->regs[bank] + reg); > + writel_relaxed(val, pmx->regs[bank] + reg); > + /* make sure pinmux register write completed */ > + wmb(); > } > > static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) > But this only ensures that CPU have sent the write to the APB BUS and not that the write actually taken into effect? I'm a bit paranoid when it comes to a cross-domain synchronization things. Any ways it looks better than it was before. Reviewed-by: Dmitry Osipenko