From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33FA338F8E for ; Mon, 18 Sep 2023 10:41:27 +0000 (UTC) Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88D0D100; Mon, 18 Sep 2023 03:41:23 -0700 (PDT) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 38IA6DNe031947; Mon, 18 Sep 2023 10:40:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=qcppdkim1; bh=B/syoctX9E+0f5BY3ihWhiNWKIhOTa+1cKiNrQMlXAw=; b=d/rrt51jHmxYQ6ZK1Ek6joQRsqp7TSdiBpTB2Qyx5qnvfMdPWRw0XmaFcQ/hOHA5/F0u VEFqqYGDGu8pRqJ22xHdXNIx7+X9GuHvDrrFZ8DbGIosDDq2NLURbmTeFY7laEG0L55j iSp20H37mZTYfMSicY+3wD88QU/MXfNyXCrudPrKU8xGBcilmZk3O1JZFAuK8UdC4aJi mIxQT0vAsMcbN4xAKWrImIUW/kikXg2MTglsGNcWbGy3eUELXZMakAaGKWRlBlgUsY5J Tu9CS9ordpPcHibWsn+FAqj44xEM2ZNltWsKCw1i8QBe9rflmLO2HTNKDOCXNTMNwLAg kw== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3t53ps2u91-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 18 Sep 2023 10:40:55 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 38IAesN0002326 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 18 Sep 2023 10:40:54 GMT Received: from [10.239.132.204] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Mon, 18 Sep 2023 03:40:46 -0700 Message-ID: Date: Mon, 18 Sep 2023 18:40:43 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 7/8] arm64: dts: qcom: add uart console support for SM4450 To: Konrad Dybcio , , , , , , , , , CC: , , , , , , , , , , , , , , , , , References: <20230915021509.25773-1-quic_tengfan@quicinc.com> <20230915021509.25773-9-quic_tengfan@quicinc.com> From: Tengfei Fan In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: lgC4iExz9KqOaoeDh8g-0Y9YessK-dwZ X-Proofpoint-GUID: lgC4iExz9KqOaoeDh8g-0Y9YessK-dwZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-18_02,2023-09-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 malwarescore=0 mlxlogscore=495 spamscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309180093 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net 在 9/15/2023 8:12 PM, Konrad Dybcio 写道: > On 15.09.2023 04:15, Tengfei Fan wrote: >> Add base description of UART, TLMM, interconnect, TCSRCC and SMMU nodes >> which helps SM4450 boot to shell with console on boards with this SoC. >> >> Signed-off-by: Tengfei Fan >> --- > You're adding multiple independent hardware blocks at once. > This is impossible to bisect if anyone ever encounters an > issue with one of them. > > Konrad Hi Konrad, Because all these DT nodes are for support enable uart console. Put all these DT nodes in one patch to form a complete funcitonal body, so add multiple independent hardware blocks in one patch. -- Thx and BRs, Tengfei Fan