[PATCH 0/2] dt-bindings: ufs: qcom: Split SC7280 and similar into separate file

[PATCH 0/2] dt-bindings: ufs: qcom: Split SC7280 and similar into separate file

[Krzysztof Kozlowski]

The binding for Qualcomm SoC UFS controllers grew and it will grow
further.  It already includes several conditionals, partially for
difference in handling encryption block (ICE, either as phandle or as IO
address space) but it will further grow for MCQ.

See also: lore.kernel.org/r/20250730082229.23475-1-quic_rdwivedi@quicinc.com

The question is whether SM8650 and SM8750 should have their own schemas,
but based on bindings above I think all devices here have MCQ?

Best regards,
Krzysztof

---
Krzysztof Kozlowski (2):
      dt-bindings: ufs: qcom: Split common part to qcom,ufs-common.yaml
      dt-bindings: ufs: qcom: Split SC7280 and similar

 .../devicetree/bindings/ufs/qcom,sc7280-ufshc.yaml | 149 +++++++++++++++++++
 .../devicetree/bindings/ufs/qcom,ufs-common.yaml   |  67 +++++++++
 .../devicetree/bindings/ufs/qcom,ufs.yaml          | 160 +++++----------------
 3 files changed, 251 insertions(+), 125 deletions(-)
---
base-commit: d7af19298454ed155f5cf67201a70f5cf836c842
change-id: 20250730-dt-bindings-ufs-qcom-980795ebd0aa

Best regards,
-- 
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

[PATCH 1/2] dt-bindings: ufs: qcom: Split common part to qcom,ufs-common.yaml

[Krzysztof Kozlowski]

The binding for Qualcomm SoC UFS controllers grew and it will grow
further.  It already includes several conditionals, partially for
difference in handling encryption block (ICE, either as phandle or as IO
address space) but it will further grow for MCQ.

Prepare for splitting this one big binding into several ones for common
group of devices by defining common part for all Qualcomm UFS schemas.

This only moves code, no functional impact expected.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 .../devicetree/bindings/ufs/qcom,ufs-common.yaml   | 67 ++++++++++++++++++++++
 .../devicetree/bindings/ufs/qcom,ufs.yaml          | 53 +----------------
 2 files changed, 68 insertions(+), 52 deletions(-)

diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs-common.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs-common.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..962dffcd28b44b3489be5615c75e7270a0c45dc4
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs-common.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ufs/qcom,ufs-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Universal Flash Storage (UFS) Controller Common Properties
+
+maintainers:
+  - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+properties:
+  clocks:
+    minItems: 7
+    maxItems: 9
+
+  clock-names:
+    minItems: 7
+    maxItems: 9
+
+  dma-coherent: true
+
+  interconnects:
+    minItems: 2
+    maxItems: 2
+
+  interconnect-names:
+    items:
+      - const: ufs-ddr
+      - const: cpu-ufs
+
+  iommus:
+    minItems: 1
+    maxItems: 2
+
+  phys:
+    maxItems: 1
+
+  phy-names:
+    items:
+      - const: ufsphy
+
+  power-domains:
+    maxItems: 1
+
+  required-opps:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  '#reset-cells':
+    const: 1
+
+  reset-names:
+    items:
+      - const: rst
+
+  reset-gpios:
+    maxItems: 1
+    description:
+      GPIO connected to the RESET pin of the UFS memory device.
+
+allOf:
+  - $ref: ufs-common.yaml
+
+additionalProperties: true
diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
index 6c6043d9809e1d6bf489153ab0aea5186d3563cc..fc0f7b8d1cd1c4a2168f29cffcc0c2ff660424df 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
@@ -47,39 +47,6 @@ properties:
       - const: qcom,ufshc
       - const: jedec,ufs-2.0
 
-  clocks:
-    minItems: 7
-    maxItems: 9
-
-  clock-names:
-    minItems: 7
-    maxItems: 9
-
-  dma-coherent: true
-
-  interconnects:
-    minItems: 2
-    maxItems: 2
-
-  interconnect-names:
-    items:
-      - const: ufs-ddr
-      - const: cpu-ufs
-
-  iommus:
-    minItems: 1
-    maxItems: 2
-
-  phys:
-    maxItems: 1
-
-  phy-names:
-    items:
-      - const: ufsphy
-
-  power-domains:
-    maxItems: 1
-
   qcom,ice:
     $ref: /schemas/types.yaml#/definitions/phandle
     description: phandle to the Inline Crypto Engine node
@@ -93,30 +60,12 @@ properties:
       - const: std
       - const: ice
 
-  required-opps:
-    maxItems: 1
-
-  resets:
-    maxItems: 1
-
-  '#reset-cells':
-    const: 1
-
-  reset-names:
-    items:
-      - const: rst
-
-  reset-gpios:
-    maxItems: 1
-    description:
-      GPIO connected to the RESET pin of the UFS memory device.
-
 required:
   - compatible
   - reg
 
 allOf:
-  - $ref: ufs-common.yaml
+  - $ref: qcom,ufs-common.yaml
 
   - if:
       properties:

-- 
2.48.1

[PATCH 2/2] dt-bindings: ufs: qcom: Split SC7280 and similar

[Krzysztof Kozlowski]

The binding for Qualcomm SoC UFS controllers grew and it will grow
further.  Split SC7280 and several other devices which:
1. Do not reference ICE as IO address space, but as phandle,
2. Have same order of clocks.

The split allows easier review and further growth with MCQ IO address
space.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 .../devicetree/bindings/ufs/qcom,sc7280-ufshc.yaml | 149 +++++++++++++++++++++
 .../devicetree/bindings/ufs/qcom,ufs.yaml          | 107 +++++----------
 2 files changed, 183 insertions(+), 73 deletions(-)

diff --git a/Documentation/devicetree/bindings/ufs/qcom,sc7280-ufshc.yaml b/Documentation/devicetree/bindings/ufs/qcom,sc7280-ufshc.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..0f2fe48860a7847819f325bb8170692a82af2ae3
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/qcom,sc7280-ufshc.yaml
@@ -0,0 +1,149 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ufs/qcom,sc7280-ufshc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SC7280 and Other SoCs UFS Controllers
+
+maintainers:
+  - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+# Select only our matches, not all jedec,ufs-2.0
+select:
+  properties:
+    compatible:
+      contains:
+        enum:
+          - qcom,msm8998-ufshc
+          - qcom,qcs8300-ufshc
+          - qcom,sa8775p-ufshc
+          - qcom,sc7280-ufshc
+          - qcom,sc8180x-ufshc
+          - qcom,sc8280xp-ufshc
+          - qcom,sm8250-ufshc
+          - qcom,sm8350-ufshc
+          - qcom,sm8450-ufshc
+          - qcom,sm8550-ufshc
+          - qcom,sm8650-ufshc
+          - qcom,sm8750-ufshc
+  required:
+    - compatible
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - qcom,msm8998-ufshc
+          - qcom,qcs8300-ufshc
+          - qcom,sa8775p-ufshc
+          - qcom,sc7280-ufshc
+          - qcom,sc8180x-ufshc
+          - qcom,sc8280xp-ufshc
+          - qcom,sm8250-ufshc
+          - qcom,sm8350-ufshc
+          - qcom,sm8450-ufshc
+          - qcom,sm8550-ufshc
+          - qcom,sm8650-ufshc
+          - qcom,sm8750-ufshc
+      - const: qcom,ufshc
+      - const: jedec,ufs-2.0
+
+  reg:
+    maxItems: 1
+
+  reg-names:
+    items:
+      - const: std
+
+  clocks:
+    minItems: 8
+    maxItems: 8
+
+  clock-names:
+    items:
+      - const: core_clk
+      - const: bus_aggr_clk
+      - const: iface_clk
+      - const: core_clk_unipro
+      - const: ref_clk
+      - const: tx_lane0_sync_clk
+      - const: rx_lane0_sync_clk
+      - const: rx_lane1_sync_clk
+
+  qcom,ice:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: phandle to the Inline Crypto Engine node
+
+required:
+  - compatible
+  - reg
+
+allOf:
+  - $ref: qcom,ufs-common.yaml
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interconnect/qcom,sm8450.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        ufs@1d84000 {
+            compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
+                         "jedec,ufs-2.0";
+            reg = <0x0 0x01d84000 0x0 0x3000>;
+            interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+            phys = <&ufs_mem_phy_lanes>;
+            phy-names = "ufsphy";
+            lanes-per-direction = <2>;
+            #reset-cells = <1>;
+            resets = <&gcc GCC_UFS_PHY_BCR>;
+            reset-names = "rst";
+            reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+
+            vcc-supply = <&vreg_l7b_2p5>;
+            vcc-max-microamp = <1100000>;
+            vccq-supply = <&vreg_l9b_1p2>;
+            vccq-max-microamp = <1200000>;
+
+            power-domains = <&gcc UFS_PHY_GDSC>;
+            iommus = <&apps_smmu 0xe0 0x0>;
+            interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
+                            <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
+            interconnect-names = "ufs-ddr", "cpu-ufs";
+
+            clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+                     <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+                     <&gcc GCC_UFS_PHY_AHB_CLK>,
+                     <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+                     <&rpmhcc RPMH_CXO_CLK>,
+                     <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+                     <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+                     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+            clock-names = "core_clk",
+                          "bus_aggr_clk",
+                          "iface_clk",
+                          "core_clk_unipro",
+                          "ref_clk",
+                          "tx_lane0_sync_clk",
+                          "rx_lane0_sync_clk",
+                          "rx_lane1_sync_clk";
+            freq-table-hz = <75000000 300000000>,
+                            <0 0>,
+                            <0 0>,
+                            <75000000 300000000>,
+                            <75000000 300000000>,
+                            <0 0>,
+                            <0 0>,
+                            <0 0>;
+            qcom,ice = <&ice>;
+        };
+    };
diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
index fc0f7b8d1cd1c4a2168f29cffcc0c2ff660424df..b34da3df841a11eb50022fa7d091ebfbb33b1d17 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
@@ -15,7 +15,16 @@ select:
   properties:
     compatible:
       contains:
-        const: qcom,ufshc
+        enum:
+          - qcom,msm8994-ufshc
+          - qcom,msm8996-ufshc
+          - qcom,qcs615-ufshc
+          - qcom,sc7180-ufshc
+          - qcom,sdm845-ufshc
+          - qcom,sm6115-ufshc
+          - qcom,sm6125-ufshc
+          - qcom,sm6350-ufshc
+          - qcom,sm8150-ufshc
   required:
     - compatible
 
@@ -25,25 +34,13 @@ properties:
       - enum:
           - qcom,msm8994-ufshc
           - qcom,msm8996-ufshc
-          - qcom,msm8998-ufshc
           - qcom,qcs615-ufshc
-          - qcom,qcs8300-ufshc
-          - qcom,sa8775p-ufshc
           - qcom,sc7180-ufshc
-          - qcom,sc7280-ufshc
-          - qcom,sc8180x-ufshc
-          - qcom,sc8280xp-ufshc
           - qcom,sdm845-ufshc
           - qcom,sm6115-ufshc
           - qcom,sm6125-ufshc
           - qcom,sm6350-ufshc
           - qcom,sm8150-ufshc
-          - qcom,sm8250-ufshc
-          - qcom,sm8350-ufshc
-          - qcom,sm8450-ufshc
-          - qcom,sm8550-ufshc
-          - qcom,sm8650-ufshc
-          - qcom,sm8750-ufshc
       - const: qcom,ufshc
       - const: jedec,ufs-2.0
 
@@ -92,44 +89,6 @@ allOf:
         reg-names:
           maxItems: 1
 
-  - if:
-      properties:
-        compatible:
-          contains:
-            enum:
-              - qcom,msm8998-ufshc
-              - qcom,qcs8300-ufshc
-              - qcom,sa8775p-ufshc
-              - qcom,sc7280-ufshc
-              - qcom,sc8180x-ufshc
-              - qcom,sc8280xp-ufshc
-              - qcom,sm8250-ufshc
-              - qcom,sm8350-ufshc
-              - qcom,sm8450-ufshc
-              - qcom,sm8550-ufshc
-              - qcom,sm8650-ufshc
-              - qcom,sm8750-ufshc
-    then:
-      properties:
-        clocks:
-          minItems: 8
-          maxItems: 8
-        clock-names:
-          items:
-            - const: core_clk
-            - const: bus_aggr_clk
-            - const: iface_clk
-            - const: core_clk_unipro
-            - const: ref_clk
-            - const: tx_lane0_sync_clk
-            - const: rx_lane0_sync_clk
-            - const: rx_lane1_sync_clk
-        reg:
-          minItems: 1
-          maxItems: 1
-        reg-names:
-          maxItems: 1
-
   - if:
       properties:
         compatible:
@@ -246,10 +205,10 @@ unevaluatedProperties: false
 
 examples:
   - |
-    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
+    #include <dt-bindings/clock/qcom,gcc-sm8150.h>
     #include <dt-bindings/clock/qcom,rpmh.h>
     #include <dt-bindings/gpio/gpio.h>
-    #include <dt-bindings/interconnect/qcom,sm8450.h>
+    #include <dt-bindings/interconnect/qcom,sm8150.h>
     #include <dt-bindings/interrupt-controller/arm-gic.h>
 
     soc {
@@ -257,9 +216,12 @@ examples:
         #size-cells = <2>;
 
         ufs@1d84000 {
-            compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
+            compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
                          "jedec,ufs-2.0";
-            reg = <0 0x01d84000 0 0x3000>;
+            reg = <0x0 0x01d84000 0x0 0x2500>,
+                  <0x0 0x01d90000 0x0 0x8000>;
+            reg-names = "std", "ice";
+
             interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
             phys = <&ufs_mem_phy_lanes>;
             phy-names = "ufsphy";
@@ -275,19 +237,8 @@ examples:
             vccq-max-microamp = <1200000>;
 
             power-domains = <&gcc UFS_PHY_GDSC>;
-            iommus = <&apps_smmu 0xe0 0x0>;
-            interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
-                            <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
-            interconnect-names = "ufs-ddr", "cpu-ufs";
+            iommus = <&apps_smmu 0x300 0>;
 
-            clock-names = "core_clk",
-                          "bus_aggr_clk",
-                          "iface_clk",
-                          "core_clk_unipro",
-                          "ref_clk",
-                          "tx_lane0_sync_clk",
-                          "rx_lane0_sync_clk",
-                          "rx_lane1_sync_clk";
             clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
                      <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
                      <&gcc GCC_UFS_PHY_AHB_CLK>,
@@ -295,15 +246,25 @@ examples:
                      <&rpmhcc RPMH_CXO_CLK>,
                      <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
                      <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
-                     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
-            freq-table-hz = <75000000 300000000>,
+                     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
+                     <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+            clock-names = "core_clk",
+                          "bus_aggr_clk",
+                          "iface_clk",
+                          "core_clk_unipro",
+                          "ref_clk",
+                          "tx_lane0_sync_clk",
+                          "rx_lane0_sync_clk",
+                          "rx_lane1_sync_clk",
+                          "ice_core_clk";
+            freq-table-hz = <37500000 300000000>,
                             <0 0>,
                             <0 0>,
-                            <75000000 300000000>,
-                            <75000000 300000000>,
+                            <37500000 300000000>,
                             <0 0>,
                             <0 0>,
-                            <0 0>;
-            qcom,ice = <&ice>;
+                            <0 0>,
+                            <0 0>,
+                            <0 300000000>;
         };
     };

-- 
2.48.1

Re: [PATCH 0/2] dt-bindings: ufs: qcom: Split SC7280 and similar into separate file

[Nitin Rawat]

On 7/30/2025 6:05 PM, Krzysztof Kozlowski wrote:
> The binding for Qualcomm SoC UFS controllers grew and it will grow
> further.  It already includes several conditionals, partially for
> difference in handling encryption block (ICE, either as phandle or as IO
> address space) but it will further grow for MCQ.
> 
> See also: lore.kernel.org/r/20250730082229.23475-1-quic_rdwivedi@quicinc.com
> 
> The question is whether SM8650 and SM8750 should have their own schemas,
> but based on bindings above I think all devices here have MCQ?
> 
> Best regards,
> Krzysztof
> 


Hi Krzysztof,

If I understand correctly, you're splitting the YAML files based on MCQ 
(Multi-Circular Queue) support:

-qcom,sc7280-ufshc.yaml includes targets that support MCQ
-qcom,ufs-common.yaml includes common properties
-qcom,ufs.yaml includes targets that do not support MCQ


In future, if a new property applies to both some MCQ and some
non-MCQ targets, we would need to update both YAML files. In the current 
implementation, we handle such cases using if-else conditions to include 
the new property.

For reference, only SM8650 and SM8750 currently support MCQ, though more 
targets may be added later.

Regarding the patch 
lore.kernel.org/r/20250730082229.23475-1-quic_rdwivedi@quicinc.com, 
instead of using two separate YAML files, we could use if-else 
conditions to differentiate the reg and reg-name properties between MCQ 
targets (SM8650 and SM8750) and non-MCQ targets (all others).

Regards,
Nitin



> ---
> Krzysztof Kozlowski (2):
>        dt-bindings: ufs: qcom: Split common part to qcom,ufs-common.yaml
>        dt-bindings: ufs: qcom: Split SC7280 and similar
> 
>   .../devicetree/bindings/ufs/qcom,sc7280-ufshc.yaml | 149 +++++++++++++++++++
>   .../devicetree/bindings/ufs/qcom,ufs-common.yaml   |  67 +++++++++
>   .../devicetree/bindings/ufs/qcom,ufs.yaml          | 160 +++++----------------
>   3 files changed, 251 insertions(+), 125 deletions(-)
> ---
> base-commit: d7af19298454ed155f5cf67201a70f5cf836c842
> change-id: 20250730-dt-bindings-ufs-qcom-980795ebd0aa
> 
> Best regards,

Re: [PATCH 0/2] dt-bindings: ufs: qcom: Split SC7280 and similar into separate file

[Krzysztof Kozlowski]

On 30/07/2025 15:53, Nitin Rawat wrote:
> 
> 
> On 7/30/2025 6:05 PM, Krzysztof Kozlowski wrote:
>> The binding for Qualcomm SoC UFS controllers grew and it will grow
>> further.  It already includes several conditionals, partially for
>> difference in handling encryption block (ICE, either as phandle or as IO
>> address space) but it will further grow for MCQ.
>>
>> See also: lore.kernel.org/r/20250730082229.23475-1-quic_rdwivedi@quicinc.com
>>
>> The question is whether SM8650 and SM8750 should have their own schemas,
>> but based on bindings above I think all devices here have MCQ?
>>
>> Best regards,
>> Krzysztof
>>
> 
> 
> Hi Krzysztof,
> 
> If I understand correctly, you're splitting the YAML files based on MCQ 
> (Multi-Circular Queue) support:

Not entirely, I don't know which devices support MCQ. I split based on
common parts in the binding.

> 
> -qcom,sc7280-ufshc.yaml includes targets that support MCQ
> -qcom,ufs-common.yaml includes common properties
> -qcom,ufs.yaml includes targets that do not support MCQ
> 
> 
> In future, if a new property applies to both some MCQ and some
> non-MCQ targets, we would need to update both YAML files. In the current 

No

> implementation, we handle such cases using if-else conditions to include 
> the new property.

Hm?

> 
> For reference, only SM8650 and SM8750 currently support MCQ, though more 
> targets may be added later.

Are you sure? Are you claiming that SM8550 hardware does not support MCQ?

> 
> Regarding the patch 
> lore.kernel.org/r/20250730082229.23475-1-quic_rdwivedi@quicinc.com, 
> instead of using two separate YAML files, we could use if-else 
> conditions to differentiate the reg and reg-name properties between MCQ 
> targets (SM8650 and SM8750) and non-MCQ targets (all others).

It's a mess already and you want to make it messy. I already responded
on that.

Best regards,
Krzysztof

Re: [PATCH 0/2] dt-bindings: ufs: qcom: Split SC7280 and similar into separate file

[Krzysztof Kozlowski]

On Wed, Jul 30, 2025 at 04:25:06PM +0200, Krzysztof Kozlowski wrote:
> On 30/07/2025 15:53, Nitin Rawat wrote:
> > 
> > 
> > On 7/30/2025 6:05 PM, Krzysztof Kozlowski wrote:
> >> The binding for Qualcomm SoC UFS controllers grew and it will grow
> >> further.  It already includes several conditionals, partially for
> >> difference in handling encryption block (ICE, either as phandle or as IO
> >> address space) but it will further grow for MCQ.
> >>
> >> See also: lore.kernel.org/r/20250730082229.23475-1-quic_rdwivedi@quicinc.com
> >>
> >> The question is whether SM8650 and SM8750 should have their own schemas,
> >> but based on bindings above I think all devices here have MCQ?
> >>
> >> Best regards,
> >> Krzysztof
> >>
> > 
> > 
> > Hi Krzysztof,
> > 
> > If I understand correctly, you're splitting the YAML files based on MCQ 
> > (Multi-Circular Queue) support:
> 
> Not entirely, I don't know which devices support MCQ. I split based on
> common parts in the binding.

I found the docs, so I'll send v2 with MCQ also separated.

Best regards,
Krzysztof

Re: [PATCH 0/2] dt-bindings: ufs: qcom: Split SC7280 and similar into separate file

[Nitin Rawat]

On 7/30/2025 7:55 PM, Krzysztof Kozlowski wrote:
> On 30/07/2025 15:53, Nitin Rawat wrote:
>>
>>
>> On 7/30/2025 6:05 PM, Krzysztof Kozlowski wrote:
>>> The binding for Qualcomm SoC UFS controllers grew and it will grow
>>> further.  It already includes several conditionals, partially for
>>> difference in handling encryption block (ICE, either as phandle or as IO
>>> address space) but it will further grow for MCQ.
>>>
>>> See also: lore.kernel.org/r/20250730082229.23475-1-quic_rdwivedi@quicinc.com
>>>
>>> The question is whether SM8650 and SM8750 should have their own schemas,
>>> but based on bindings above I think all devices here have MCQ?
>>>
>>> Best regards,
>>> Krzysztof
>>>
>>
>>
>> Hi Krzysztof,
>>
>> If I understand correctly, you're splitting the YAML files based on MCQ
>> (Multi-Circular Queue) support:
> 
> Not entirely, I don't know which devices support MCQ. I split based on
> common parts in the binding.
> 
>>
>> -qcom,sc7280-ufshc.yaml includes targets that support MCQ
>> -qcom,ufs-common.yaml includes common properties
>> -qcom,ufs.yaml includes targets that do not support MCQ
>>
>>
>> In future, if a new property applies to both some MCQ and some
>> non-MCQ targets, we would need to update both YAML files. In the current
> 
> No
> 
>> implementation, we handle such cases using if-else conditions to include
>> the new property.
> 
> Hm?
> 
>>
>> For reference, only SM8650 and SM8750 currently support MCQ, though more
>> targets may be added later.
> 
> Are you sure? Are you claiming that SM8550 hardware does not support MCQ?

Offcourse I can say that because I am working on Qualcomm UFS Driver.

> 
>>
>> Regarding the patch
>> lore.kernel.org/r/20250730082229.23475-1-quic_rdwivedi@quicinc.com,
>> instead of using two separate YAML files, we could use if-else
>> conditions to differentiate the reg and reg-name properties between MCQ
>> targets (SM8650 and SM8750) and non-MCQ targets (all others).
> 
> It's a mess already and you want to make it messy. I already responded
> on that.
> 
> Best regards,
> Krzysztof

Re: [PATCH 0/2] dt-bindings: ufs: qcom: Split SC7280 and similar into separate file

[Krzysztof Kozlowski]

On 31/07/2025 08:59, Nitin Rawat wrote:
>> Hm?
>>
>>>
>>> For reference, only SM8650 and SM8750 currently support MCQ, though more
>>> targets may be added later.
>>
>> Are you sure? Are you claiming that SM8550 hardware does not support MCQ?
> 
> Offcourse I can say that because I am working on Qualcomm UFS Driver.

Qualcomm sent many patches which were not related to hardware at all,
just based on drivers, so my question is completely valid based on
previous experience with Qualcomm.

Best regards,
Krzysztof

Re: [PATCH 0/2] dt-bindings: ufs: qcom: Split SC7280 and similar into separate file

[Ram Kumar Dwivedi]

On 31-Jul-25 12:25 PM, Krzysztof Kozlowski wrote:
> On Wed, Jul 30, 2025 at 04:25:06PM +0200, Krzysztof Kozlowski wrote:
>> On 30/07/2025 15:53, Nitin Rawat wrote:
>>>
>>>
>>> On 7/30/2025 6:05 PM, Krzysztof Kozlowski wrote:
>>>> The binding for Qualcomm SoC UFS controllers grew and it will grow
>>>> further.  It already includes several conditionals, partially for
>>>> difference in handling encryption block (ICE, either as phandle or as IO
>>>> address space) but it will further grow for MCQ.
>>>>
>>>> See also: lore.kernel.org/r/20250730082229.23475-1-quic_rdwivedi@quicinc.com
>>>>
>>>> The question is whether SM8650 and SM8750 should have their own schemas,
>>>> but based on bindings above I think all devices here have MCQ?
>>>>
>>>> Best regards,
>>>> Krzysztof
>>>>
>>>
>>>
>>> Hi Krzysztof,
>>>
>>> If I understand correctly, you're splitting the YAML files based on MCQ 
>>> (Multi-Circular Queue) support:
>>
>> Not entirely, I don't know which devices support MCQ. I split based on
>> common parts in the binding.
> 
> I found the docs, so I'll send v2 with MCQ also separated.
> 
Hi Krzysztof,

Regarding my patch: lore.kernel.org/r/20250730082229.23475-1-quic_rdwivedi@quicinc.com
I will post the next patchset on the top of your latest(v2) binding patch. 
Please let me know if you have any concern.

Thanks,
Ram.


> Best regards,
> Krzysztof
> 

Re: [PATCH 0/2] dt-bindings: ufs: qcom: Split SC7280 and similar into separate file

[Manivannan Sadhasivam]

On Thu, Jul 31, 2025 at 09:04:48AM GMT, Krzysztof Kozlowski wrote:
> On 31/07/2025 08:59, Nitin Rawat wrote:
> >> Hm?
> >>
> >>>
> >>> For reference, only SM8650 and SM8750 currently support MCQ, though more
> >>> targets may be added later.
> >>
> >> Are you sure? Are you claiming that SM8550 hardware does not support MCQ?
> > 
> > Offcourse I can say that because I am working on Qualcomm UFS Driver.
> 
> Qualcomm sent many patches which were not related to hardware at all,
> just based on drivers, so my question is completely valid based on
> previous experience with Qualcomm.
> 

SM8550 indeed doesn't support MCQ. Even though it is based on UFSHCD 4.x, it
doesn't support MCQ due to hardware design. MCQ support only starts from SM8650.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH 0/2] dt-bindings: ufs: qcom: Split SC7280 and similar into separate file

[Krzysztof Kozlowski]

On 31/07/2025 16:09, Manivannan Sadhasivam wrote:
> On Thu, Jul 31, 2025 at 09:04:48AM GMT, Krzysztof Kozlowski wrote:
>> On 31/07/2025 08:59, Nitin Rawat wrote:
>>>> Hm?
>>>>
>>>>>
>>>>> For reference, only SM8650 and SM8750 currently support MCQ, though more
>>>>> targets may be added later.
>>>>
>>>> Are you sure? Are you claiming that SM8550 hardware does not support MCQ?
>>>
>>> Offcourse I can say that because I am working on Qualcomm UFS Driver.
>>
>> Qualcomm sent many patches which were not related to hardware at all,
>> just based on drivers, so my question is completely valid based on
>> previous experience with Qualcomm.
>>
> 
> SM8550 indeed doesn't support MCQ. Even though it is based on UFSHCD 4.x, it
> doesn't support MCQ due to hardware design. MCQ support only starts from SM8650.

Yeah, I checked later in datasheets and programming guide. That's why I
sent v2 and marked it in Patchwork as changes-requested.

Best regards,
Krzysztof