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[109.252.139.36]) by smtp.googlemail.com with ESMTPSA id m26sm587716lfo.107.2022.01.23.13.07.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 23 Jan 2022 13:07:17 -0800 (PST) Message-ID: Date: Mon, 24 Jan 2022 00:07:17 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v2 1/4] dt-bindings: Add headers for Tegra234 I2C Content-Language: en-US To: Akhil R , "devicetree@vger.kernel.org" , Jonathan Hunter , Laxman Dewangan , "linux-i2c@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-tegra@vger.kernel.org" , Mikko Perttunen , "robh+dt@kernel.org" , "thierry.reding@gmail.com" References: <1642850607-20664-1-git-send-email-akhilrajeev@nvidia.com> <1642850607-20664-2-git-send-email-akhilrajeev@nvidia.com> <103960bf-ed5c-4a0c-9142-65ffc2e4bca0@gmail.com> From: Dmitry Osipenko In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org 23.01.2022 19:56, Akhil R пишет: >>> Add dt-bindings header files for I2C controllers for Tegra234 >>> >>> Signed-off-by: Akhil R >>> --- >>> include/dt-bindings/clock/tegra234-clock.h | 19 +++++++++++++++++++ >>> include/dt-bindings/reset/tegra234-reset.h | 8 ++++++++ >>> 2 files changed, 27 insertions(+) >>> >>> diff --git a/include/dt-bindings/clock/tegra234-clock.h >>> b/include/dt-bindings/clock/tegra234-clock.h >>> index 8d7e66e..5d05c19 100644 >>> --- a/include/dt-bindings/clock/tegra234-clock.h >>> +++ b/include/dt-bindings/clock/tegra234-clock.h >>> @@ -30,5 +30,24 @@ >>> #define TEGRA234_CLK_PLLC4 237U >>> /** @brief 32K input clock provided by PMIC */ >>> #define TEGRA234_CLK_CLK_32K 289U >>> +/** @brief output of mux controlled by >> CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */ >>> +#define TEGRA234_CLK_I2C1 48U >>> +/** @brief output of mux controlled by >> CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ >>> +#define TEGRA234_CLK_I2C2 49U >>> +/** @brief output of mux controlled by >> CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ >>> +#define TEGRA234_CLK_I2C3 50U >>> +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 >> */ >>> +#define TEGRA234_CLK_I2C4 51U >>> +/** @brief output of mux controlled by >> CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ >>> +#define TEGRA234_CLK_I2C6 52U >>> +/** @brief output of mux controlled by >> CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ >>> +#define TEGRA234_CLK_I2C7 53U >>> +/** @brief output of mux controlled by >> CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ >>> +#define TEGRA234_CLK_I2C8 54U >>> +/** @brief output of mux controlled by >> CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ >>> +#define TEGRA234_CLK_I2C9 55U >>> + >>> +/** @brief PLLP clk output */ >>> +#define TEGRA234_CLK_PLLP_OUT0 102U >>> >>> #endif >>> diff --git a/include/dt-bindings/reset/tegra234-reset.h >>> b/include/dt-bindings/reset/tegra234-reset.h >>> index 50e13bc..e07e898 100644 >>> --- a/include/dt-bindings/reset/tegra234-reset.h >>> +++ b/include/dt-bindings/reset/tegra234-reset.h >>> @@ -12,6 +12,14 @@ >>> */ >>> #define TEGRA234_RESET_SDMMC4 85U >>> #define TEGRA234_RESET_UARTA 100U >>> +#define TEGRA234_RESET_I2C1 24U >>> +#define TEGRA234_RESET_I2C2 29U >>> +#define TEGRA234_RESET_I2C3 30U >>> +#define TEGRA234_RESET_I2C4 31U >>> +#define TEGRA234_RESET_I2C6 32U >>> +#define TEGRA234_RESET_I2C7 33U >>> +#define TEGRA234_RESET_I2C8 34U >>> +#define TEGRA234_RESET_I2C9 35U >> >> Why ID order isn't maintained? > Do you mean RESET_UART4, SDMMC4 etc should be > below RESET_I2C*? Yes, please see T186/194 headers for the example and do the same for T234. Always try to use existing examples in general to maintain consistency.