From: Stanimir Varbanov <svarbanov@suse.de>
To: Florian Fainelli <florian.fainelli@broadcom.com>,
Stanimir Varbanov <svarbanov@suse.de>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org,
Broadcom internal kernel review list
<bcm-kernel-feedback-list@broadcom.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Jim Quinlan <jim2101024@gmail.com>,
Nicolas Saenz Julienne <nsaenz@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lpieralisi@kernel.org>,
kw@linux.com, Philipp Zabel <p.zabel@pengutronix.de>,
Andrea della Porta <andrea.porta@suse.com>,
Phil Elwell <phil@raspberrypi.com>,
Jonathan Bell <jonathan@raspberrypi.com>
Subject: Re: [PATCH v2 -next 05/11] PCI: brcmstb: Restore CRS in RootCtl after prstn_n
Date: Tue, 17 Sep 2024 13:24:30 +0300 [thread overview]
Message-ID: <a93c9757-963a-4b4f-a169-0c17ff39576b@suse.de> (raw)
In-Reply-To: <9de505c5-d9a2-44b7-8db1-0686c61a0fb4@broadcom.com>
Hi Florian,
On 9/10/24 19:59, Florian Fainelli wrote:
> On 9/10/24 08:18, Stanimir Varbanov wrote:
>> RootCtl bits might reset by perst_n during probe, re-enable
>> CRS SVE here in pcie_start_link.
>>
>> Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
>
> This looks like a bug fix, and we should explain what is the user
> visible effect of that, if any.
It is definitely a bugfix. Otherwise, CRS Software Visibility is
important feature from pcie1.1. Not enabling it on Root Port could lead
to infinite configuration retry cycles when enumerate endpoints which
supports CRS. For more information [1] and [2].
I spent some time debugging it and found that this is not the proper
solution. I think the issue comes from wrongly implemented .add_bus
pci_ops. Looks like .add_bus op shouldn't call brcm_pcie_start_link()
but invoke before pci_host_probe(), then the issue will fix by itself.
What I observed is that pci_enable_crs() is setting CSR Software
Visibility Enable bit but the controller is ignoring it without error
(reading the Root Control register returns zero). This means that the
controller is not ready to accept configuration write requests at that
time, that's why I tried the following diff which seems to work:
static struct pci_ops brcm_pcie_ops = {
.map_bus = brcm_pcie_map_bus,
.read = pci_generic_config_read,
.write = pci_generic_config_write,
- .add_bus = brcm_pcie_add_bus,
- .remove_bus = brcm_pcie_remove_bus,
};
static struct pci_ops brcm7425_pcie_ops = {
@@ -1983,6 +2018,9 @@ static int brcm_pcie_probe(struct platform_device
*pdev)
platform_set_drvdata(pdev, pcie);
+ //TODO: check for error
+ brcm_pcie_start_link(pcie);
+
ret = pci_host_probe(bridge);
if (!ret && !brcm_pcie_link_up(pcie))
ret = -ENODEV;
Of course this change would work on RPi5 because there are no regulators.
I will drop the patch from the series for now and work on a proper solution.
regards,
~Stan
[1]
https://patchwork.kernel.org/project/linux-pci/patch/53FFA54D.9000907@gmail.com/
[2]
https://blog.linuxplumbersconf.org/2017/ocw/system/presentations/4732/original/crs.pdf
next prev parent reply other threads:[~2024-09-17 10:24 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-10 15:18 [PATCH v2 -next 00/11] Add PCIe support for bcm2712 Stanimir Varbanov
2024-09-10 15:18 ` [PATCH v2 -next 01/11] dt-bindings: interrupt-controller: Add bcm2712 MSI-X DT bindings Stanimir Varbanov
2024-09-11 16:56 ` Rob Herring
2024-09-16 10:32 ` Stanimir Varbanov
2024-09-10 15:18 ` [PATCH v2 -next 02/11] dt-bindings: PCI: brcmstb: Update bindings for PCIe on bcm2712 Stanimir Varbanov
2024-09-11 16:57 ` Rob Herring (Arm)
2024-09-11 17:00 ` Florian Fainelli
2024-09-10 15:18 ` [PATCH v2 -next 03/11] irqchip: mip: Add Broadcom bcm2712 MSI-X interrupt controller Stanimir Varbanov
2024-09-10 15:58 ` Thomas Gleixner
2024-09-17 10:36 ` Stanimir Varbanov
2024-09-10 15:18 ` [PATCH v2 -next 04/11] PCI: brcmstb: Expand inbound size calculation helper Stanimir Varbanov
2024-09-10 16:59 ` Florian Fainelli
2024-09-17 10:38 ` Stanimir Varbanov
2024-09-10 15:18 ` [PATCH v2 -next 05/11] PCI: brcmstb: Restore CRS in RootCtl after prstn_n Stanimir Varbanov
2024-09-10 16:59 ` Florian Fainelli
2024-09-17 10:24 ` Stanimir Varbanov [this message]
2024-09-10 15:18 ` [PATCH v2 -next 06/11] PCI: brcmstb: Enable external MSI-X if available Stanimir Varbanov
2024-09-10 15:18 ` [PATCH v2 -next 07/11] PCI: brcmstb: Avoid turn off of bridge reset Stanimir Varbanov
2024-09-10 17:03 ` Florian Fainelli
2024-09-17 10:40 ` Stanimir Varbanov
2024-09-10 15:18 ` [PATCH v2 -next 08/11] PCI: brcmstb: Add bcm2712 support Stanimir Varbanov
2024-09-10 17:03 ` Florian Fainelli
2024-09-10 15:18 ` [PATCH v2 -next 09/11] PCI: brcmstb: Reuse config structure Stanimir Varbanov
2024-09-10 17:04 ` Florian Fainelli
2024-09-10 15:18 ` [PATCH v2 -next 10/11] arm64: dts: broadcom: bcm2712: Add PCIe DT nodes Stanimir Varbanov
2024-09-10 17:08 ` Florian Fainelli
2024-09-10 15:18 ` [PATCH v2 -next 11/11] arm64: dts: broadcom: bcm2712-rpi-5-b: Enable " Stanimir Varbanov
2024-09-11 13:50 ` [PATCH v2 -next 00/11] Add PCIe support for bcm2712 Rob Herring (Arm)
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