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Wed, 17 Jun 2026 05:11:38 -0700 (PDT) X-Received: by 2002:a05:6102:8499:10b0:726:e608:6651 with SMTP id ada2fe7eead31-726e617ab08mr45100137.2.1781698297638; Wed, 17 Jun 2026 05:11:37 -0700 (PDT) Received: from [192.168.120.170] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-bfdb531896dsm781731566b.27.2026.06.17.05.11.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 17 Jun 2026 05:11:36 -0700 (PDT) Message-ID: Date: Wed, 17 Jun 2026 14:11:33 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 7/7] arm64: dts: qcom: mahua: Switch pcie5_phy ref clock to RPMH_CXO_CLK To: Qiang Yu Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, krishna.chundru@oss.qualcomm.com References: <20260527-tcsr_qref_0527-v4-0-ded83866c9d9@oss.qualcomm.com> <20260527-tcsr_qref_0527-v4-7-ded83866c9d9@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE3MDExNSBTYWx0ZWRfXxid8x7B8AWCr KPdstq/wCO4WYI/45cPT/4Yb3uAfDCymqDyG4Pgs/sepwH3aLXkrjxPiUKed5mCNnnePpo1arUm jsBZtRjEifStQKilMlV03EQvtkPkmoA= X-Proofpoint-ORIG-GUID: qx4etlvJk_j1QxzjV5fUpuNAu5BEkpjm X-Authority-Analysis: v=2.4 cv=R6oz39RX c=1 sm=1 tr=0 ts=6a328efa cx=c_pps a=+D9SDfe9YZWTjADjLiQY5g==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=kmjxFz_dt4H88yzuuMsA:9 a=QEXdDO2ut3YA:10 a=vmgOmaN-Xu0dpDh8OwbV:22 X-Proofpoint-GUID: qx4etlvJk_j1QxzjV5fUpuNAu5BEkpjm X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE3MDExNSBTYWx0ZWRfX0G1mhANwyCqj iKGhGYWD/ZqgOwuB8T3NUa4IPpMOx7vTyzbjXb5zSLAdBbJmljj8bELYXY2/leqzNhirucMfrj3 lJZEsPHdOyMjMRWSPxUhqNf/lAKeNUkFm5HUnQcRGJHTvUS/ATHm5jtlQGkyYPMApQBBOkocRSz 35Rq8vbPZ0d52LU6/chCtJhmbvCOkiF1K/bytyHB/y/EHEWjfFGiHJdmPUi7S0zXZyi/sBoYgqS sYG/h10+bMnKT3tpN+Bzbt8c1mVgd8R1Vw44Ld1Lt2ToFd9890VII+Svb42FHcBPftujxljoOhn qr/MW/3NDCcTxQ8dBkUZvSfOqGWfkcnJhsoL7JbfXIE1/Tkv5UoreKNuA/lesbDV1Focqhy8/x5 cS5mKtUvFp4PUJVZOFXm+C0WnGUq35f3WVVhDEQguDM1iZxOnwnmo0bhPOSaAZTmhmRhGEZtiFN mi1oAgfxHNDmDzS43sQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-17_01,2026-06-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 clxscore=1015 impostorscore=0 phishscore=0 lowpriorityscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606170115 On 6/15/26 10:51 AM, Qiang Yu wrote: > On Tue, Jun 09, 2026 at 03:06:02PM +0200, Konrad Dybcio wrote: >> On 5/28/26 4:29 AM, Qiang Yu wrote: >>> PCIe5 PHY on Mahua gets refclk from CXO0 pad directly, so no QREF >>> clkref_en voting is required. Override the clock list to use RPMH_CXO_CLK >>> directly instead. >> >> This is the last piece of the puzzle that this series is missing. >> There's no QREF clkref_en, but there is a refgen that needs to be >> powered. For PCIe5 on Mahua this would be L2F_E0 (0p9) and L4H_E0 >> (1p2). >> >> I think the easiest (laziest?) solution would be to add dummy clocks >> in the clkref driver and only toggle the required regulators. Another >> option is to defer back to individual drivers (such as PCIe QMPPHY). >> >> I kinda like the "one central node to drive power" approach, but I'm >> not sure others agree, since it stretches truth just a tiny bit >> (although not as much as one would think since there are *some* >> controls for the transparent-to-the-OS hw pieces in these paths still >> in TCSR).. Dmitry, Krzysztof, would you object to that? >> > > PCIe5 PHY on Mahua does not use QREF at all, so there is no refgen for > QREF either. The refgen supplies you mentioned are for the PCIe5 PHY > itself, not for QREF. For other PHYs that do use QREF, there are two > refgens: one for QREF (voted here in the TCSR clkref driver) and one for > the PHY (which should be voted in the PHY driver). Okay, so in this case we have the refgen regulator hardwired into the PHY block and we just consume it from the PHY node&driver, am I following correctly? Konrad