From: Maarten Brock <m.brock@vanmierlo.com>
To: Rob Herring <robh@kernel.org>
Cc: shubhrajyoti.datta@gmail.com, linux-serial@vger.kernel.org,
devicetree@vger.kernel.org, jacmet@sunsite.dk,
Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>,
linux-serial-owner@vger.kernel.org
Subject: Re: [PATCHv3 4/4] dt-bindings: serial: Add binding for uartlite
Date: Mon, 06 Aug 2018 10:57:05 +0200 [thread overview]
Message-ID: <a9896568bfe44758a8c71e811ebb95a0@vanmierlo.com> (raw)
In-Reply-To: <20180716160251.GA11275@rob-hp-laptop>
On 2018-07-16 18:02, Rob Herring wrote:
>> +Optional properties:
>> +- port-number : Set Uart port number
>> +- clock-names : Should be "s_axi_aclk"
>> +- clocks : Input clock specifier. Refer to common clock bindings.
>
> How do you calc baud rates if this is omitted?
The uartlite is fixed to some baud rate (actually divisor) in the fpga.
And btw. so are the number of data bits, stop bits and parity.
Maarten
next prev parent reply other threads:[~2018-08-06 8:57 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-16 5:23 [PATCHv3 1/4] tty: serial: uartlite: Add structure for private data shubhrajyoti.datta
2018-07-16 5:23 ` [PATCHv3 2/4] tty: serial: uartlite: Add clock adaptation shubhrajyoti.datta
2018-07-16 5:23 ` [PATCHv3 3/4] tty: serial: uartlite: Add support for suspend and resume shubhrajyoti.datta
2018-07-16 5:23 ` [PATCHv3 4/4] dt-bindings: serial: Add binding for uartlite shubhrajyoti.datta
2018-07-16 16:02 ` Rob Herring
2018-07-18 5:42 ` Shubhrajyoti Datta
2018-08-06 8:57 ` Maarten Brock [this message]
-- strict thread matches above, loose matches on Subject: below --
2018-07-18 5:40 [PATCHv4 1/4] tty: serial: uartlite: Add structure for private data Shubhrajyoti Datta
2018-07-18 5:41 ` [PATCHv3 4/4] dt-bindings: serial: Add binding for uartlite Shubhrajyoti Datta
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