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Wed, 21 Oct 2026 09:11:08 -0700 (PDT) Received: from [192.168.1.10] ([122.164.81.208]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8a0894b484esm1095569b3a.13.2026.10.21.09.11.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Oct 2026 09:11:06 -0700 (PDT) Message-ID: Date: Wed, 21 Oct 2026 21:41:00 +0530 X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/4] clk: qcom: apss-ipq9650: Add IPQ9650 APSS clock controller driver To: Konrad Dybcio , Georgi Djakov , Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org References: <20261007-ipq9650_apss_clk-v1-0-fd4c2b3cbdea@oss.qualcomm.com> <20261007-ipq9650_apss_clk-v1-4-fd4c2b3cbdea@oss.qualcomm.com> Content-Language: en-US From: Kathiravan Thirumoorthy In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=aI5lOr9m c=1 sm=1 tr=0 ts=6ad8e41d cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=rZLzW5DhxuwyX7/NBrPT8g==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=OgLFbhcrQp8kNKIItaQA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-ORIG-GUID: eF4e03OlOCWasdaYQZVheL50NY1-AbV1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDA2NCBTYWx0ZWRfX2DI9cz6Rx64Y V7VlXYdUVUkLXpjKHYgaSs0IJz7z2/IQUoINjQSw4IBUrHdHdpwqjVR76Uz4eB6tLxZxi60t7yz nePEtCkIdL0eSuQuZnG0Fslx0pFdpyld7DgzXbo7s1NA66l7liG556TyF/gSQnYZy+ch/bbIST9 BbDC6ufj3jiHJtgvM/4DKXqfEXrFLz6OAFKCeg4ecmdHnPp0vZ/3XNvqzEyDppbB22qMjR3m0/d pbe/b8cQKIv6UbND0TFc1UGHhZTV645+G2b2102YgoXTimfSTSJWrhvR7XWDWzrgr0W4fG62JzO Ma88MTiJ2kMP5UxTX49dAXYVUmd+BvOHL6adcp3Oiau2qYfTy/v17pxlXoRI9XzcMEI0LS9aVNi 6GZMzrk9rv9+2EGYcekaPyxjbjrp9qESlT0VXuSXakAOCXAJmfM7hPf2tbYwxsTWAAiq3ZYXto2 gwV28m2rI12HHF9GHCA== X-Proofpoint-GUID: eF4e03OlOCWasdaYQZVheL50NY1-AbV1 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDA2NCBTYWx0ZWRfX9kREOyf7NZVY qfeV9WVNXRJcmYUrBcorKH0veA2P13+VakgP8Jr8qLEMo3TB7DBwqwN/Kntmohx1oCsW6jlOtV7 N8kWNfM2aEi6Ek33nddb+AM4IZZAMUA= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-21_04,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 impostorscore=0 spamscore=0 bulkscore=0 malwarescore=0 suspectscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210064 On 10/16/2026 7:22 PM, Konrad Dybcio wrote: > On 10/7/26 8:50 AM, Kathiravan Thirumoorthy wrote: >> The APSS clock controller on IPQ9650 provides the CPU and L3 clocks. >> The four Cortex-A55 cores (silver), the Cortex-A78 core (gold) and the >> L3 are each clocked by their own Zonda PLL. Each clock is selected >> through a glitch-free mux (GFM) whose parents are XO, GPLL0 and the >> corresponding PLL. The gold mux can also select the PLL's post-divider > [...] > >> +static struct clk_branch apss_silver_core_clk = { >> + .halt_reg = 0x8c, >> + .clkr = { >> + .enable_reg = 0x8c, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data) { >> + .name = "apss_silver_clk", >> + .parent_hws = (const struct clk_hw*[]) { >> + &silver_apss_pll_gfmux.hw, >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, > Do the clocks have to be enabled even if the CPUs are offline? Yes. The bootloader leaves these clocks enabled. Marking them with CLK_IS_CRITICAL prevents clk_disable_unused() from gating the CPU and L3 clocks and hanging the system during boot. > > Konrad