From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Witold Sadowski <wsadowski@marvell.com>,
linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org,
devicetree@vger.kernel.org
Cc: broonie@kernel.org, robh@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
pthombar@cadence.com
Subject: Re: [PATCH v5 2/5] spi: dt-bindings: cadence: Add Marvell overlay bindings documentation for Cadence XSPI
Date: Tue, 28 May 2024 08:56:28 +0200 [thread overview]
Message-ID: <a9902865-afcb-4d58-934d-05d62a9e995d@linaro.org> (raw)
In-Reply-To: <20240527084216.667380-4-wsadowski@marvell.com>
On 27/05/2024 10:42, Witold Sadowski wrote:
> Add new bindings for the v2 Marvell xSPI overlay: marvell,cn10-xspi-nor
> compatible string. This new compatible string distinguishes between the
> original and modified xSPI block.
>
> Also add an optional base for the xfer register set with an additional
> reg field to allocate the xSPI Marvell overlay XFER block.
>
> Signed-off-by: Witold Sadowski <wsadowski@marvell.com>
> ---
> .../devicetree/bindings/spi/cdns,xspi.yaml | 38 +++++++++++++++----
> 1 file changed, 31 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/spi/cdns,xspi.yaml b/Documentation/devicetree/bindings/spi/cdns,xspi.yaml
> index eb0f92468185..d6b8b2a2ecf5 100644
> --- a/Documentation/devicetree/bindings/spi/cdns,xspi.yaml
> +++ b/Documentation/devicetree/bindings/spi/cdns,xspi.yaml
> @@ -15,33 +15,57 @@ description: |
> single, dual, quad or octal wire transmission modes for
> read/write access to slaves such as SPI-NOR flash.
>
> -allOf:
> - - $ref: spi-controller.yaml#
> -
> properties:
> compatible:
> - const: cdns,xspi-nor
> + enum:
> + - cdns,xspi-nor
> + - marvell,cn10-xspi-nor
> +
> + interrupts:
> + maxItems: 1
Items got re-ordered. Keep previous order which matches expected style
(see also DTS coding style).
>
> reg:
> items:
> - description: address and length of the controller register set
> - description: address and length of the Slave DMA data port
> - description: address and length of the auxiliary registers
> + - description: address and length of the xfer registers
> + minItems: 3
>
> reg-names:
> items:
> - const: io
> - const: sdma
> - const: aux
> -
> - interrupts:
> - maxItems: 1
> + - const: xferbase
> + minItems: 3
>
Best regards,
Krzysztof
next prev parent reply other threads:[~2024-05-28 6:56 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-27 8:42 [PATCH v5 0/5] Marvell HW overlay support for Cadence xSPI Witold Sadowski
2024-05-27 8:42 ` Witold Sadowski
2024-05-27 8:42 ` [PATCH v5 1/5] spi: cadence: Ensure data lines set to low during dummy-cycle period Witold Sadowski
2024-05-27 8:42 ` [PATCH v5 2/5] spi: dt-bindings: cadence: Add Marvell overlay bindings documentation for Cadence XSPI Witold Sadowski
2024-05-28 6:56 ` Krzysztof Kozlowski [this message]
2024-05-29 7:40 ` [EXTERNAL] " Witold Sadowski
2024-05-27 8:42 ` [PATCH v5 3/5] spi: cadence: Add Marvell xSPI IP overlay changes Witold Sadowski
2024-05-27 8:42 ` [PATCH v5 4/5] spi: cadence: Allow to read basic xSPI configuration from ACPI Witold Sadowski
2024-05-27 8:42 ` [PATCH v5 5/5] spi: cadence: Add MRVL overlay xfer operation support Witold Sadowski
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