Re: [PATCH v3 00/10] Basic device tree support for ESWIN EIC7700 RISC-V SoC

Jisheng Zhang
2025-04-26T14:49:24Z

On Thu, Apr 10, 2025 at 08:55:09PM +0530, Pinkesh Vaghela wrote:
> Add support for ESWIN EIC7700 SoC consisting of SiFive Quad-Core
> P550 CPU cluster and the first development board that uses it, the
> SiFive HiFive Premier P550.
>
> This patch series adds initial device tree and also adds ESWIN
> architecture support.

Per past experience, new SoC needs at least pinctrl and clk tree ready.
>
> Boot-tested using intiramfs with Linux 6.15.0-rc1 on HiFive Premier
> P550 board using U-Boot 2024.01 and OpenSBI 1.4.
>
> Changes in v3:
> - Rebased the patches to kernel 6.15.0-rc1
> - Added "Reviewed-by" tag of "Rob Herring" for Patch 4
> - Updated MAINTAINERS file
> - Add GIT tree URL
> - Updated DTSI file
> - Added "dma-noncoherent" property to soc node
> - Updated GPIO node labels in DTSI file
> - Link to v2: https://lore.kernel.org/lkml/20250320105449.2094192-1-pinkesh.vaghela@einfochips.com/
>
> Changes in v2:
> - Added "Acked-by" tag of "Conor Dooley" for Patches 1, 2, 3, 7 and 8
> - Added "Reviewed-by" tag of "Matthias Brugger" for Patch 4
> - Updated MAINTAINERS file
> - Add the path for the eswin binding file
> - Updated sifive,ccache0.yaml
> - Add restrictions for "cache-size" property based on the
> compatible string
> - Link to v1: https://lore.kernel.org/lkml/20250311073432.4068512-1-pinkesh.vaghela@einfochips.com/
>
> Darshan Prajapati (3):
> dt-bindings: riscv: Add SiFive P550 CPU compatible
> dt-bindings: interrupt-controller: Add ESWIN EIC7700 PLIC
> dt-bindings: timer: Add ESWIN EIC7700 CLINT
>
> Min Lin (2):
> riscv: dts: add initial support for EIC7700 SoC
> riscv: dts: eswin: add HiFive Premier P550 board device tree
>
> Pinkesh Vaghela (2):
> riscv: Add Kconfig option for ESWIN platforms
> cache: sifive_ccache: Add ESWIN EIC7700 support
>
> Pritesh Patel (3):
> dt-bindings: vendor-prefixes: add eswin
> dt-bindings: riscv: Add SiFive HiFive Premier P550 board
> dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC
> compatibility
>
> .../bindings/cache/sifive,ccache0.yaml | 44 ++-
> .../sifive,plic-1.0.0.yaml | 1 +
> .../devicetree/bindings/riscv/cpus.yaml | 1 +
> .../devicetree/bindings/riscv/eswin.yaml | 29 ++
> .../bindings/timer/sifive,clint.yaml | 1 +
> .../devicetree/bindings/vendor-prefixes.yaml | 2 +
> MAINTAINERS | 9 +
> arch/riscv/Kconfig.socs | 6 +
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/eswin/Makefile | 2 +
> .../dts/eswin/eic7700-hifive-premier-p550.dts | 29 ++
> arch/riscv/boot/dts/eswin/eic7700.dtsi | 345 ++++++++++++++++++
> drivers/cache/sifive_ccache.c | 2 +
> 13 files changed, 469 insertions(+), 3 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/riscv/eswin.yaml
> create mode 100644 arch/riscv/boot/dts/eswin/Makefile
> create mode 100644 arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> create mode 100644 arch/riscv/boot/dts/eswin/eic7700.dtsi
>
> --
> 2.25.1
>
>
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