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Fri, 09 May 2025 01:32:07 -0700 (PDT) Date: Fri, 9 May 2025 11:32:04 +0300 From: Dan Carpenter To: Patrice Chotard Cc: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Krzysztof Kozlowski , Catalin Marinas , Will Deacon , christophe.kerello@foss.st.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v11 2/3] memory: Add STM32 Octo Memory Manager driver Message-ID: References: <20250428-upstream_ospi_v6-v11-0-1548736fd9d2@foss.st.com> <20250428-upstream_ospi_v6-v11-2-1548736fd9d2@foss.st.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250428-upstream_ospi_v6-v11-2-1548736fd9d2@foss.st.com> On Mon, Apr 28, 2025 at 10:58:31AM +0200, Patrice Chotard wrote: > +static int stm32_omm_toggle_child_clock(struct device *dev, bool enable) > +{ > + struct stm32_omm *omm = dev_get_drvdata(dev); > + int i, ret; > + > + for (i = 0; i < omm->nb_child; i++) { > + if (enable) { > + ret = clk_prepare_enable(omm->clk_bulk[i + 1].clk); > + if (ret) { > + dev_err(dev, "Can not enable clock\n"); > + goto clk_error; > + } > + } else { > + clk_disable_unprepare(omm->clk_bulk[i + 1].clk); > + } > + } > + > + return 0; > + > +clk_error: > + while (i--) > + clk_disable_unprepare(omm->clk_bulk[i + 1].clk); > + > + return ret; > +} > + > +static int stm32_omm_disable_child(struct device *dev) > +{ > + struct stm32_omm *omm = dev_get_drvdata(dev); > + struct reset_control *reset; > + int ret; > + u8 i; > + > + ret = stm32_omm_toggle_child_clock(dev, true); > + if (!ret) ^^^^ I'm pretty sure this was intended to be if (ret) and the ! is a typo. > + return ret; If it's not a typo please write this as: if (!ret) return 0; regards, dan carpenter > + > + for (i = 0; i < omm->nb_child; i++) { > + /* reset OSPI to ensure CR_EN bit is set to 0 */ > + reset = omm->child_reset[i]; > + ret = reset_control_acquire(reset); > + if (ret) { > + stm32_omm_toggle_child_clock(dev, false); > + dev_err(dev, "Can not acquire resset %d\n", ret); > + return ret; > + } > + > + reset_control_assert(reset); > + udelay(2); > + reset_control_deassert(reset); > + > + reset_control_release(reset); > + } > + > + return stm32_omm_toggle_child_clock(dev, false); > +}