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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a0ad54f105sm4491875f8f.85.2025.05.07.00.55.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 May 2025 00:55:27 -0700 (PDT) Date: Wed, 7 May 2025 09:55:25 +0200 From: Daniel Lezcano To: Fabrice Gasnier Cc: lee@kernel.org, alexandre.torgue@foss.st.com, tglx@linutronix.de, ukleinek@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, jic23@kernel.org, robh@kernel.org, catalin.marinas@arm.com, will@kernel.org, devicetree@vger.kernel.org, wbg@kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-pwm@vger.kernel.org, olivier.moysan@foss.st.com Subject: Re: [PATCH v6 3/7] clocksource: stm32-lptimer: add support for stm32mp25 Message-ID: References: <20250429125133.1574167-1-fabrice.gasnier@foss.st.com> <20250429125133.1574167-4-fabrice.gasnier@foss.st.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250429125133.1574167-4-fabrice.gasnier@foss.st.com> On Tue, Apr 29, 2025 at 02:51:29PM +0200, Fabrice Gasnier wrote: > On stm32mp25, DIER (former IER) must only be modified when the lptimer > is enabled. On earlier SoCs, it must be only be modified when it is > disabled. There's also a new DIEROK flag, to ensure register access > has completed. > Add a new "set_evt" routine to be used on stm32mp25, called depending > on the version register, read by the MFD core (LPTIM_VERR). > > Signed-off-by: Patrick Delaunay > Signed-off-by: Fabrice Gasnier > --- > Changes in V6: > - Fixed warning reported by kernel test robot in > https://lore.kernel.org/oe-kbuild-all/202504261456.aCATBoYN-lkp@intel.com/ > use FIELD_GET() macro > Changes in V5: > - Added a delay after timer enable, it needs two clock cycles. > Changes in V4: > - Daniel suggests to encapsulate IER write into a separate function > that manages the enabling/disabling of the LP timer. In addition, > DIEROK and ARROK flags checks have been added. So adopt a new routine > to set the event into ARR register and enable the interrupt. > Changes in V2: > - rely on fallback compatible as no specific .data is associated to the > driver. Use version data from MFD core. > - Added interrupt enable register access update in (missed in V1) > --- Acked-by: Daniel Lezcano -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog