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s=mail; t=1746683387; bh=9h1xbURXxGWrvKx9QCcbV1QCEaBoQJVsir3FtKD2gCs=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Q7g4GK4QYHgbQRvVz6WueosEuJM3dTt/iuT/Z69kHnZRsG0/sUiBbIyX4qx/VniWK SWoAyq3+YdPBynkoZy8PMBLF/6a8XVwYF5jAGJaYVLPi5fEU+SGJdnbQm1UbgERhb2 knsws/s/c6KJgz3BRpNDaspFV50aUkpi/tE9GlVs9uCLSXth8ItSS7xFnDrato4Z2E nEkHMItd74NUdWtAF7qFWr95LFveUeghbIFwWhVVsKLYQ8iaIJjqrJaDTOo3SpXXaV B9bNrtnQXXwriCcCMqxef2UHdfSuvxPu+lB/kcc2Sk0GnC4zYzfLEo9n64czP8mj89 yRq0ef7LoXY0A== Date: Thu, 8 May 2025 05:49:39 +0000 From: Haylen Chu To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Haylen Chu , Yixun Lan , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, spacemit@lists.linux.dev, Inochi Amaoto , Chen Wang , Jisheng Zhang , Meng Zhang , Alex Elder Subject: Re: [PATCH v8 5/6] riscv: dts: spacemit: Add clock tree for SpacemiT K1 Message-ID: References: <20250416135406.16284-1-heylenay@4d2.org> <20250416135406.16284-6-heylenay@4d2.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250416135406.16284-6-heylenay@4d2.org> Hi Yixun, On Wed, Apr 16, 2025 at 01:54:05PM +0000, Haylen Chu wrote: > Describe the PLL and system controllers that're capable of generating > clock signals in the devicetree. > > Signed-off-by: Haylen Chu > Reviewed-by: Alex Elder > Reviewed-by: Yixun Lan > --- > arch/riscv/boot/dts/spacemit/k1.dtsi | 75 ++++++++++++++++++++++++++++ > 1 file changed, 75 insertions(+) > > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi > index c670ebf8fa12..584f0dbc60f5 100644 > --- a/arch/riscv/boot/dts/spacemit/k1.dtsi > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi I found that I forgot to make the nodenames of syscons consistent: both "system-control" and "system-controller" are used, and pll should be named as "clock-controller" instead. Could you please drop the SoC devicetree patch then I could rework on it and correct the mistake? Or I could follow up a clean up patch if dropping isn't easy or doesn't follow the convention. Thanks for your work, Haylen Chu > @@ -314,6 +346,17 @@ soc { > dma-noncoherent; > ranges; > > + syscon_apbc: system-control@d4015000 { > + compatible = "spacemit,k1-syscon-apbc"; > + reg = <0x0 0xd4015000 0x0 0x1000>; > + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, > + <&vctcxo_24m>; > + clock-names = "osc", "vctcxo_1m", "vctcxo_3m", > + "vctcxo_24m"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > uart0: serial@d4017000 { > compatible = "spacemit,k1-uart", "intel,xscale-uart"; > reg = <0x0 0xd4017000 0x0 0x100>; > @@ -409,6 +452,38 @@ pinctrl: pinctrl@d401e000 { > reg = <0x0 0xd401e000 0x0 0x400>; > }; > > + syscon_mpmu: system-controller@d4050000 { > + compatible = "spacemit,k1-syscon-mpmu"; > + reg = <0x0 0xd4050000 0x0 0x209c>; > + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, > + <&vctcxo_24m>; > + clock-names = "osc", "vctcxo_1m", "vctcxo_3m", > + "vctcxo_24m"; > + #clock-cells = <1>; > + #power-domain-cells = <1>; > + #reset-cells = <1>; > + }; > + > + pll: system-control@d4090000 { > + compatible = "spacemit,k1-pll"; > + reg = <0x0 0xd4090000 0x0 0x1000>; > + clocks = <&vctcxo_24m>; > + spacemit,mpmu = <&syscon_mpmu>; > + #clock-cells = <1>; > + }; > + > + syscon_apmu: system-control@d4282800 { > + compatible = "spacemit,k1-syscon-apmu"; > + reg = <0x0 0xd4282800 0x0 0x400>; > + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, > + <&vctcxo_24m>; > + clock-names = "osc", "vctcxo_1m", "vctcxo_3m", > + "vctcxo_24m"; > + #clock-cells = <1>; > + #power-domain-cells = <1>; > + #reset-cells = <1>; > + }; > + > plic: interrupt-controller@e0000000 { > compatible = "spacemit,k1-plic", "sifive,plic-1.0.0"; > reg = <0x0 0xe0000000 0x0 0x4000000>; > -- > 2.49.0 >