* [PATCH v2 1/7] dt-bindings: iio: adc: Add AD4170
2025-04-28 12:27 [PATCH v2 0/7] iio: adc: Add support for AD4170 series of ADCs Marcelo Schmitt
@ 2025-04-28 12:27 ` Marcelo Schmitt
2025-05-09 18:56 ` Rob Herring
2025-04-28 12:28 ` [PATCH v2 2/7] iio: adc: Add basic support for AD4170 Marcelo Schmitt
` (5 subsequent siblings)
6 siblings, 1 reply; 27+ messages in thread
From: Marcelo Schmitt @ 2025-04-28 12:27 UTC (permalink / raw)
To: linux-iio, devicetree, linux-kernel
Cc: jic23, lars, Michael.Hennerich, dlechner, nuno.sa, andy, robh,
krzk+dt, conor+dt, marcelo.schmitt1
Add device tree documentation for AD4170 and similar sigma-delta ADCs.
The AD4170 is a 24-bit, multichannel, sigma-delta ADC.
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
[device tree changes]
- Referenced adc.yaml from sensor-node.
- Merged property descriptions to reduce doc duplication.
- Every child node type is now in the example.
- Better described sensor-type property with a list of possible types.
- Updated adi,excitation-pins description to cover a use case I had overlooked.
- Added default to interrupt-names and to clock-names.
- Added support for clock-output-names
- Dropped '|' from descriptions when not needed.
- Added extra example
-
.../bindings/iio/adc/adi,ad4170.yaml | 554 ++++++++++++++++++
MAINTAINERS | 7 +
2 files changed, 561 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml
diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml
new file mode 100644
index 000000000000..679825be1f15
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml
@@ -0,0 +1,554 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad4170.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD4170 and similar Analog to Digital Converters
+
+maintainers:
+ - Marcelo Schmitt <marcelo.schmitt@analog.com>
+
+description: |
+ Analog Devices AD4170 series of Sigma-delta Analog to Digital Converters.
+ Specifications can be found at:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ad4170-4.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ad4190-4.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ad4195-4.pdf
+
+$ref: /schemas/spi/spi-peripheral-props.yaml#
+
+$defs:
+ sensor-node:
+ type: object
+ $ref: /schemas/iio/adc/adc.yaml#
+ description:
+ The AD4170 and similar designs have features to aid interfacing with weigh
+ scale, RTD, and thermocouple sensors. Each of those sensor types requires
+ either distinct wiring configuration or external circuitry for proper
+ sensor operation and can use different AD4170 functionality on their
+ setups. A key characteristic of those external sensors is that they must
+ be excited either by voltage supply or by AD4170 excitation signals. The
+ sensor can then be read through a pair of analog inputs. These properties
+ describe external sensor circuitry connected to the ADC.
+
+ properties:
+ reg:
+ description:
+ Channel number. Connects the sensor to the channel with this number
+ of the device.
+ minimum: 1
+ maximum: 16
+
+ diff-channels:
+ description:
+ Defines the ADC input pins used to read sensor data. Only regular
+ analog input pins can be used.
+ items:
+ enum: [0, 1, 2, 3, 4, 5, 6, 7, 8]
+
+ bipolar: true
+
+ adi,sensor-type:
+ description: |
+ Type of sensor connected to the device. Depending on the sensor type
+ (weigh scale, RTD, or thermocouple) the values of sensor-node
+ properties have slightly different constraints. This property
+ specifies which particular external sensor is connected to the ADC so
+ the sensor-node properties can be properly parsed and verified. The
+ possible sensor types are:
+ 0: weigh scale;
+ 1: RTD;
+ 2: thermocouple.
+ $ref: /schemas/types.yaml#/definitions/uint8
+
+ adi,reference-select:
+ description: |
+ Selects the reference source to use when converting on the specific
+ channel. Valid values are:
+ 0: Differential reference voltage REFIN+ - REFIN−.
+ 1: Differential reference voltage REFIN2+ - REFIN2−.
+ 2: Internal 2.5V referece (REFOUT) relative to AVSS.
+ 3: Analog supply voltage (AVDD) relative AVSS.
+ $ref: /schemas/types.yaml#/definitions/uint8
+ enum: [0, 1, 2, 3]
+
+ adi,excitation-ac:
+ type: boolean
+ description:
+ Whether the external sensor has to be AC or DC excited.
+
+ adi,excitation-pins:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description:
+ Pins used to excite the sensor or external circuit that contains the
+ sensor. Thermocouples and RTD sensors are excited either with one
+ current source or with a pair of current sources to minimize the
+ excitation current mismatch and the excitation current drift matching
+ on the ADC. E.g. <0>; <1>; <0 1>. Load cell weigh scales may be
+ excited with one current source, a pair of excitation currents, or two
+ pairs of excitation currents. When four pins are defined, the first
+ two values specify the first pair and the last ones specify the second
+ pair of excitation currents. E.g. <0>; <0 1>; <0 1 2 3>.
+ items:
+ minimum: 0
+ maximum: 20
+
+ adi,excitation-current-microamp:
+ description:
+ Excitation current in microamperes to be output to each excitation pin
+ specified by adi,excitation-pins property. If not provided and
+ adi,excitation-ac is true, use predefined ACX1, ACX1 negated, ACX2,
+ and ACX2 negated signals to AC excite the bridge circuit. Those
+ singals are output on GPIO2, GPIO0, GPIO3, and GPIO1, respectively.
+ enum: [0, 10, 50, 100, 250, 500, 1000, 1500]
+ default: 0
+
+ adi,power-down-switch-pin:
+ description:
+ Number of the GPIO used as power-down switch for the bridge circuit.
+ $ref: /schemas/types.yaml#/definitions/uint8
+ enum: [0, 1]
+
+ adi,vbias:
+ type: boolean
+ description:
+ For unbiased thermocouple applications, the voltage generated by the
+ thermocouple must be biased around some DC voltage. When present, this
+ property specifies a bias voltage of (AVDD + AVSS)/2 to be applied as
+ common-mode voltage for the sensor.
+
+ required:
+ - reg
+ - diff-channels
+ - bipolar
+ - adi,sensor-type
+ - adi,reference-select
+
+
+properties:
+ compatible:
+ enum:
+ - adi,ad4170
+ - adi,ad4190
+ - adi,ad4195
+
+ avss-supply:
+ description:
+ Referece voltage supply for AVSS. If provided, describes the magnitude
+ (absolute value) of the negative voltage supplied to the AVSS pin. Since
+ AVSS must be −2.625V minimum and 0V maximum, the declared supply voltage
+ must be between 0 and 2.65V. If not provided, AVSS is assumed to be at
+ system ground (0V).
+
+ avdd-supply:
+ description:
+ A supply of 4.75V to 5.25V relative to AVSS that powers the chip (AVDD).
+
+ iovdd-supply:
+ description: 1.7V to 5.25V reference supply to the serial interface (IOVDD).
+
+ refin1p-supply:
+ description: REFIN+ supply that can be used as reference for conversion.
+
+ refin1n-supply:
+ description: REFIN- supply that can be used as reference for conversion. If
+ provided, describes the magnitude (absolute value) of the negative voltage
+ supplied to the REFIN- pin.
+
+ refin2p-supply:
+ description: REFIN2+ supply that can be used as reference for conversion.
+
+ refin2n-supply:
+ description: REFIN2- supply that can be used as reference for conversion. If
+ provided, describes the magnitude (absolute value) of the negative voltage
+ supplied to the REFIN2- pin.
+
+ spi-cpol: true
+
+ spi-cpha: true
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ description:
+ Specify which pin should be configured as Data Ready interrupt.
+ enum:
+ - sdo
+ - dig_aux1
+ default: sdo
+
+ clocks:
+ maxItems: 1
+ description:
+ Optional external clock source. Can specify either an external clock or
+ external crystal.
+
+ clock-names:
+ enum:
+ - ext-clk
+ - xtal
+ default: ext-clk
+
+ '#clock-cells':
+ const: 0
+
+ clock-output-names:
+ maxItems: 1
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+ description: |
+ The first cell is for the GPIO number: 0 to 3.
+ The second cell takes standard GPIO flags.
+
+ ldac-gpios:
+ description:
+ GPIO connected to DIG_AUX2 pin to be used as LDAC toggle to control the
+ transfer of data from the DAC_INPUT_A register to the DAC.
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+patternProperties:
+ "^channel@[0-9a-f]$":
+ $ref: adc.yaml
+ type: object
+ unevaluatedProperties: false
+ description:
+ Represents the external channels which are connected to the ADC.
+
+ properties:
+ reg:
+ description:
+ The channel number.
+ minimum: 0
+ maximum: 15
+
+ diff-channels:
+ description: |
+ This property is used for defining the inputs of a differential
+ voltage channel. The first value is the positive input and the second
+ value is the negative input of the channel.
+
+ Besides the analog input pins AIN0 to AIN8, there are special inputs
+ that can be selected with the following values:
+ 17: Internal temperature sensor
+ 18: (AVDD-AVSS)/5
+ 19: (IOVDD-DGND)/5
+ 20: DAC output
+ 21: ALDO
+ 22: DLDO
+ 23: AVSS
+ 24: DGND
+ 25: REFIN+
+ 26: REFIN-
+ 27: REFIN2+
+ 28: REFIN2-
+ 29: REFOUT
+ For the internal temperature sensor, use the input number for both
+ inputs (i.e. diff-channels = <17 17>).
+ items:
+ enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 17, 18, 19, 20, 21, 22, 23, 24, 25,
+ 26, 27, 28, 29]
+
+ single-channel: true
+
+ common-mode-channel: true
+
+ bipolar: true
+
+ adi,buffered-positive:
+ description: |
+ Enable precharge buffer, full buffer, or skip reference buffering of
+ the positive voltage reference. Because the output impedance of the
+ source driving the voltage reference inputs may be dynamic, RC
+ combinations of those inputs can cause DC gain errors if the reference
+ inputs go unbuffered into the ADC. Enable reference buffering if the
+ provided reference source has dynamic high impedance output. Note the
+ absolute voltage allowed on positive reference inputs (REFIN+,
+ REFIN2+) is from AVSS − 50 mV to AVDD + 50 mV when the reference
+ buffers are disabled but narrows to AVSS to AVDD when reference
+ buffering is enabled or in precharge mode.
+ 0: Reference precharge buffer.
+ 1: Full Buffer.
+ 2: Bypass reference buffers (buffering disabled).
+ $ref: /schemas/types.yaml#/definitions/uint8
+ enum: [0, 1, 2]
+ default: 1
+
+ adi,buffered-negative:
+ description: |
+ Enable precharge buffer, full buffer, or skip reference buffering of
+ the negative voltage reference. Because the output impedance of the
+ source driving the voltage reference inputs may be dynamic, RC
+ combinations of those inputs can cause DC gain errors if the reference
+ inputs go unbuffered into the ADC. Enable reference buffering if the
+ provided reference source has dynamic high impedance output. Note the
+ absolute voltage allowed on negative reference inputs (REFIN-,
+ REFIN2-) is from AVSS − 50 mV to AVDD + 50 mV when the reference
+ buffers are disabled but narrows to AVSS to AVDD when reference
+ buffering is enabled or in precharge mode.
+ 0: Reference precharge buffer.
+ 1: Full Buffer.
+ 2: Bypass reference buffers (buffering disabled).
+ $ref: /schemas/types.yaml#/definitions/uint8
+ enum: [0, 1, 2]
+ default: 1
+
+ adi,reference-select:
+ description: |
+ Select the reference source to use when converting on the specific
+ channel. Valid values are:
+ 0: Differential reference voltage REFIN+ - REFIN−.
+ 1: Differential reference voltage REFIN2+ - REFIN2−.
+ 2: Internal 2.5V referece (REFOUT) relative to AVSS.
+ 3: Analog supply voltage (AVDD) relative AVSS.
+ If this field is left empty, the internal reference is selected.
+ $ref: /schemas/types.yaml#/definitions/uint8
+ enum: [0, 1, 2, 3]
+ default: 2
+
+ required:
+ - reg
+
+ allOf:
+ - oneOf:
+ - required: [single-channel]
+ properties:
+ diff-channels: false
+ - required: [diff-channels]
+ properties:
+ single-channel: false
+ common-mode-channel: false
+
+ "^weighscale@":
+ $ref: '#/$defs/sensor-node'
+ unevaluatedProperties: false
+
+ properties:
+ diff-channels: true
+ bipolar: true
+
+ adi,sensor-type:
+ description: Weigh scale sensor.
+ $ref: /schemas/types.yaml#/definitions/uint8
+ const: 0
+
+ adi,excitation-pins: true
+
+ "^rtd@":
+ $ref: '#/$defs/sensor-node'
+ unevaluatedProperties: false
+
+ properties:
+ diff-channels: true
+ bipolar: true
+
+ adi,sensor-type:
+ description: RTD sensor.
+ $ref: /schemas/types.yaml#/definitions/uint8
+ const: 1
+
+ adi,excitation-pins: true
+
+ adi,excitation-current-microamp: true
+
+ required:
+ - adi,excitation-pins
+ - adi,excitation-current-microamp
+
+ "^thermocouple@":
+ $ref: '#/$defs/sensor-node'
+ unevaluatedProperties: false
+
+ properties:
+ diff-channels: true
+ bipolar: true
+
+ adi,sensor-type:
+ description: Thermocouple sensor.
+ $ref: /schemas/types.yaml#/definitions/uint8
+ const: 2
+
+ required:
+ - adi,excitation-pins
+ - adi,excitation-current-microamp
+
+required:
+ - compatible
+ - reg
+ - avdd-supply
+ - iovdd-supply
+ - spi-cpol
+ - spi-cpha
+
+allOf:
+ # Some devices don't have integrated DAC
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,ad4190
+ - adi,ad4195
+ then:
+ properties:
+ ldac-gpios: false
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad4170";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ spi-cpol;
+ spi-cpha;
+ avdd-supply = <&avdd>;
+ iovdd-supply = <&iovdd>;
+ interrupt-parent = <&gpio_in>;
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ // Sample AIN0 with respect to DGND throughout AVDD/DGND input range
+ // Pseudo-differential unipolar
+ channel@0 {
+ reg = <0>;
+ single-channel = <0>;
+ common-mode-channel = <24>;
+ adi,reference-select = /bits/ 8 <3>;
+ };
+ // Weigh scale sensor
+ weighscale@1 {
+ reg = <1>;
+ bipolar;
+ diff-channels = <1 2>;
+ adi,sensor-type = /bits/ 8 <0>;
+ adi,reference-select = /bits/ 8 <0>;
+ adi,excitation-ac;
+ adi,excitation-pins = <19 20>;
+ adi,power-down-switch-pin = /bits/ 8 <0>;
+ };
+ // RTD sensor
+ rtd@2 {
+ reg = <2>;
+ bipolar;
+ diff-channels = <3 4>;
+ adi,sensor-type = /bits/ 8 <1>;
+ adi,reference-select = /bits/ 8 <0>;
+ adi,excitation-ac;
+ adi,excitation-pins = <5 6>;
+ adi,excitation-current-microamp = <500>;
+ };
+ // Thermocouple sensor
+ thermocouple@3 {
+ reg = <3>;
+ bipolar;
+ diff-channels = <7 8>;
+ adi,sensor-type = /bits/ 8 <2>;
+ adi,reference-select = /bits/ 8 <0>;
+ adi,excitation-pins = <18>;
+ adi,excitation-current-microamp = <500>;
+ adi,vbias;
+ };
+ };
+ };
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad4170";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ spi-cpol;
+ spi-cpha;
+ avdd-supply = <&avdd>;
+ iovdd-supply = <&iovdd>;
+ interrupt-parent = <&gpio_in>;
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ // Sample AIN0 with respect to AIN1 throughout AVDD/AVSS input range
+ // Differential bipolar. If AVSS < 0V, differential true bipolar
+ channel@0 {
+ reg = <0>;
+ bipolar;
+ diff-channels = <0 1>;
+ adi,reference-select = /bits/ 8 <3>;
+ };
+ // Sample AIN2 with respect to DGND throughout AVDD/DGND input range
+ // Pseudo-differential unipolar
+ channel@1 {
+ reg = <1>;
+ single-channel = <2>;
+ common-mode-channel = <24>;
+ adi,reference-select = /bits/ 8 <3>;
+ };
+ // Sample AIN3 with respect to 2.5V throughout AVDD/AVSS input range
+ // Pseudo-differential bipolar
+ channel@2 {
+ reg = <2>;
+ bipolar;
+ single-channel = <3>;
+ common-mode-channel = <29>;
+ adi,reference-select = /bits/ 8 <3>;
+ };
+ // Sample AIN4 with respect to DGND throughout AVDD/AVSS input range
+ // Pseudo-differential bipolar
+ channel@3 {
+ reg = <3>;
+ bipolar;
+ single-channel = <4>;
+ common-mode-channel = <24>;
+ adi,reference-select = /bits/ 8 <3>;
+ };
+ // Sample AIN5 with respect to 2.5V throughout AVDD/AVSS input range
+ // Pseudo-differential unipolar (AD4170 datasheet page 46 example)
+ channel@4 {
+ reg = <4>;
+ single-channel = <5>;
+ common-mode-channel = <29>;
+ adi,reference-select = /bits/ 8 <3>;
+ };
+ // Sample AIN6 with respect to 2.5V throughout REFIN+/REFIN- input range
+ // Pseudo-differential bipolar
+ channel@5 {
+ reg = <5>;
+ bipolar;
+ single-channel = <6>;
+ common-mode-channel = <29>;
+ adi,reference-select = /bits/ 8 <0>;
+ };
+ // Weigh scale sensor
+ weighscale@6 {
+ reg = <6>;
+ bipolar;
+ diff-channels = <7 8>;
+ adi,reference-select = /bits/ 8 <0>;
+ adi,sensor-type = /bits/ 8 <0>;
+ adi,excitation-ac;
+ adi,excitation-pins = <17 18 19 20>;
+ };
+ };
+ };
+...
+
diff --git a/MAINTAINERS b/MAINTAINERS
index 030d90d38341..991b6e2e373a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1337,6 +1337,13 @@ F: Documentation/ABI/testing/sysfs-bus-iio-adc-ad4130
F: Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml
F: drivers/iio/adc/ad4130.c
+ANALOG DEVICES INC AD4170 DRIVER
+M: Marcelo Schmitt <marcelo.schmitt@analog.com>
+L: linux-iio@vger.kernel.org
+S: Supported
+W: https://ez.analog.com/linux-software-drivers
+F: Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml
+
ANALOG DEVICES INC AD4695 DRIVER
M: Michael Hennerich <michael.hennerich@analog.com>
M: Nuno Sá <nuno.sa@analog.com>
--
2.47.2
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v2 1/7] dt-bindings: iio: adc: Add AD4170
2025-04-28 12:27 ` [PATCH v2 1/7] dt-bindings: iio: adc: Add AD4170 Marcelo Schmitt
@ 2025-05-09 18:56 ` Rob Herring
2025-05-11 15:27 ` Marcelo Schmitt
0 siblings, 1 reply; 27+ messages in thread
From: Rob Herring @ 2025-05-09 18:56 UTC (permalink / raw)
To: Marcelo Schmitt
Cc: linux-iio, devicetree, linux-kernel, jic23, lars,
Michael.Hennerich, dlechner, nuno.sa, andy, krzk+dt, conor+dt,
marcelo.schmitt1
On Mon, Apr 28, 2025 at 09:27:46AM -0300, Marcelo Schmitt wrote:
> Add device tree documentation for AD4170 and similar sigma-delta ADCs.
> The AD4170 is a 24-bit, multichannel, sigma-delta ADC.
>
> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
> ---
> [device tree changes]
> - Referenced adc.yaml from sensor-node.
> - Merged property descriptions to reduce doc duplication.
> - Every child node type is now in the example.
> - Better described sensor-type property with a list of possible types.
> - Updated adi,excitation-pins description to cover a use case I had overlooked.
> - Added default to interrupt-names and to clock-names.
> - Added support for clock-output-names
> - Dropped '|' from descriptions when not needed.
> - Added extra example
> -
>
> .../bindings/iio/adc/adi,ad4170.yaml | 554 ++++++++++++++++++
> MAINTAINERS | 7 +
> 2 files changed, 561 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml
> new file mode 100644
> index 000000000000..679825be1f15
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml
> @@ -0,0 +1,554 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iio/adc/adi,ad4170.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Analog Devices AD4170 and similar Analog to Digital Converters
> +
> +maintainers:
> + - Marcelo Schmitt <marcelo.schmitt@analog.com>
> +
> +description: |
> + Analog Devices AD4170 series of Sigma-delta Analog to Digital Converters.
> + Specifications can be found at:
> + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4170-4.pdf
> + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4190-4.pdf
> + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4195-4.pdf
> +
> +$ref: /schemas/spi/spi-peripheral-props.yaml#
> +
> +$defs:
> + sensor-node:
> + type: object
> + $ref: /schemas/iio/adc/adc.yaml#
> + description:
> + The AD4170 and similar designs have features to aid interfacing with weigh
> + scale, RTD, and thermocouple sensors. Each of those sensor types requires
> + either distinct wiring configuration or external circuitry for proper
> + sensor operation and can use different AD4170 functionality on their
> + setups. A key characteristic of those external sensors is that they must
> + be excited either by voltage supply or by AD4170 excitation signals. The
> + sensor can then be read through a pair of analog inputs. These properties
> + describe external sensor circuitry connected to the ADC.
> +
> + properties:
> + reg:
> + description:
> + Channel number. Connects the sensor to the channel with this number
> + of the device.
> + minimum: 1
> + maximum: 16
> +
> + diff-channels:
> + description:
> + Defines the ADC input pins used to read sensor data. Only regular
> + analog input pins can be used.
> + items:
> + enum: [0, 1, 2, 3, 4, 5, 6, 7, 8]
> +
> + bipolar: true
> +
> + adi,sensor-type:
> + description: |
> + Type of sensor connected to the device. Depending on the sensor type
> + (weigh scale, RTD, or thermocouple) the values of sensor-node
> + properties have slightly different constraints. This property
> + specifies which particular external sensor is connected to the ADC so
> + the sensor-node properties can be properly parsed and verified. The
> + possible sensor types are:
> + 0: weigh scale;
> + 1: RTD;
> + 2: thermocouple.
> + $ref: /schemas/types.yaml#/definitions/uint8
> +
> + adi,reference-select:
> + description: |
> + Selects the reference source to use when converting on the specific
> + channel. Valid values are:
> + 0: Differential reference voltage REFIN+ - REFIN−.
> + 1: Differential reference voltage REFIN2+ - REFIN2−.
> + 2: Internal 2.5V referece (REFOUT) relative to AVSS.
> + 3: Analog supply voltage (AVDD) relative AVSS.
> + $ref: /schemas/types.yaml#/definitions/uint8
> + enum: [0, 1, 2, 3]
> +
> + adi,excitation-ac:
> + type: boolean
> + description:
> + Whether the external sensor has to be AC or DC excited.
> +
> + adi,excitation-pins:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + description:
> + Pins used to excite the sensor or external circuit that contains the
> + sensor. Thermocouples and RTD sensors are excited either with one
> + current source or with a pair of current sources to minimize the
> + excitation current mismatch and the excitation current drift matching
> + on the ADC. E.g. <0>; <1>; <0 1>. Load cell weigh scales may be
> + excited with one current source, a pair of excitation currents, or two
> + pairs of excitation currents. When four pins are defined, the first
> + two values specify the first pair and the last ones specify the second
> + pair of excitation currents. E.g. <0>; <0 1>; <0 1 2 3>.
> + items:
> + minimum: 0
> + maximum: 20
> +
> + adi,excitation-current-microamp:
> + description:
> + Excitation current in microamperes to be output to each excitation pin
> + specified by adi,excitation-pins property. If not provided and
> + adi,excitation-ac is true, use predefined ACX1, ACX1 negated, ACX2,
> + and ACX2 negated signals to AC excite the bridge circuit. Those
> + singals are output on GPIO2, GPIO0, GPIO3, and GPIO1, respectively.
> + enum: [0, 10, 50, 100, 250, 500, 1000, 1500]
> + default: 0
> +
> + adi,power-down-switch-pin:
> + description:
> + Number of the GPIO used as power-down switch for the bridge circuit.
> + $ref: /schemas/types.yaml#/definitions/uint8
> + enum: [0, 1]
> +
> + adi,vbias:
> + type: boolean
> + description:
> + For unbiased thermocouple applications, the voltage generated by the
> + thermocouple must be biased around some DC voltage. When present, this
> + property specifies a bias voltage of (AVDD + AVSS)/2 to be applied as
> + common-mode voltage for the sensor.
> +
> + required:
> + - reg
> + - diff-channels
> + - bipolar
> + - adi,sensor-type
> + - adi,reference-select
> +
> +
> +properties:
> + compatible:
> + enum:
> + - adi,ad4170
> + - adi,ad4190
> + - adi,ad4195
> +
> + avss-supply:
> + description:
> + Referece voltage supply for AVSS. If provided, describes the magnitude
> + (absolute value) of the negative voltage supplied to the AVSS pin. Since
> + AVSS must be −2.625V minimum and 0V maximum, the declared supply voltage
> + must be between 0 and 2.65V. If not provided, AVSS is assumed to be at
> + system ground (0V).
> +
> + avdd-supply:
> + description:
> + A supply of 4.75V to 5.25V relative to AVSS that powers the chip (AVDD).
> +
> + iovdd-supply:
> + description: 1.7V to 5.25V reference supply to the serial interface (IOVDD).
> +
> + refin1p-supply:
> + description: REFIN+ supply that can be used as reference for conversion.
> +
> + refin1n-supply:
> + description: REFIN- supply that can be used as reference for conversion. If
> + provided, describes the magnitude (absolute value) of the negative voltage
> + supplied to the REFIN- pin.
> +
> + refin2p-supply:
> + description: REFIN2+ supply that can be used as reference for conversion.
> +
> + refin2n-supply:
> + description: REFIN2- supply that can be used as reference for conversion. If
> + provided, describes the magnitude (absolute value) of the negative voltage
> + supplied to the REFIN2- pin.
> +
> + spi-cpol: true
> +
> + spi-cpha: true
> +
> + interrupts:
> + maxItems: 1
> +
> + interrupt-names:
> + description:
> + Specify which pin should be configured as Data Ready interrupt.
> + enum:
> + - sdo
> + - dig_aux1
> + default: sdo
> +
> + clocks:
> + maxItems: 1
> + description:
> + Optional external clock source. Can specify either an external clock or
> + external crystal.
> +
> + clock-names:
> + enum:
> + - ext-clk
> + - xtal
> + default: ext-clk
> +
> + '#clock-cells':
> + const: 0
> +
> + clock-output-names:
> + maxItems: 1
> +
> + gpio-controller: true
> +
> + "#gpio-cells":
> + const: 2
> + description: |
> + The first cell is for the GPIO number: 0 to 3.
> + The second cell takes standard GPIO flags.
> +
> + ldac-gpios:
> + description:
> + GPIO connected to DIG_AUX2 pin to be used as LDAC toggle to control the
> + transfer of data from the DAC_INPUT_A register to the DAC.
> + maxItems: 1
> +
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 0
> +
> +patternProperties:
> + "^channel@[0-9a-f]$":
> + $ref: adc.yaml
> + type: object
> + unevaluatedProperties: false
> + description:
> + Represents the external channels which are connected to the ADC.
> +
> + properties:
> + reg:
> + description:
> + The channel number.
> + minimum: 0
> + maximum: 15
> +
> + diff-channels:
> + description: |
> + This property is used for defining the inputs of a differential
> + voltage channel. The first value is the positive input and the second
> + value is the negative input of the channel.
> +
> + Besides the analog input pins AIN0 to AIN8, there are special inputs
> + that can be selected with the following values:
> + 17: Internal temperature sensor
> + 18: (AVDD-AVSS)/5
> + 19: (IOVDD-DGND)/5
> + 20: DAC output
> + 21: ALDO
> + 22: DLDO
> + 23: AVSS
> + 24: DGND
> + 25: REFIN+
> + 26: REFIN-
> + 27: REFIN2+
> + 28: REFIN2-
> + 29: REFOUT
> + For the internal temperature sensor, use the input number for both
> + inputs (i.e. diff-channels = <17 17>).
> + items:
> + enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 17, 18, 19, 20, 21, 22, 23, 24, 25,
> + 26, 27, 28, 29]
> +
> + single-channel: true
> +
> + common-mode-channel: true
> +
> + bipolar: true
> +
> + adi,buffered-positive:
> + description: |
> + Enable precharge buffer, full buffer, or skip reference buffering of
> + the positive voltage reference. Because the output impedance of the
> + source driving the voltage reference inputs may be dynamic, RC
> + combinations of those inputs can cause DC gain errors if the reference
> + inputs go unbuffered into the ADC. Enable reference buffering if the
> + provided reference source has dynamic high impedance output. Note the
> + absolute voltage allowed on positive reference inputs (REFIN+,
> + REFIN2+) is from AVSS − 50 mV to AVDD + 50 mV when the reference
> + buffers are disabled but narrows to AVSS to AVDD when reference
> + buffering is enabled or in precharge mode.
> + 0: Reference precharge buffer.
> + 1: Full Buffer.
> + 2: Bypass reference buffers (buffering disabled).
> + $ref: /schemas/types.yaml#/definitions/uint8
> + enum: [0, 1, 2]
> + default: 1
> +
> + adi,buffered-negative:
> + description: |
> + Enable precharge buffer, full buffer, or skip reference buffering of
> + the negative voltage reference. Because the output impedance of the
> + source driving the voltage reference inputs may be dynamic, RC
> + combinations of those inputs can cause DC gain errors if the reference
> + inputs go unbuffered into the ADC. Enable reference buffering if the
> + provided reference source has dynamic high impedance output. Note the
> + absolute voltage allowed on negative reference inputs (REFIN-,
> + REFIN2-) is from AVSS − 50 mV to AVDD + 50 mV when the reference
> + buffers are disabled but narrows to AVSS to AVDD when reference
> + buffering is enabled or in precharge mode.
> + 0: Reference precharge buffer.
> + 1: Full Buffer.
> + 2: Bypass reference buffers (buffering disabled).
> + $ref: /schemas/types.yaml#/definitions/uint8
> + enum: [0, 1, 2]
> + default: 1
> +
> + adi,reference-select:
> + description: |
> + Select the reference source to use when converting on the specific
> + channel. Valid values are:
> + 0: Differential reference voltage REFIN+ - REFIN−.
> + 1: Differential reference voltage REFIN2+ - REFIN2−.
> + 2: Internal 2.5V referece (REFOUT) relative to AVSS.
> + 3: Analog supply voltage (AVDD) relative AVSS.
> + If this field is left empty, the internal reference is selected.
> + $ref: /schemas/types.yaml#/definitions/uint8
You already defined the type in the $defs, so no need to do it again.
> + enum: [0, 1, 2, 3]
> + default: 2
> +
> + required:
> + - reg
> +
> + allOf:
Don't need allOf.
> + - oneOf:
> + - required: [single-channel]
> + properties:
> + diff-channels: false
> + - required: [diff-channels]
> + properties:
> + single-channel: false
> + common-mode-channel: false
> +
> + "^weighscale@":
> + $ref: '#/$defs/sensor-node'
> + unevaluatedProperties: false
> +
> + properties:
> + diff-channels: true
> + bipolar: true
> +
> + adi,sensor-type:
> + description: Weigh scale sensor.
> + $ref: /schemas/types.yaml#/definitions/uint8
Already defined the type. And for the rest...
Rob
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 1/7] dt-bindings: iio: adc: Add AD4170
2025-05-09 18:56 ` Rob Herring
@ 2025-05-11 15:27 ` Marcelo Schmitt
0 siblings, 0 replies; 27+ messages in thread
From: Marcelo Schmitt @ 2025-05-11 15:27 UTC (permalink / raw)
To: Rob Herring
Cc: Marcelo Schmitt, linux-iio, devicetree, linux-kernel, jic23, lars,
Michael.Hennerich, dlechner, nuno.sa, andy, krzk+dt, conor+dt
...
> > +
> > + adi,reference-select:
> > + description: |
> > + Select the reference source to use when converting on the specific
> > + channel. Valid values are:
> > + 0: Differential reference voltage REFIN+ - REFIN−.
> > + 1: Differential reference voltage REFIN2+ - REFIN2−.
> > + 2: Internal 2.5V referece (REFOUT) relative to AVSS.
> > + 3: Analog supply voltage (AVDD) relative AVSS.
> > + If this field is left empty, the internal reference is selected.
> > + $ref: /schemas/types.yaml#/definitions/uint8
>
> You already defined the type in the $defs, so no need to do it again.
The ADC channel node doesn't include/reference the sensor-node.
Wouldn't adi,reference-select default to uint32 if the type is dropped?
The issue here is that adi,reference-select is a property that is meaningful
both for conventional ADC channels and for channels connecting to external
sensors. Thus, the unfortunate repetition of the property. Another possibility
would to be add another type for the ad4170 channels. Something like
$defs:
ad4170-channel:
$ref: /schemas/iio/adc/adc.yaml#
adi,reference-select:
....
sensor-node:
type: object
$ref: '#/$defs/ad4170-channel'
...
patternProperties:
"^channel@[0-9a-f]$":
$ref: '#/$defs/ad4170-channel'
...
"^weighscale@":
$ref: '#/$defs/sensor-node'
...
"^rtd@":
$ref: '#/$defs/sensor-node'
...
would that be a better way of having those?
Thanks,
Marcelo
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 2/7] iio: adc: Add basic support for AD4170
2025-04-28 12:27 [PATCH v2 0/7] iio: adc: Add support for AD4170 series of ADCs Marcelo Schmitt
2025-04-28 12:27 ` [PATCH v2 1/7] dt-bindings: iio: adc: Add AD4170 Marcelo Schmitt
@ 2025-04-28 12:28 ` Marcelo Schmitt
2025-05-02 11:28 ` Andy Shevchenko
2025-05-04 18:21 ` Jonathan Cameron
2025-04-28 12:28 ` [PATCH v2 3/7] iio: adc: ad4170: Add support for buffered data capture Marcelo Schmitt
` (4 subsequent siblings)
6 siblings, 2 replies; 27+ messages in thread
From: Marcelo Schmitt @ 2025-04-28 12:28 UTC (permalink / raw)
To: linux-iio, devicetree, linux-kernel
Cc: Ana-Maria Cusco, jic23, lars, Michael.Hennerich, dlechner,
nuno.sa, andy, robh, krzk+dt, conor+dt, marcelo.schmitt1
From: Ana-Maria Cusco <ana-maria.cusco@analog.com>
Add support for the AD4170 ADC with the following features:
- Single-shot read.
- Analog front end PGA configuration.
- Digital filter and sampling frequency configuration.
- Calibration gain and offset configuration.
- Differential and pseudo-differential input configuration.
Signed-off-by: Ana-Maria Cusco <ana-maria.cusco@analog.com>
Co-developed-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
changes since v1
- Replaced 3 regmap configs by regmap with custom reg_read/write implementation.
MAINTAINERS | 1 +
drivers/iio/adc/Kconfig | 12 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/ad4170.c | 1888 ++++++++++++++++++++++++++++++++++++++
4 files changed, 1902 insertions(+)
create mode 100644 drivers/iio/adc/ad4170.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 991b6e2e373a..56cd87028dfd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1343,6 +1343,7 @@ L: linux-iio@vger.kernel.org
S: Supported
W: https://ez.analog.com/linux-software-drivers
F: Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml
+F: drivers/iio/adc/ad4170.c
ANALOG DEVICES INC AD4695 DRIVER
M: Michael Hennerich <michael.hennerich@analog.com>
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 636469392945..d5d0308da007 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -70,6 +70,18 @@ config AD4130
To compile this driver as a module, choose M here: the module will be
called ad4130.
+
+config AD4170
+ tristate "Analog Device AD4170 ADC Driver"
+ depends on SPI
+ select REGMAP_SPI
+ help
+ Say yes here to build support for Analog Devices AD4170 SPI analog
+ to digital converters (ADC).
+
+ To compile this driver as a module, choose M here: the module will be
+ called ad4170.
+
config AD4695
tristate "Analog Device AD4695 ADC Driver"
depends on SPI
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index 07d4b832c42e..d3a1376d1f96 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_AD_SIGMA_DELTA) += ad_sigma_delta.o
obj-$(CONFIG_AD4000) += ad4000.o
obj-$(CONFIG_AD4030) += ad4030.o
obj-$(CONFIG_AD4130) += ad4130.o
+obj-$(CONFIG_AD4170) += ad4170.o
obj-$(CONFIG_AD4695) += ad4695.o
obj-$(CONFIG_AD4851) += ad4851.o
obj-$(CONFIG_AD7091R) += ad7091r-base.o
diff --git a/drivers/iio/adc/ad4170.c b/drivers/iio/adc/ad4170.c
new file mode 100644
index 000000000000..4d0af15cb48d
--- /dev/null
+++ b/drivers/iio/adc/ad4170.c
@@ -0,0 +1,1888 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Analog Devices, Inc.
+ * Author: Ana-Maria Cusco <ana-maria.cusco@analog.com>
+ * Author: Marcelo Schmitt <marcelo.schmitt@analog.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/iio/iio.h>
+#include <linux/iio/sysfs.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/math64.h>
+#include <linux/module.h>
+#include <linux/property.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+#include <linux/spi/spi.h>
+#include <linux/unaligned.h>
+#include <linux/units.h>
+#include <linux/util_macros.h>
+
+/*
+ * AD4170 registers
+ * Multibyte register addresses point to the most significant byte which is the
+ * address to use to get the most significant byte first (address accessed is
+ * decremented by one for each data byte)
+ *
+ * Each register address define follows the AD4170_<REG_NAME>_REG form.
+ * Each mask follows the AD4170_<REG_NAME>_<FIELD_NAME> form.
+ * E.g. AD4170_PIN_MUXING_DIG_AUX2_CTRL_MSK is for accessing DIG_AUX2_CTRL field
+ * of PIN_MUXING_REG.
+ * Each constant follows the AD4170_<REG_NAME>_<FIELD_NAME>_<FUNCTION> form.
+ * E.g. AD4170_PIN_MUXING_DIG_AUX2_DISABLED is the value written to
+ * DIG_AUX2_CTRL field of PIN_MUXING register to disable DIG_AUX2 pin.
+ * Some register names and register field names are shortened versions of
+ * their datasheet counterpart names to provide better code readability.
+ */
+#define AD4170_CONFIG_A_REG 0x00
+#define AD4170_DATA_24B_REG 0x1E
+#define AD4170_PIN_MUXING_REG 0x69
+#define AD4170_ADC_CTRL_REG 0x71
+#define AD4170_CHAN_EN_REG 0x79
+#define AD4170_CHAN_SETUP_REG(x) (0x81 + 4 * (x))
+#define AD4170_CHAN_MAP_REG(x) (0x83 + 4 * (x))
+#define AD4170_MISC_REG(x) (0xC1 + 14 * (x))
+#define AD4170_AFE_REG(x) (0xC3 + 14 * (x))
+#define AD4170_FILTER_REG(x) (0xC5 + 14 * (x))
+#define AD4170_FILTER_FS_REG(x) (0xC7 + 14 * (x))
+#define AD4170_OFFSET_REG(x) (0xCA + 14 * (x))
+#define AD4170_GAIN_REG(x) (0xCD + 14 * (x))
+
+#define AD4170_REG_READ_MASK BIT(14)
+
+/* AD4170_CONFIG_A_REG - INTERFACE_CONFIG_A REGISTER */
+#define AD4170_SW_RESET_MSK (BIT(7) | BIT(0))
+
+/* AD4170_PIN_MUXING_REG */
+#define AD4170_PIN_MUXING_DIG_AUX2_CTRL_MSK GENMASK(7, 6)
+#define AD4170_PIN_MUXING_DIG_AUX1_CTRL_MSK GENMASK(5, 4)
+#define AD4170_PIN_MUXING_SYNC_CTRL_MSK GENMASK(3, 2)
+
+/* AD4170_ADC_CTRL_REG */
+#define AD4170_ADC_CTRL_MULTI_DATA_REG_SEL_MSK BIT(7)
+#define AD4170_ADC_CTRL_CONT_READ_MSK GENMASK(5, 4)
+#define AD4170_ADC_CTRL_MODE_MSK GENMASK(3, 0)
+
+/* AD4170_CHAN_EN_REG */
+#define AD4170_CHAN_EN(ch) BIT(ch)
+
+/* AD4170_CHAN_SETUP_REG */
+#define AD4170_CHAN_SETUP_SETUP_MSK GENMASK(2, 0)
+
+/* AD4170_CHAN_MAP_REG */
+#define AD4170_CHAN_MAP_AINP_MSK GENMASK(12, 8)
+#define AD4170_CHAN_MAP_AINM_MSK GENMASK(4, 0)
+
+/* AD4170_MISC_REG */
+#define AD4170_MISC_CHOP_IEXC_MSK GENMASK(15, 14)
+#define AD4170_MISC_CHOP_ADC_MSK GENMASK(9, 8)
+#define AD4170_MISC_BURNOUT_MSK GENMASK(1, 0)
+
+/* AD4170_AFE_REG */
+#define AD4170_AFE_REF_BUF_M_MSK GENMASK(11, 10)
+#define AD4170_AFE_REF_BUF_P_MSK GENMASK(9, 8)
+#define AD4170_AFE_REF_SELECT_MSK GENMASK(6, 5)
+#define AD4170_AFE_BIPOLAR_MSK BIT(4)
+#define AD4170_AFE_PGA_GAIN_MSK GENMASK(3, 0)
+
+/* AD4170_FILTER_REG */
+#define AD4170_FILTER_FILTER_TYPE_MSK GENMASK(3, 0)
+
+/* AD4170 register constants */
+
+/* AD4170_CHAN_MAP_REG constants */
+#define AD4170_CHAN_MAP_AIN0 0
+#define AD4170_CHAN_MAP_AIN1 1
+#define AD4170_CHAN_MAP_AIN2 2
+#define AD4170_CHAN_MAP_AIN3 3
+#define AD4170_CHAN_MAP_AIN4 4
+#define AD4170_CHAN_MAP_AIN5 5
+#define AD4170_CHAN_MAP_AIN6 6
+#define AD4170_CHAN_MAP_AIN7 7
+#define AD4170_CHAN_MAP_AIN8 8
+#define AD4170_CHAN_MAP_TEMP_SENSOR 17
+#define AD4170_CHAN_MAP_AVDD_AVSS_P 18
+#define AD4170_CHAN_MAP_AVDD_AVSS_N 18
+#define AD4170_CHAN_MAP_IOVDD_DGND_P 19
+#define AD4170_CHAN_MAP_IOVDD_DGND_N 19
+#define AD4170_CHAN_MAP_DAC_P 20
+#define AD4170_CHAN_MAP_DAC_N 20
+#define AD4170_CHAN_MAP_ALDO 21
+#define AD4170_CHAN_MAP_DLDO 22
+#define AD4170_CHAN_MAP_AVSS 23
+#define AD4170_CHAN_MAP_DGND 24
+#define AD4170_CHAN_MAP_REFIN1_P 25
+#define AD4170_CHAN_MAP_REFIN1_N 26
+#define AD4170_CHAN_MAP_REFIN2_P 27
+#define AD4170_CHAN_MAP_REFIN2_N 28
+#define AD4170_CHAN_MAP_REFOUT 29
+
+/* AD4170_PIN_MUXING_REG constants */
+#define AD4170_PIN_MUXING_DIG_AUX1_DISABLED 0x0
+#define AD4170_PIN_MUXING_DIG_AUX1_RDY 0x1
+#define AD4170_PIN_MUXING_DIG_AUX1_SYNC 0x2
+
+#define AD4170_PIN_MUXING_DIG_AUX2_DISABLED 0x0
+#define AD4170_PIN_MUXING_DIG_AUX2_LDAC 0x1
+#define AD4170_PIN_MUXING_DIG_AUX2_SYNC 0x2
+
+#define AD4170_PIN_MUXING_SYNC_DISABLED 0x0
+#define AD4170_PIN_MUXING_SYNC_STANDARD 0x1
+#define AD4170_PIN_MUXING_SYNC_ALTERNATE 0x2
+
+/* AD4170_ADC_CTRL_REG constants */
+#define AD4170_ADC_CTRL_CONT_READ_DISABLE 0x0
+#define AD4170_ADC_CTRL_CONT_READ_ENABLE 0x1
+
+#define AD4170_ADC_CTRL_MODE_CONT 0x0
+#define AD4170_ADC_CTRL_MODE_SINGLE 0x4
+#define AD4170_ADC_CTRL_MODE_IDLE 0x7
+
+/* AD4170_FILTER_REG constants */
+#define AD4170_FILTER_FILTER_TYPE_SINC5_AVG 0x0
+#define AD4170_FILTER_FILTER_TYPE_SINC5 0x4
+#define AD4170_FILTER_FILTER_TYPE_SINC3 0x6
+
+/* Device properties and auxiliary constants */
+
+#define AD4170_NUM_ANALOG_PINS 9
+#define AD4170_MAX_CHANNELS 16
+#define AD4170_MAX_ANALOG_PINS 8
+#define AD4170_MAX_SETUPS 8
+#define AD4170_INVALID_SETUP 9
+#define AD4170_SPI_MAX_XFER_LEN 6
+#define AD4170_NUM_CURRENT_SRC 4
+#define AD4170_DEFAULT_SAMP_RATE (125 * KILO)
+
+/* Internal and external clock properties */
+#define AD4170_INT_CLOCK_16MHZ (16 * MEGA)
+#define AD4170_EXT_CLOCK_MHZ_MIN (1 * MEGA)
+#define AD4170_EXT_CLOCK_MHZ_MAX (17 * MEGA)
+
+#define AD4170_NUM_PGA_OPTIONS 10
+
+/* Digital filter properties */
+#define AD4170_SINC3_MIN_FS 4
+#define AD4170_SINC3_MAX_FS 65532
+#define AD4170_SINC5_MIN_FS 1
+#define AD4170_SINC5_MAX_FS 256
+
+#define AD4170_GAIN_REG_DEFAULT 0x555555
+
+#define AD4170_ADC_CTRL_CONT_READ_EXIT 0xA5
+
+/* Analog pin functions */
+#define AD4170_PIN_UNASIGNED 0x00
+#define AD4170_PIN_ANALOG_IN 0x01
+#define AD4170_PIN_CURRENT_OUT 0x02
+
+static const unsigned int ad4170_reg_size[] = {
+ [AD4170_CONFIG_A_REG] = 1,
+ [AD4170_DATA_24B_REG] = 3,
+ [AD4170_PIN_MUXING_REG] = 2,
+ [AD4170_ADC_CTRL_REG] = 2,
+ [AD4170_CHAN_EN_REG] = 2,
+ /*
+ * CHANNEL_SETUP and CHANNEL_MAP register are all 2 byte size each and
+ * their addresses are interleaved such that we have CHANNEL_SETUP0
+ * address followed by CHANNEL_MAP0 address, followed by CHANNEL_SETUP1,
+ * and so on until CHANNEL_MAP15.
+ * Thus, initialize the register size for them only once.
+ */
+ [AD4170_CHAN_SETUP_REG(0) ... AD4170_CHAN_MAP_REG(AD4170_MAX_CHANNELS - 1)] = 2,
+ /*
+ * MISC, AFE, FILTER, FILTER_FS, OFFSET, and GAIN register addresses are
+ * also interleaved but MISC, AFE, FILTER, FILTER_FS, OFFSET are 16-bit
+ * while OFFSET, GAIN are 24-bit registers so we can't init them all to
+ * the same size.
+ */
+ [AD4170_MISC_REG(0) ... AD4170_FILTER_FS_REG(0)] = 2,
+ [AD4170_MISC_REG(1) ... AD4170_FILTER_FS_REG(1)] = 2,
+ [AD4170_MISC_REG(2) ... AD4170_FILTER_FS_REG(2)] = 2,
+ [AD4170_MISC_REG(3) ... AD4170_FILTER_FS_REG(3)] = 2,
+ [AD4170_MISC_REG(4) ... AD4170_FILTER_FS_REG(4)] = 2,
+ [AD4170_MISC_REG(5) ... AD4170_FILTER_FS_REG(5)] = 2,
+ [AD4170_MISC_REG(6) ... AD4170_FILTER_FS_REG(6)] = 2,
+ [AD4170_MISC_REG(7) ... AD4170_FILTER_FS_REG(7)] = 2,
+ /* Init OFFSET register size */
+ /* Init GAIN register size */
+ [AD4170_OFFSET_REG(0) ... AD4170_GAIN_REG(0)] = 3,
+ [AD4170_OFFSET_REG(1) ... AD4170_GAIN_REG(1)] = 3,
+ [AD4170_OFFSET_REG(2) ... AD4170_GAIN_REG(2)] = 3,
+ [AD4170_OFFSET_REG(3) ... AD4170_GAIN_REG(3)] = 3,
+ [AD4170_OFFSET_REG(4) ... AD4170_GAIN_REG(4)] = 3,
+ [AD4170_OFFSET_REG(5) ... AD4170_GAIN_REG(5)] = 3,
+ [AD4170_OFFSET_REG(6) ... AD4170_GAIN_REG(6)] = 3,
+ [AD4170_OFFSET_REG(7) ... AD4170_GAIN_REG(7)] = 3,
+};
+
+enum ad4170_ref_buf {
+ AD4170_REF_BUF_PRE, /* Pre-charge referrence buffer */
+ AD4170_REF_BUF_FULL, /* Full referrence buffering */
+ AD4170_REF_BUF_BYPASS /* Bypass referrence buffering */
+};
+
+enum ad4170_ref_select {
+ AD4170_REF_REFIN1,
+ AD4170_REF_REFIN2,
+ AD4170_REF_REFOUT,
+ AD4170_REF_AVDD
+};
+
+enum ad4170_filter_type {
+ AD4170_SINC5_AVG,
+ AD4170_SINC5,
+ AD4170_SINC3,
+};
+
+enum ad4170_regulator {
+ AD4170_AVDD_SUP,
+ AD4170_AVSS_SUP,
+ AD4170_IOVDD_SUP,
+ AD4170_REFIN1P_SUP,
+ AD4170_REFIN1N_SUP,
+ AD4170_REFIN2P_SUP,
+ AD4170_REFIN2N_SUP,
+ AD4170_MAX_SUP
+};
+
+enum ad4170_int_pin_sel {
+ AD4170_INT_PIN_SDO,
+ AD4170_INT_PIN_DIG_AUX1,
+};
+
+static const char * const ad4170_int_pin_names[] = {
+ [AD4170_INT_PIN_SDO] = "sdo",
+ [AD4170_INT_PIN_DIG_AUX1] = "dig_aux1",
+};
+
+static const unsigned int ad4170_sinc3_filt_fs_tbl[] = {
+ 4, 8, 12, 16, 20, 40, 48, 80, 100, 256, 500, 1000, 5000, 8332, 10000,
+ 25000, 50000, 65532,
+};
+
+#define AD4170_MAX_FS_TBL_SIZE ARRAY_SIZE(ad4170_sinc3_filt_fs_tbl)
+
+static const unsigned int ad4170_sinc5_filt_fs_tbl[] = {
+ 1, 2, 4, 8, 12, 16, 20, 40, 48, 80, 100, 256,
+};
+
+struct ad4170_chip_info {
+ const char *name;
+};
+
+static const struct ad4170_chip_info ad4170_chip_info = {
+ .name = "ad4170",
+};
+
+static const struct ad4170_chip_info ad4190_chip_info = {
+ .name = "ad4190",
+};
+
+static const struct ad4170_chip_info ad4195_chip_info = {
+ .name = "ad4195",
+};
+
+/*
+ * There are 8 of each MISC, AFE, FILTER, FILTER_FS, OFFSET, and GAIN
+ * configuration registers. That is, there are 8 miscellaneous registers, MISC0
+ * to MISC7. Each MISC register is associated with a setup; MISCN is associated
+ * with setup number N. The other 5 above mentioned types of registers have
+ * analogous structure. A setup is a set of those registers. For example,
+ * setup 1 comprises of MISC1, AFE1, FILTER1, FILTER_FS1, OFFSET1, and GAIN1
+ * registers. Also, there are 16 CHANNEL_SETUP registers (CHANNEL_SETUP0 to
+ * CHANNEL_SETUP15). Each channel setup is associated with one of the 8 possible
+ * setups. Thus, AD4170 can support up to 16 channels but, since there are only
+ * 8 available setups, channels must share settings if more than 8 channels are
+ * configured.
+ */
+struct ad4170_setup {
+ u16 misc;
+ u16 afe;
+ u16 filter;
+ u16 filter_fs;
+ u32 offset; /* For calibration purposes */
+ u32 gain; /* For calibration purposes */
+};
+
+struct ad4170_setup_info {
+ struct ad4170_setup setup;
+ unsigned int enabled_channels;
+ unsigned int channels;
+};
+
+struct ad4170_chan_info {
+ int setup_num; /* Index to access state setup_infos array */
+ struct ad4170_setup setup; /* cached setup */
+ int input_range_uv;
+ u32 scale_tbl[10][2];
+ int offset_tbl[10];
+ bool initialized;
+ bool enabled;
+};
+
+static const char * const ad4170_filt_names[] = {
+ [AD4170_SINC5_AVG] = "sinc5+avg",
+ [AD4170_SINC5] = "sinc5",
+ [AD4170_SINC3] = "sinc3",
+};
+
+struct ad4170_state {
+ struct regmap *regmap;
+ struct spi_device *spi;
+ int vrefs_uv[AD4170_MAX_SUP];
+ struct mutex lock; /* Protect read-modify-write and multi write sequences */
+ struct iio_chan_spec chans[AD4170_MAX_CHANNELS];
+ struct ad4170_chan_info chan_infos[AD4170_MAX_CHANNELS];
+ struct ad4170_setup_info setup_infos[AD4170_MAX_SETUPS];
+ u32 mclk_hz;
+ int pins_fn[AD4170_NUM_ANALOG_PINS];
+ u32 int_pin_sel;
+ int sps_tbl[ARRAY_SIZE(ad4170_filt_names)][AD4170_MAX_FS_TBL_SIZE][2];
+ struct completion completion;
+ /*
+ * DMA (thus cache coherency maintenance) requires the transfer buffers
+ * to live in their own cache lines.
+ */
+ u8 tx_buf[AD4170_SPI_MAX_XFER_LEN] __aligned(IIO_DMA_MINALIGN);
+ u8 rx_buf[AD4170_SPI_MAX_XFER_LEN];
+};
+
+static void ad4170_fill_sps_tbl(struct ad4170_state *st)
+{
+ unsigned int tmp0, tmp1, i;
+
+ /*
+ * The ODR can be calculated the same way for sinc5+avg, sinc5, and
+ * sinc3 filter types with the exception that sinc5 filter has a
+ * narrowed range of allowed FILTER_FS values.
+ */
+ for (i = 0; i < ARRAY_SIZE(ad4170_sinc3_filt_fs_tbl); i++) {
+ tmp0 = div_u64_rem(st->mclk_hz, 32 * ad4170_sinc3_filt_fs_tbl[i],
+ &tmp1);
+ tmp1 = mult_frac(tmp1, MICRO, 32 * ad4170_sinc3_filt_fs_tbl[i]);
+ /* Fill sinc5+avg filter SPS table */
+ st->sps_tbl[AD4170_SINC5_AVG][i][0] = tmp0; /* Integer part */
+ st->sps_tbl[AD4170_SINC5_AVG][i][1] = tmp1; /* Fractional part */
+
+ /* Fill sinc3 filter SPS table */
+ st->sps_tbl[AD4170_SINC3][i][0] = tmp0; /* Integer part */
+ st->sps_tbl[AD4170_SINC3][i][1] = tmp1; /* Fractional part */
+ }
+ /* Sinc5 filter ODR doesn't use all FILTER_FS bits */
+ for (i = 0; i < ARRAY_SIZE(ad4170_sinc5_filt_fs_tbl); i++) {
+ tmp0 = div_u64_rem(st->mclk_hz, 32 * ad4170_sinc5_filt_fs_tbl[i],
+ &tmp1);
+ tmp1 = mult_frac(tmp1, MICRO, 32 * ad4170_sinc5_filt_fs_tbl[i]);
+ /* Fill sinc5 filter SPS table */
+ st->sps_tbl[AD4170_SINC5][i][0] = tmp0; /* Integer part */
+ st->sps_tbl[AD4170_SINC5][i][1] = tmp1; /* Fractional part */
+ }
+}
+
+static int ad4170_debugfs_reg_access(struct iio_dev *indio_dev,
+ unsigned int reg, unsigned int writeval,
+ unsigned int *readval)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ int ret = -EINVAL;
+
+ if (readval)
+ ret = regmap_read(st->regmap, reg, readval);
+ else
+ ret = regmap_write(st->regmap, reg, writeval);
+
+ return ret;
+}
+
+static int ad4170_get_reg_size(struct ad4170_state *st, unsigned int reg,
+ unsigned int *size)
+{
+ if (reg >= ARRAY_SIZE(ad4170_reg_size))
+ return -EINVAL;
+
+ *size = ad4170_reg_size[reg];
+
+ return 0;
+}
+
+static int ad4170_reg_write(void *context, unsigned int reg, unsigned int val)
+{
+ struct ad4170_state *st = context;
+ unsigned int size;
+ int ret;
+
+ ret = ad4170_get_reg_size(st, reg, &size);
+ if (ret)
+ return ret;
+
+ put_unaligned_be16(reg, st->tx_buf);
+ switch (size) {
+ case 3:
+ put_unaligned_be24(val, &st->tx_buf[2]);
+ break;
+ case 2:
+ put_unaligned_be16(val, &st->tx_buf[2]);
+ break;
+ case 1:
+ st->tx_buf[2] = val;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return spi_write(st->spi, st->tx_buf, size + 2);
+}
+
+static int ad4170_reg_read(void *context, unsigned int reg, unsigned int *val)
+{
+ struct ad4170_state *st = context;
+ struct spi_transfer t[] = {
+ {
+ .tx_buf = st->tx_buf,
+ .len = 2,
+ },
+ {
+ .rx_buf = st->rx_buf,
+ },
+ };
+ unsigned int size;
+ int ret;
+
+ ret = ad4170_get_reg_size(st, reg, &size);
+ if (ret)
+ return ret;
+
+ put_unaligned_be16(AD4170_REG_READ_MASK | reg, st->tx_buf);
+ t[1].len = size;
+
+ ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
+ if (ret)
+ return ret;
+
+ switch (size) {
+ case 3:
+ *val = get_unaligned_be24(st->rx_buf);
+ break;
+ case 2:
+ *val = get_unaligned_be16(st->rx_buf);
+ break;
+ case 1:
+ *val = st->rx_buf[0];
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct regmap_config ad4170_regmap_config = {
+ .reg_read = ad4170_reg_read,
+ .reg_write = ad4170_reg_write,
+};
+
+static int ad4170_find_setup(struct ad4170_state *st,
+ struct ad4170_setup *target_setup,
+ unsigned int *setup_num, bool *overwrite)
+{
+ unsigned int i;
+
+ *setup_num = AD4170_INVALID_SETUP;
+ *overwrite = false;
+
+ for (i = 0; i < AD4170_MAX_SETUPS; i++) {
+ struct ad4170_setup_info *setup_info = &st->setup_infos[i];
+
+ /* Immediately accept a matching setup. */
+ if (!memcmp(target_setup, &setup_info->setup,
+ sizeof(*target_setup))) {
+ *setup_num = i;
+ return 0;
+ }
+
+ /* Ignore all setups which are used by enabled channels. */
+ if (setup_info->enabled_channels)
+ continue;
+
+ /* Find the least used slot. */
+ if (*setup_num == AD4170_INVALID_SETUP ||
+ setup_info->channels < st->setup_infos[*setup_num].channels)
+ *setup_num = i;
+ }
+
+ if (*setup_num == AD4170_INVALID_SETUP)
+ return -EINVAL;
+
+ *overwrite = true;
+ return 0;
+}
+
+static void ad4170_unlink_channel(struct ad4170_state *st, unsigned int channel)
+{
+ struct ad4170_chan_info *chan_info = &st->chan_infos[channel];
+ struct ad4170_setup_info *setup_info = &st->setup_infos[chan_info->setup_num];
+
+ chan_info->setup_num = AD4170_INVALID_SETUP;
+ setup_info->channels--;
+}
+
+static int ad4170_unlink_setup(struct ad4170_state *st, unsigned int setup_num)
+{
+ unsigned int i;
+
+ for (i = 0; i < AD4170_MAX_CHANNELS; i++) {
+ struct ad4170_chan_info *chan_info = &st->chan_infos[i];
+
+ if (!chan_info->initialized || chan_info->setup_num != setup_num)
+ continue;
+
+ ad4170_unlink_channel(st, i);
+ }
+ return 0;
+}
+
+static int ad4170_link_channel_setup(struct ad4170_state *st,
+ unsigned int chan_addr,
+ unsigned int setup_num)
+{
+ struct ad4170_setup_info *setup_info = &st->setup_infos[setup_num];
+ struct ad4170_chan_info *chan_info = &st->chan_infos[chan_addr];
+ int ret;
+
+ ret = regmap_update_bits(st->regmap, AD4170_CHAN_SETUP_REG(chan_addr),
+ AD4170_CHAN_SETUP_SETUP_MSK,
+ FIELD_PREP(AD4170_CHAN_SETUP_SETUP_MSK,
+ setup_num));
+ if (ret)
+ return ret;
+
+ chan_info->setup_num = setup_num;
+ setup_info->channels++;
+ return 0;
+}
+
+/*
+ * Sets the ADC operating mode. Supported modes are
+ * - Continuous conversion mode (default)
+ * - Single conversion mode
+ * - Idle mode
+ */
+static int ad4170_set_mode(struct ad4170_state *st, unsigned int mode)
+{
+ return regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG,
+ AD4170_ADC_CTRL_MODE_MSK,
+ FIELD_PREP(AD4170_ADC_CTRL_MODE_MSK, mode));
+}
+
+static int ad4170_write_setup(struct ad4170_state *st, unsigned int setup_num,
+ struct ad4170_setup *setup)
+{
+ int ret;
+
+ /*
+ * It is recommended to place the ADC in standby mode or idle mode to
+ * write to OFFSET and GAIN registers.
+ */
+ ret = ad4170_set_mode(st, AD4170_ADC_CTRL_MODE_IDLE);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(st->regmap, AD4170_MISC_REG(setup_num), setup->misc);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(st->regmap, AD4170_AFE_REG(setup_num), setup->afe);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(st->regmap, AD4170_FILTER_REG(setup_num),
+ setup->filter);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(st->regmap, AD4170_FILTER_FS_REG(setup_num),
+ setup->filter_fs);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(st->regmap, AD4170_OFFSET_REG(setup_num),
+ setup->offset);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(st->regmap, AD4170_GAIN_REG(setup_num), setup->gain);
+ if (ret)
+ return ret;
+
+ memcpy(&st->setup_infos[setup_num].setup, setup, sizeof(*setup));
+ return 0;
+}
+
+static int ad4170_write_channel_setup(struct ad4170_state *st,
+ unsigned int chan_addr, bool on_enable)
+{
+ struct ad4170_chan_info *chan_info = &st->chan_infos[chan_addr];
+ bool overwrite;
+ int setup_num;
+ int ret;
+
+ /*
+ * Similar to AD4130 driver, the following cases need to be handled.
+ *
+ * 1. Enabled and linked channel with setup changes:
+ * - Find a setup. If not possible, return error.
+ * - Unlink channel from current setup.
+ * - If the setup found has only disabled channels linked to it,
+ * unlink all channels, and write the new setup to it.
+ * - Link channel to new setup.
+ *
+ * 2. Soon to be enabled and unlinked channel:
+ * - Find a setup. If not possible, return error.
+ * - If the setup found has only disabled channels linked to it,
+ * unlink all channels, and write the new setup to it.
+ * - Link channel to the setup.
+ *
+ * 3. Disabled and linked channel with setup changes:
+ * - Unlink channel from current setup.
+ *
+ * 4. Soon to be enabled and linked channel:
+ * 5. Disabled and unlinked channel with setup changes:
+ * - Do nothing.
+ */
+
+ /* Case 4 */
+ if (on_enable && chan_info->setup_num != AD4170_INVALID_SETUP)
+ return 0;
+
+ if (!on_enable && !chan_info->enabled) {
+ if (chan_info->setup_num != AD4170_INVALID_SETUP)
+ /* Case 3 */
+ ad4170_unlink_channel(st, chan_addr);
+
+ /* Cases 3 & 5 */
+ return 0;
+ }
+
+ /* Cases 1 & 2 */
+ ret = ad4170_find_setup(st, &chan_info->setup, &setup_num, &overwrite);
+ if (ret)
+ return ret;
+
+ if (chan_info->setup_num != AD4170_INVALID_SETUP)
+ /* Case 1 */
+ ad4170_unlink_channel(st, chan_addr);
+
+ if (overwrite) {
+ ret = ad4170_unlink_setup(st, setup_num);
+ if (ret)
+ return ret;
+
+ ret = ad4170_write_setup(st, setup_num, &chan_info->setup);
+ if (ret)
+ return ret;
+ }
+
+ return ad4170_link_channel_setup(st, chan_addr, setup_num);
+}
+
+static int ad4170_set_channel_enable(struct ad4170_state *st,
+ unsigned int chan_addr, bool status)
+{
+ struct ad4170_chan_info *chan_info = &st->chan_infos[chan_addr];
+ struct ad4170_setup_info *setup_info;
+ int ret;
+
+ if (chan_info->enabled == status)
+ return 0;
+
+ if (status) {
+ ret = ad4170_write_channel_setup(st, chan_addr, true);
+ if (ret)
+ return ret;
+ }
+
+ setup_info = &st->setup_infos[chan_info->setup_num];
+
+ ret = regmap_update_bits(st->regmap, AD4170_CHAN_EN_REG,
+ AD4170_CHAN_EN(chan_addr),
+ status ? AD4170_CHAN_EN(chan_addr) : 0);
+ if (ret)
+ return ret;
+
+ setup_info->enabled_channels += status ? 1 : -1;
+ chan_info->enabled = status;
+ return 0;
+}
+
+static int __ad4170_get_filter_type(unsigned int filter)
+{
+ u16 f_conf = FIELD_GET(AD4170_FILTER_FILTER_TYPE_MSK, filter);
+
+ switch (f_conf) {
+ case AD4170_FILTER_FILTER_TYPE_SINC5_AVG:
+ return AD4170_SINC5_AVG;
+ case AD4170_FILTER_FILTER_TYPE_SINC5:
+ return AD4170_SINC5;
+ case AD4170_FILTER_FILTER_TYPE_SINC3:
+ return AD4170_SINC3;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int ad4170_set_filter_type(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ unsigned int val)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
+ struct ad4170_setup *setup = &chan_info->setup;
+ unsigned int old_filter_fs, old_filter, filter_type_conf;
+ int ret = 0;
+
+ switch (val) {
+ case AD4170_SINC5_AVG:
+ filter_type_conf = AD4170_FILTER_FILTER_TYPE_SINC5_AVG;
+ break;
+ case AD4170_SINC5:
+ filter_type_conf = AD4170_FILTER_FILTER_TYPE_SINC5;
+ break;
+ case AD4170_SINC3:
+ filter_type_conf = AD4170_FILTER_FILTER_TYPE_SINC3;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (!iio_device_claim_direct(indio_dev))
+ return -EBUSY;
+
+ guard(mutex)(&st->lock);
+ /*
+ * The filters provide the same ODR for a given filter_fs value but
+ * there are different minimum and maximum filter_fs limits for each
+ * filter. The filter_fs value will be adjusted if the current filter_fs
+ * is out of the limits of the just requested filter. Since the
+ * filter_fs value affects the ODR (sampling_frequency), changing the
+ * filter may lead to a change in the sampling frequency.
+ */
+ old_filter = setup->filter;
+ old_filter_fs = setup->filter_fs;
+ if (val == AD4170_SINC5_AVG || val == AD4170_SINC3) {
+ if (setup->filter_fs < AD4170_SINC3_MIN_FS)
+ setup->filter_fs = AD4170_SINC3_MIN_FS;
+ if (setup->filter_fs > AD4170_SINC3_MAX_FS)
+ setup->filter_fs = AD4170_SINC3_MAX_FS;
+
+ } else if (val == AD4170_SINC5) {
+ if (setup->filter_fs < AD4170_SINC5_MIN_FS)
+ setup->filter_fs = AD4170_SINC5_MIN_FS;
+ if (setup->filter_fs > AD4170_SINC5_MAX_FS)
+ setup->filter_fs = AD4170_SINC5_MAX_FS;
+ }
+
+ setup->filter &= ~AD4170_FILTER_FILTER_TYPE_MSK;
+ setup->filter |= FIELD_PREP(AD4170_FILTER_FILTER_TYPE_MSK,
+ filter_type_conf);
+
+ ret = ad4170_write_channel_setup(st, chan->address, false);
+ if (ret) {
+ setup->filter = old_filter;
+ setup->filter_fs = old_filter_fs;
+ }
+
+ iio_device_release_direct(indio_dev);
+ return ret;
+}
+
+static int ad4170_get_filter_type(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
+ struct ad4170_setup *setup = &chan_info->setup;
+
+ return __ad4170_get_filter_type(setup->filter);
+}
+
+static const struct iio_enum ad4170_filter_type_enum = {
+ .items = ad4170_filt_names,
+ .num_items = ARRAY_SIZE(ad4170_filt_names),
+ .get = ad4170_get_filter_type,
+ .set = ad4170_set_filter_type,
+};
+
+static const struct iio_chan_spec_ext_info ad4170_filter_type_ext_info[] = {
+ IIO_ENUM("filter_type", IIO_SEPARATE, &ad4170_filter_type_enum),
+ IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_TYPE,
+ &ad4170_filter_type_enum),
+ { }
+};
+
+static const struct iio_chan_spec ad4170_channel_template = {
+ .type = IIO_VOLTAGE,
+ .indexed = 1,
+ .differential = 1,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
+ BIT(IIO_CHAN_INFO_SCALE) |
+ BIT(IIO_CHAN_INFO_OFFSET) |
+ BIT(IIO_CHAN_INFO_CALIBSCALE) |
+ BIT(IIO_CHAN_INFO_CALIBBIAS) |
+ BIT(IIO_CHAN_INFO_SAMP_FREQ),
+ .info_mask_separate_available = BIT(IIO_CHAN_INFO_SCALE) |
+ BIT(IIO_CHAN_INFO_SAMP_FREQ),
+ .ext_info = ad4170_filter_type_ext_info,
+ .scan_type = {
+ .realbits = 24,
+ .storagebits = 32,
+ .endianness = IIO_BE,
+ },
+};
+
+/*
+ * Receives the number of a multiplexed AD4170 input (ain_n), and stores the
+ * voltage (in µV) of the specified input into ain_voltage. If the input number
+ * is a ordinary analog input (AIN0 to AIN8), stores zero into ain_voltage.
+ * If a voltage regulator required by a special input is unavailable, return
+ * error code. Return 0 on success.
+ */
+static int ad4170_get_ain_voltage_uv(struct ad4170_state *st, int ain_n,
+ int *ain_voltage)
+{
+ struct device *dev = &st->spi->dev;
+
+ *ain_voltage = 0;
+ if (ain_n <= AD4170_CHAN_MAP_TEMP_SENSOR)
+ return 0;
+
+ switch (ain_n) {
+ case AD4170_CHAN_MAP_AVDD_AVSS_N:
+ *ain_voltage = (st->vrefs_uv[AD4170_AVDD_SUP]
+ - st->vrefs_uv[AD4170_AVSS_SUP]) / 5;
+ return 0;
+ case AD4170_CHAN_MAP_IOVDD_DGND_N:
+ *ain_voltage = st->vrefs_uv[AD4170_IOVDD_SUP] / 5;
+ return 0;
+ case AD4170_CHAN_MAP_AVSS:
+ *ain_voltage = st->vrefs_uv[AD4170_AVSS_SUP];
+ return 0;
+ case AD4170_CHAN_MAP_DGND:
+ *ain_voltage = 0;
+ return 0;
+ case AD4170_CHAN_MAP_REFIN1_P:
+ if (st->vrefs_uv[AD4170_REFIN1P_SUP] == -ENODEV)
+ return dev_err_probe(dev, -ENODEV,
+ "input set to REFIN+ but ref not provided\n");
+
+ *ain_voltage = st->vrefs_uv[AD4170_REFIN1P_SUP];
+ return 0;
+ case AD4170_CHAN_MAP_REFIN1_N:
+ if (st->vrefs_uv[AD4170_REFIN1N_SUP] == -ENODEV)
+ return dev_err_probe(dev, -ENODEV,
+ "input set to REFIN- but ref not provided\n");
+
+ *ain_voltage = st->vrefs_uv[AD4170_REFIN1N_SUP];
+ return 0;
+ case AD4170_CHAN_MAP_REFIN2_P:
+ if (st->vrefs_uv[AD4170_REFIN2P_SUP] == -ENODEV)
+ return dev_err_probe(dev, -ENODEV,
+ "input set to REFIN2+ but ref not provided\n");
+
+ *ain_voltage = st->vrefs_uv[AD4170_REFIN2P_SUP];
+ return 0;
+ case AD4170_CHAN_MAP_REFIN2_N:
+ if (st->vrefs_uv[AD4170_REFIN2N_SUP] == -ENODEV)
+ return dev_err_probe(dev, -ENODEV,
+ "input set to REFIN2- but ref not provided\n");
+
+ *ain_voltage = st->vrefs_uv[AD4170_REFIN2N_SUP];
+ return 0;
+ case AD4170_CHAN_MAP_REFOUT:
+ /* REFOUT is 2.5V relative to AVSS so take that into account */
+ *ain_voltage = st->vrefs_uv[AD4170_AVSS_SUP] + (2500 * MILLI);
+ return 0;
+ }
+ return -EINVAL;
+}
+
+static int ad4170_validate_analog_input(struct ad4170_state *st, int pin)
+{
+ if (pin <= AD4170_MAX_ANALOG_PINS) {
+ if (st->pins_fn[pin] & AD4170_PIN_CURRENT_OUT)
+ return dev_err_probe(&st->spi->dev, -EINVAL,
+ "Pin %d already used with fn %u.\n",
+ pin, st->pins_fn[pin]);
+
+ st->pins_fn[pin] |= AD4170_PIN_ANALOG_IN;
+ }
+ return 0;
+}
+
+static int ad4170_validate_channel_input(struct ad4170_state *st, int pin, bool com)
+{
+ /* Check common-mode input pin is mapped to a special input. */
+ if (com && (pin < AD4170_CHAN_MAP_AVDD_AVSS_P || pin > AD4170_CHAN_MAP_REFOUT))
+ return dev_err_probe(&st->spi->dev, -EINVAL,
+ "Invalid common-mode input pin number. %d\n",
+ pin);
+
+ /* Check differential input pin is mapped to a analog input pin. */
+ if (!com && pin > AD4170_MAX_ANALOG_PINS)
+ return dev_err_probe(&st->spi->dev, -EINVAL,
+ "Invalid analog input pin number. %d\n",
+ pin);
+
+ return ad4170_validate_analog_input(st, pin);
+}
+
+/*
+ * Verifies whether the channel input configuration is valid by checking the
+ * input numbers.
+ * Returns 0 on valid channel input configuration. -EINVAL otherwise.
+ */
+static int ad4170_validate_channel(struct ad4170_state *st,
+ struct iio_chan_spec const *chan)
+{
+ int ret;
+
+ ret = ad4170_validate_channel_input(st, chan->channel, false);
+ if (ret < 0)
+ return ret;
+
+ return ad4170_validate_channel_input(st, chan->channel2,
+ !chan->differential);
+}
+
+/*
+ * Verifies whether the channel configuration is valid by checking the provided
+ * input type, polarity, and voltage references result in a sane input range.
+ * Returns negative error code on failure.
+ */
+static int ad4170_get_input_range(struct ad4170_state *st,
+ struct iio_chan_spec const *chan,
+ unsigned int ch_reg, unsigned int ref_sel)
+{
+ bool bipolar = chan->scan_type.sign == 's';
+ struct device *dev = &st->spi->dev;
+ int refp, refn, ain_voltage, ret;
+
+ switch (ref_sel) {
+ case AD4170_REF_REFIN1:
+ if (st->vrefs_uv[AD4170_REFIN1P_SUP] == -ENODEV ||
+ st->vrefs_uv[AD4170_REFIN1N_SUP] == -ENODEV)
+ return dev_err_probe(dev, -ENODEV,
+ "REFIN+, REFIN− selected but not provided\n");
+
+ refp = st->vrefs_uv[AD4170_REFIN1P_SUP];
+ refn = st->vrefs_uv[AD4170_REFIN1N_SUP];
+ break;
+ case AD4170_REF_REFIN2:
+ if (st->vrefs_uv[AD4170_REFIN2P_SUP] == -ENODEV ||
+ st->vrefs_uv[AD4170_REFIN2N_SUP] == -ENODEV)
+ return dev_err_probe(dev, -ENODEV,
+ "REFIN2+, REFIN2− selected but not provided\n");
+
+ refp = st->vrefs_uv[AD4170_REFIN2P_SUP];
+ refn = st->vrefs_uv[AD4170_REFIN2N_SUP];
+ break;
+ case AD4170_REF_AVDD:
+ refp = st->vrefs_uv[AD4170_AVDD_SUP];
+ refn = st->vrefs_uv[AD4170_AVSS_SUP];
+ break;
+ case AD4170_REF_REFOUT:
+ /* REFOUT is 2.5 V relative to AVSS */
+ refp = st->vrefs_uv[AD4170_AVSS_SUP] + (2500 * MILLI);
+ refn = st->vrefs_uv[AD4170_AVSS_SUP];
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /*
+ * Find out the analog input range from the channel type, polarity, and
+ * voltage reference selection.
+ * AD4170 channels are either differential or pseudo-differential.
+ * Diff input voltage range: −VREF/gain to +VREF/gain (datasheet page 6)
+ * Pseudo-diff input voltage range: 0 to VREF/gain (datasheet page 6)
+ */
+ if (chan->differential) {
+ if (!bipolar)
+ return dev_err_probe(&st->spi->dev, -EINVAL,
+ "Channel %u differential unipolar\n",
+ ch_reg);
+
+ /*
+ * Differential bipolar channel.
+ * avss-supply is never above 0V.
+ * Assuming refin1n-supply not above 0V.
+ * Assuming refin2n-supply not above 0V.
+ */
+ return refp + abs(refn);
+ }
+ /*
+ * Some configurations can lead to invalid setups.
+ * For example, if AVSS = -2.5V, REF_SELECT set to REFOUT (REFOUT/AVSS),
+ * and pseudo-diff channel configuration set, then the input range
+ * should go from 0V to +VREF (single-ended - datasheet pg 10), but
+ * REFOUT/AVSS range would be -2.5V to 0V.
+ * Check the positive reference is higher than 0V for pseudo-diff
+ * channels.
+ */
+ if (refp <= 0)
+ return dev_err_probe(&st->spi->dev, -EINVAL,
+ "REF+ <= GND for pseudo-diff chan %u\n",
+ ch_reg);
+
+ if (bipolar)
+ return refp;
+
+ /*
+ * Pseudo-differential unipolar channel.
+ * Input expected to swing from IN- to +VREF.
+ */
+ ret = ad4170_get_ain_voltage_uv(st, chan->channel2, &ain_voltage);
+ if (ret < 0)
+ return ret;
+
+ if (refp - ain_voltage <= 0)
+ return dev_err_probe(&st->spi->dev, -EINVAL,
+ "Negative input >= REF+ for pseudo-diff chan %u\n",
+ ch_reg);
+
+ return refp - ain_voltage;
+}
+
+static int __ad4170_read_sample(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan, int *val)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ int settling_time_ms, ret;
+
+ ret = ad4170_set_mode(st, AD4170_ADC_CTRL_MODE_SINGLE);
+ if (ret)
+ return ret;
+
+ /*
+ * When a channel is manually selected by the user, the ADC needs an
+ * extra time to provide the first stable conversion. The ADC settling
+ * time depends on the filter type, filter frequency, and ADC clock
+ * frequency (see datasheet page 53). The maximum settling time among
+ * all filter configurations is 6291164 / fCLK. Use that formula to wait
+ * for sufficient time whatever the filter configuration may be.
+ */
+ settling_time_ms = DIV_ROUND_UP(6291164 * MILLI, st->mclk_hz);
+ reinit_completion(&st->completion);
+ ret = wait_for_completion_timeout(&st->completion,
+ msecs_to_jiffies(settling_time_ms));
+ if (!ret)
+ dev_dbg(&st->spi->dev,
+ "No Data Ready signal. Reading after delay.\n");
+
+ ret = regmap_read(st->regmap, AD4170_DATA_24B_REG, val);
+ if (ret)
+ return ret;
+
+ if (chan->scan_type.sign == 's')
+ *val = sign_extend32(*val, chan->scan_type.realbits - 1);
+
+ return 0;
+}
+
+static int ad4170_read_sample(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan, int *val)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ int ret;
+
+ guard(mutex)(&st->lock);
+ /*
+ * The ADC sequences through all enabled channels. That can lead to
+ * incorrect channel being sampled if a previous read would have left a
+ * different channel enabled. Thus, always enable and disable the
+ * channel on single-shot read.
+ */
+ ret = ad4170_set_channel_enable(st, chan->address, true);
+ if (ret)
+ return ret;
+
+ ret = __ad4170_read_sample(indio_dev, chan, val);
+ if (ret)
+ dev_err(&st->spi->dev, "failed to read sample: %d\n", ret);
+
+ ret = ad4170_set_channel_enable(st, chan->address, false);
+ if (ret)
+ return ret;
+
+ return IIO_VAL_INT;
+}
+
+static int ad4170_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val, int *val2, long info)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
+ struct ad4170_setup *setup = &chan_info->setup;
+ enum ad4170_filter_type f_type;
+ unsigned int pga, fs_idx;
+ int ret;
+
+ switch (info) {
+ case IIO_CHAN_INFO_RAW:
+ if (!iio_device_claim_direct(indio_dev))
+ return -EBUSY;
+
+ ret = ad4170_read_sample(indio_dev, chan, val);
+ iio_device_release_direct(indio_dev);
+ return ret;
+ case IIO_CHAN_INFO_SCALE:
+ pga = FIELD_GET(AD4170_AFE_PGA_GAIN_MSK, setup->afe);
+ *val = chan_info->scale_tbl[pga][0];
+ *val2 = chan_info->scale_tbl[pga][1];
+ return IIO_VAL_INT_PLUS_NANO;
+ case IIO_CHAN_INFO_OFFSET:
+ pga = FIELD_GET(AD4170_AFE_PGA_GAIN_MSK, setup->afe);
+ *val = chan_info->offset_tbl[pga];
+ return IIO_VAL_INT;
+ case IIO_CHAN_INFO_SAMP_FREQ:
+ f_type = __ad4170_get_filter_type(setup->filter);
+ switch (f_type) {
+ case AD4170_SINC5_AVG:
+ case AD4170_SINC3:
+ fs_idx = find_closest(setup->filter_fs,
+ ad4170_sinc3_filt_fs_tbl,
+ ARRAY_SIZE(ad4170_sinc3_filt_fs_tbl));
+ *val = st->sps_tbl[f_type][fs_idx][0];
+ *val2 = st->sps_tbl[f_type][fs_idx][1];
+ break;
+ case AD4170_SINC5:
+ fs_idx = find_closest(setup->filter_fs,
+ ad4170_sinc5_filt_fs_tbl,
+ ARRAY_SIZE(ad4170_sinc5_filt_fs_tbl));
+ *val = st->sps_tbl[f_type][fs_idx][0];
+ *val2 = st->sps_tbl[f_type][fs_idx][1];
+ break;
+ default:
+ return -EINVAL;
+ }
+ return IIO_VAL_INT_PLUS_MICRO;
+ case IIO_CHAN_INFO_CALIBBIAS:
+ *val = setup->offset;
+ return IIO_VAL_INT;
+ case IIO_CHAN_INFO_CALIBSCALE:
+ *val = setup->gain;
+ return IIO_VAL_INT;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int ad4170_fill_scale_tbl(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
+ int bipolar = chan->scan_type.sign == 's' ? 1 : 0;
+ int precision_bits = chan->scan_type.realbits;
+ int pga, ainm_voltage, ret;
+ unsigned long long offset;
+
+ ainm_voltage = 0;
+ ret = ad4170_get_ain_voltage_uv(st, chan->channel2, &ainm_voltage);
+ if (ret < 0)
+ return dev_err_probe(&st->spi->dev, ret,
+ "Failed to fill scale table\n");
+
+ for (pga = 0; pga < AD4170_NUM_PGA_OPTIONS; pga++) {
+ u64 nv;
+ unsigned int lshift, rshift;
+
+ /*
+ * The scale factor to get ADC output codes to values in mV
+ * units is given by:
+ * _scale = (input_range / gain) / 2^precision
+ * AD4170 gain is a power of 2 so the above can be written as
+ * _scale = input_range / 2^(precision + gain)
+ * Keep the input range in µV to avoid truncating the less
+ * significan bits when right shifting it so to preserve scale
+ * precision.
+ */
+ nv = (u64)chan_info->input_range_uv * NANO;
+ lshift = (pga >> 3 & 1); /* handle cases 8 and 9 */
+ rshift = precision_bits - bipolar + (pga & 0x7) - lshift;
+ chan_info->scale_tbl[pga][0] = 0;
+ chan_info->scale_tbl[pga][1] = div_u64(nv >> rshift, MILLI);
+
+ /*
+ * If the negative input is not at GND, the conversion result
+ * (which is relative to IN-) will be offset by the level at IN-.
+ * Use the scale factor the other way around to go from a known
+ * voltage to the corresponding ADC output code.
+ * With that, we are able to get to what would be the output
+ * code for the voltage at the negative input.
+ * If the negative input is not fixed, there is no offset.
+ */
+ offset = ((unsigned long long)abs(ainm_voltage)) * MICRO;
+ offset = DIV_ROUND_CLOSEST_ULL(offset, chan_info->scale_tbl[pga][1]);
+
+ /*
+ * After divided by the scale, offset will always fit into 31
+ * bits. For _raw + _offset to be relative to GND, the value
+ * provided as _offset is of opposite sign than the real offset.
+ */
+ if (ainm_voltage > 0)
+ chan_info->offset_tbl[pga] = -(int)(offset);
+ else
+ chan_info->offset_tbl[pga] = (int)(offset);
+ }
+ return 0;
+}
+
+static int ad4170_read_avail(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ const int **vals, int *type, int *length,
+ long info)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
+ enum ad4170_filter_type f_type;
+
+ switch (info) {
+ case IIO_CHAN_INFO_SCALE:
+ *vals = (int *)chan_info->scale_tbl;
+ *length = ARRAY_SIZE(chan_info->scale_tbl) * 2;
+ *type = IIO_VAL_INT_PLUS_NANO;
+ return IIO_AVAIL_LIST;
+ case IIO_CHAN_INFO_SAMP_FREQ:
+ f_type = ad4170_get_filter_type(indio_dev, chan);
+ switch (f_type) {
+ case AD4170_SINC5_AVG:
+ fallthrough;
+ case AD4170_SINC3:
+ *vals = (int *)st->sps_tbl[f_type];
+ *length = ARRAY_SIZE(ad4170_sinc3_filt_fs_tbl) * 2;
+ break;
+ case AD4170_SINC5:
+ *vals = (int *)st->sps_tbl[f_type];
+ *length = ARRAY_SIZE(ad4170_sinc5_filt_fs_tbl) * 2;
+ break;
+ default:
+ return -EINVAL;
+ }
+ *type = IIO_VAL_INT_PLUS_MICRO;
+
+ return IIO_AVAIL_LIST;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int ad4170_set_pga(struct ad4170_state *st,
+ struct iio_chan_spec const *chan, int val, int val2)
+{
+ struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
+ struct ad4170_setup *setup = &chan_info->setup;
+ unsigned int old_pga = FIELD_GET(AD4170_AFE_PGA_GAIN_MSK, setup->afe);
+ unsigned int pga;
+ int ret;
+
+ for (pga = 0; pga < AD4170_NUM_PGA_OPTIONS; pga++) {
+ if (val == chan_info->scale_tbl[pga][0] &&
+ val2 == chan_info->scale_tbl[pga][1])
+ break;
+ }
+
+ if (pga == AD4170_NUM_PGA_OPTIONS)
+ return -EINVAL;
+
+ if (pga == old_pga)
+ return 0;
+
+ guard(mutex)(&st->lock);
+ setup->afe &= ~AD4170_AFE_PGA_GAIN_MSK;
+ setup->afe |= FIELD_PREP(AD4170_AFE_PGA_GAIN_MSK, pga);
+
+ ret = ad4170_write_channel_setup(st, chan->address, false);
+ if (ret) {
+ setup->afe &= ~AD4170_AFE_PGA_GAIN_MSK;
+ setup->afe |= FIELD_PREP(AD4170_AFE_PGA_GAIN_MSK, old_pga);
+ }
+
+ return ret;
+}
+
+static int ad4170_set_channel_freq(struct ad4170_state *st,
+ struct iio_chan_spec const *chan, int val,
+ int val2)
+{
+ struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
+ struct ad4170_setup *setup = &chan_info->setup;
+ enum ad4170_filter_type f_type = __ad4170_get_filter_type(setup->filter);
+ int filt_fs_tbl_size, ret, i;
+ unsigned int old_filter_fs;
+
+ switch (f_type) {
+ case AD4170_SINC5_AVG:
+ fallthrough;
+ case AD4170_SINC3:
+ filt_fs_tbl_size = ARRAY_SIZE(ad4170_sinc3_filt_fs_tbl);
+ break;
+ case AD4170_SINC5:
+ filt_fs_tbl_size = ARRAY_SIZE(ad4170_sinc5_filt_fs_tbl);
+ break;
+ }
+
+ for (i = 0; i < filt_fs_tbl_size; i++) {
+ if (st->sps_tbl[f_type][i][0] == val &&
+ st->sps_tbl[f_type][i][1] == val2)
+ break;
+ }
+ if (i >= filt_fs_tbl_size)
+ return -EINVAL;
+
+ guard(mutex)(&st->lock);
+ old_filter_fs = setup->filter_fs;
+ if (f_type == AD4170_SINC5)
+ setup->filter_fs = ad4170_sinc5_filt_fs_tbl[i];
+ else
+ setup->filter_fs = ad4170_sinc3_filt_fs_tbl[i];
+
+ ret = ad4170_write_channel_setup(st, chan->address, false);
+ if (ret)
+ setup->filter_fs = old_filter_fs;
+
+ return ret;
+}
+
+static int ad4170_set_calib_offset(struct ad4170_state *st,
+ struct iio_chan_spec const *chan, int val)
+{
+ struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
+ struct ad4170_setup *setup = &chan_info->setup;
+ u32 old_offset;
+ int ret;
+
+ guard(mutex)(&st->lock);
+ old_offset = setup->offset;
+ setup->offset = val;
+
+ ret = ad4170_write_channel_setup(st, chan->address, false);
+ if (ret)
+ setup->offset = old_offset;
+
+ return ret;
+}
+
+static int ad4170_set_calib_gain(struct ad4170_state *st,
+ struct iio_chan_spec const *chan, int val)
+{
+ struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
+ struct ad4170_setup *setup = &chan_info->setup;
+ u32 old_gain;
+ int ret;
+
+ guard(mutex)(&st->lock);
+ old_gain = setup->gain;
+ setup->gain = val;
+
+ ret = ad4170_write_channel_setup(st, chan->address, false);
+ if (ret)
+ setup->gain = old_gain;
+
+ return ret;
+}
+
+static int __ad4170_write_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan, int val,
+ int val2, long info)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+
+ switch (info) {
+ case IIO_CHAN_INFO_SCALE:
+ return ad4170_set_pga(st, chan, val, val2);
+ case IIO_CHAN_INFO_SAMP_FREQ:
+ return ad4170_set_channel_freq(st, chan, val, val2);
+ case IIO_CHAN_INFO_CALIBBIAS:
+ return ad4170_set_calib_offset(st, chan, val);
+ case IIO_CHAN_INFO_CALIBSCALE:
+ return ad4170_set_calib_gain(st, chan, val);
+ default:
+ return -EINVAL;
+ }
+}
+
+static int ad4170_write_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan, int val,
+ int val2, long info)
+{
+ int ret;
+
+ if (!iio_device_claim_direct(indio_dev))
+ return -EBUSY;
+
+ ret = __ad4170_write_raw(indio_dev, chan, val, val2, info);
+ iio_device_release_direct(indio_dev);
+ return ret;
+}
+
+static int ad4170_write_raw_get_fmt(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ long info)
+{
+ switch (info) {
+ case IIO_CHAN_INFO_SCALE:
+ return IIO_VAL_INT_PLUS_NANO;
+ case IIO_CHAN_INFO_SAMP_FREQ:
+ return IIO_VAL_INT_PLUS_MICRO;
+ case IIO_CHAN_INFO_CALIBBIAS:
+ case IIO_CHAN_INFO_CALIBSCALE:
+ return IIO_VAL_INT;
+ default:
+ return -EINVAL;
+ }
+}
+
+static const struct iio_info ad4170_info = {
+ .read_raw = ad4170_read_raw,
+ .read_avail = ad4170_read_avail,
+ .write_raw = ad4170_write_raw,
+ .write_raw_get_fmt = ad4170_write_raw_get_fmt,
+ .debugfs_reg_access = ad4170_debugfs_reg_access,
+};
+
+static int ad4170_soft_reset(struct ad4170_state *st)
+{
+ int ret;
+
+ ret = regmap_write(st->regmap, AD4170_CONFIG_A_REG,
+ AD4170_SW_RESET_MSK);
+ if (ret)
+ return ret;
+
+ /* AD4170-4 requires 1 ms between reset and any register access. */
+ fsleep(MILLI);
+
+ return 0;
+}
+
+static int ad4170_parse_reference(struct ad4170_state *st,
+ struct fwnode_handle *child,
+ struct ad4170_setup *setup)
+{
+ struct device *dev = &st->spi->dev;
+ int ret;
+ u8 aux;
+
+ /* Optional positive reference buffering, if omitted we use the default */
+ aux = AD4170_REF_BUF_FULL; /* Default to full precharge buffer enabled. */
+ ret = fwnode_property_read_u8(child, "adi,buffered-positive", &aux);
+ if (!ret) {
+ if (aux < AD4170_REF_BUF_PRE || aux > AD4170_REF_BUF_BYPASS)
+ return dev_err_probe(dev, -EINVAL,
+ "Invalid adi,buffered-positive: %u\n",
+ aux);
+ }
+ setup->afe |= FIELD_PREP(AD4170_AFE_REF_BUF_P_MSK, aux);
+
+ /* Optional negative reference buffering, if omitted we use the default */
+ aux = AD4170_REF_BUF_FULL; /* Default to full precharge buffer enabled. */
+ ret = fwnode_property_read_u8(child, "adi,buffered-negative", &aux);
+ if (!ret) {
+ if (aux < AD4170_REF_BUF_PRE || aux > AD4170_REF_BUF_BYPASS)
+ return dev_err_probe(dev, -EINVAL,
+ "Invalid adi,buffered-negative: %u\n",
+ aux);
+ }
+ setup->afe |= FIELD_PREP(AD4170_AFE_REF_BUF_M_MSK, aux);
+
+ /* Optional voltage reference selection, if omitted we use the default */
+ aux = AD4170_REF_REFOUT; /* Default reference selection. */
+ ret = fwnode_property_read_u8(child, "adi,reference-select", &aux);
+ if (!ret) {
+ if (aux > AD4170_REF_AVDD)
+ return dev_err_probe(dev, -EINVAL,
+ "Invalid reference selected %u\n",
+ aux);
+ }
+ setup->afe |= FIELD_PREP(AD4170_AFE_REF_SELECT_MSK, aux);
+
+ return 0;
+}
+
+static int ad4170_parse_adc_channel_type(struct device *dev,
+ struct fwnode_handle *child,
+ struct iio_chan_spec *chan)
+{
+ u32 pins[2];
+ int ret, ret2;
+
+ ret = fwnode_property_read_u32(child, "single-channel", &pins[0]);
+ ret2 = fwnode_property_read_u32(child, "common-mode-channel", &pins[1]);
+ if (!ret && ret2)
+ return dev_err_probe(dev, ret,
+ "single-ended channels must define common-mode-channel\n");
+ if (!ret) {
+ chan->differential = false;
+ chan->channel = pins[0];
+ chan->channel2 = pins[1];
+ return 0;
+ }
+ ret = fwnode_property_read_u32_array(child, "diff-channels", pins,
+ ARRAY_SIZE(pins));
+ if (!ret) {
+ chan->differential = true;
+ chan->channel = pins[0];
+ chan->channel2 = pins[1];
+ return 0;
+ }
+ return dev_err_probe(dev, ret,
+ "Channel must define one of diff-channels or single-channel.\n");
+}
+
+static int ad4170_parse_channel_node(struct iio_dev *indio_dev,
+ struct fwnode_handle *child,
+ unsigned int chan_num)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ struct device *dev = &st->spi->dev;
+ struct ad4170_chan_info *chan_info;
+ struct ad4170_setup *setup;
+ struct iio_chan_spec *chan;
+ unsigned int ch_reg;
+ u8 ref_select;
+ bool bipolar;
+ int ret;
+
+ ret = fwnode_property_read_u32(child, "reg", &ch_reg);
+ if (ret)
+ return dev_err_probe(dev, -EINVAL,
+ "Failed to read channel reg\n");
+
+ if (ch_reg >= AD4170_MAX_CHANNELS)
+ return dev_err_probe(dev, -EINVAL,
+ "Channel idx greater than no of channels\n");
+
+ chan = &st->chans[chan_num];
+ *chan = ad4170_channel_template;
+
+ chan->address = ch_reg;
+ chan->scan_index = ch_reg;
+ chan_info = &st->chan_infos[chan->address];
+
+ chan_info->setup_num = AD4170_INVALID_SETUP;
+ chan_info->initialized = true;
+
+ setup = &chan_info->setup;
+ ret = ad4170_parse_reference(st, child, setup);
+ if (ret)
+ return ret;
+
+ ret = ad4170_parse_adc_channel_type(dev, child, chan);
+ if (ret < 0)
+ return ret;
+
+ bipolar = fwnode_property_read_bool(child, "bipolar");
+ setup->afe |= FIELD_PREP(AD4170_AFE_BIPOLAR_MSK, bipolar);
+ if (bipolar)
+ chan->scan_type.sign = 's';
+ else
+ chan->scan_type.sign = 'u';
+
+ ref_select = FIELD_GET(AD4170_AFE_REF_SELECT_MSK, setup->afe);
+ ret = ad4170_validate_channel(st, chan);
+ if (ret < 0)
+ return ret;
+
+ ret = ad4170_get_input_range(st, chan, ch_reg, ref_select);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Invalid input config\n");
+
+ chan_info->input_range_uv = ret;
+ return 0;
+}
+
+static int ad4170_parse_channels(struct iio_dev *indio_dev)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ struct device *dev = &st->spi->dev;
+ unsigned int num_channels;
+ unsigned int chan_num;
+ int ret;
+
+ num_channels = device_get_child_node_count(dev);
+
+ if (num_channels > AD4170_MAX_CHANNELS)
+ return dev_err_probe(dev, -EINVAL, "Too many channels\n");
+
+ device_for_each_child_node_scoped(dev, child) {
+ ret = ad4170_parse_channel_node(indio_dev, child, chan_num++);
+ if (ret)
+ return ret;
+ }
+
+ indio_dev->num_channels = num_channels;
+ indio_dev->channels = st->chans;
+ return 0;
+}
+
+static int ad4170_parse_firmware(struct iio_dev *indio_dev)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ struct device *dev = &st->spi->dev;
+ int reg_data, ret, i;
+
+ st->mclk_hz = AD4170_INT_CLOCK_16MHZ;
+
+ for (i = 0; i < AD4170_NUM_ANALOG_PINS; i++)
+ st->pins_fn[i] = AD4170_PIN_UNASIGNED;
+
+ /* On power on, device defaults to using SDO pin for data ready signal */
+ st->int_pin_sel = AD4170_INT_PIN_SDO;
+ ret = device_property_match_property_string(dev, "interrupt-names",
+ ad4170_int_pin_names,
+ ARRAY_SIZE(ad4170_int_pin_names));
+ if (ret >= 0)
+ st->int_pin_sel = ret;
+
+ reg_data = FIELD_PREP(AD4170_PIN_MUXING_DIG_AUX1_CTRL_MSK,
+ st->int_pin_sel == AD4170_INT_PIN_DIG_AUX1 ?
+ AD4170_PIN_MUXING_DIG_AUX1_RDY :
+ AD4170_PIN_MUXING_DIG_AUX1_DISABLED);
+
+ ret = regmap_update_bits(st->regmap, AD4170_PIN_MUXING_REG,
+ AD4170_PIN_MUXING_DIG_AUX1_CTRL_MSK, reg_data);
+ if (ret)
+ return ret;
+
+ return ad4170_parse_channels(indio_dev);
+}
+
+static int ad4170_initial_config(struct iio_dev *indio_dev)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ struct device *dev = &st->spi->dev;
+ int i, ret;
+
+ ad4170_fill_sps_tbl(st);
+
+ ret = ad4170_set_mode(st, AD4170_ADC_CTRL_MODE_IDLE);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to set ADC mode to idle\n");
+
+ for (i = 0; i < indio_dev->num_channels; i++) {
+ struct ad4170_chan_info *chan_info;
+ struct iio_chan_spec const *chan;
+ struct ad4170_setup *setup;
+ unsigned int val;
+
+ chan = &indio_dev->channels[i];
+ chan_info = &st->chan_infos[chan->address];
+
+ setup = &chan_info->setup;
+ setup->gain = AD4170_GAIN_REG_DEFAULT;
+ ret = ad4170_write_channel_setup(st, chan->address, false);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to write channel setup\n");
+
+ val = FIELD_PREP(AD4170_CHAN_MAP_AINP_MSK, chan->channel) |
+ FIELD_PREP(AD4170_CHAN_MAP_AINM_MSK, chan->channel2);
+
+ ret = regmap_write(st->regmap, AD4170_CHAN_MAP_REG(i), val);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to write CHAN_MAP_REG\n");
+
+ ret = ad4170_set_channel_freq(st, chan,
+ AD4170_DEFAULT_SAMP_RATE, 0);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to set channel freq\n");
+
+ ret = ad4170_fill_scale_tbl(indio_dev, chan);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to fill scale tbl\n");
+ }
+
+ /* Disable all channels to avoid reading from unexpected channel */
+ ret = regmap_write(st->regmap, AD4170_CHAN_EN_REG, 0);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to disable channels\n");
+
+ /*
+ * Configure channels to share the same data output register, i.e. data
+ * can be read from the same register address regardless of channel
+ * number.
+ */
+ return regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG,
+ AD4170_ADC_CTRL_MULTI_DATA_REG_SEL_MSK,
+ AD4170_ADC_CTRL_MULTI_DATA_REG_SEL_MSK);
+}
+
+static irqreturn_t ad4170_irq_handler(int irq, void *dev_id)
+{
+ struct iio_dev *indio_dev = dev_id;
+ struct ad4170_state *st = iio_priv(indio_dev);
+
+ complete(&st->completion);
+
+ return IRQ_HANDLED;
+};
+
+static int ad4170_regulator_setup(struct ad4170_state *st)
+{
+ struct device *dev = &st->spi->dev;
+ int ret;
+
+ /* Required regulators */
+ ret = devm_regulator_get_enable_read_voltage(dev, "avdd");
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to get AVDD voltage.\n");
+
+ st->vrefs_uv[AD4170_AVDD_SUP] = ret;
+
+ ret = devm_regulator_get_enable_read_voltage(dev, "iovdd");
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to get IOVDD voltage.\n");
+
+ st->vrefs_uv[AD4170_IOVDD_SUP] = ret;
+
+ /* Optional regulators */
+ ret = devm_regulator_get_enable_read_voltage(dev, "avss");
+ if (ret < 0 && ret != -ENODEV)
+ return dev_err_probe(dev, ret, "Failed to get AVSS voltage.\n");
+
+ /* Assume AVSS at GND (0V) if not provided */
+ st->vrefs_uv[AD4170_AVSS_SUP] = ret == -ENODEV ? 0 : -ret;
+
+ ret = devm_regulator_get_enable_read_voltage(dev, "refin1p");
+ if (ret < 0 && ret != -ENODEV)
+ return dev_err_probe(dev, ret, "Failed to get REFIN+ voltage.\n");
+
+ st->vrefs_uv[AD4170_REFIN1P_SUP] = ret;
+
+ ret = devm_regulator_get_enable_read_voltage(dev, "refin1n");
+ if (ret < 0 && ret != -ENODEV)
+ return dev_err_probe(dev, ret, "Failed to get REFIN- voltage.\n");
+
+ /* Negative supplies are assumed to provide negative voltage */
+ st->vrefs_uv[AD4170_REFIN1N_SUP] = ret == -ENODEV ? -ENODEV : -ret;
+
+ ret = devm_regulator_get_enable_read_voltage(dev, "refin2p");
+ if (ret < 0 && ret != -ENODEV)
+ return dev_err_probe(dev, ret, "Failed to get REFIN2+ voltage.\n");
+
+ st->vrefs_uv[AD4170_REFIN2P_SUP] = ret;
+
+ ret = devm_regulator_get_enable_read_voltage(dev, "refin2n");
+ if (ret < 0 && ret != -ENODEV)
+ return dev_err_probe(dev, ret, "Failed to get REFIN2- voltage.\n");
+
+ /* Negative supplies are assumed to provide negative voltage */
+ st->vrefs_uv[AD4170_REFIN2N_SUP] = ret == -ENODEV ? -ENODEV : -ret;
+
+ return 0;
+}
+
+static int ad4170_probe(struct spi_device *spi)
+{
+ const struct ad4170_chip_info *chip;
+ struct device *dev = &spi->dev;
+ struct iio_dev *indio_dev;
+ struct ad4170_state *st;
+ int ret;
+
+ indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
+ if (!indio_dev)
+ return -ENOMEM;
+
+ st = iio_priv(indio_dev);
+ ret = devm_mutex_init(dev, &st->lock);
+ if (ret)
+ return ret;
+
+ chip = spi_get_device_match_data(spi);
+ if (!chip)
+ return -EINVAL;
+
+ indio_dev->name = chip->name;
+ indio_dev->info = &ad4170_info;
+
+ st->spi = spi;
+
+ st->regmap = devm_regmap_init(dev, NULL, st, &ad4170_regmap_config);
+ if (IS_ERR(st->regmap))
+ return dev_err_probe(dev, PTR_ERR(st->regmap),
+ "Failed to initialize regmap\n");
+
+ ret = ad4170_regulator_setup(st);
+ if (ret)
+ return ret;
+
+ ret = ad4170_soft_reset(st);
+ if (ret)
+ return ret;
+
+ ret = ad4170_parse_firmware(indio_dev);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to parse firmware\n");
+
+ ret = ad4170_initial_config(indio_dev);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to setup device\n");
+
+ init_completion(&st->completion);
+
+ if (spi->irq) {
+ ret = devm_request_irq(&st->spi->dev, st->spi->irq,
+ &ad4170_irq_handler, IRQF_ONESHOT,
+ indio_dev->name, indio_dev);
+ if (ret)
+ return ret;
+ }
+
+ return devm_iio_device_register(dev, indio_dev);
+}
+
+static const struct spi_device_id ad4170_id_table[] = {
+ { "ad4170", (kernel_ulong_t)&ad4170_chip_info },
+ { "ad4190", (kernel_ulong_t)&ad4190_chip_info },
+ { "ad4195", (kernel_ulong_t)&ad4195_chip_info },
+ { }
+};
+MODULE_DEVICE_TABLE(spi, ad4170_id_table);
+
+static const struct of_device_id ad4170_of_match[] = {
+ { .compatible = "adi,ad4170", .data = &ad4170_chip_info },
+ { .compatible = "adi,ad4190", .data = &ad4190_chip_info },
+ { .compatible = "adi,ad4195", .data = &ad4195_chip_info },
+ { }
+};
+MODULE_DEVICE_TABLE(of, ad4170_of_match);
+
+static struct spi_driver ad4170_driver = {
+ .driver = {
+ .name = "ad4170",
+ .of_match_table = ad4170_of_match,
+ },
+ .probe = ad4170_probe,
+ .id_table = ad4170_id_table,
+};
+module_spi_driver(ad4170_driver);
+
+MODULE_AUTHOR("Ana-Maria Cusco <ana-maria.cusco@analog.com>");
+MODULE_AUTHOR("Marcelo Schmitt <marcelo.schmitt@analog.com>");
+MODULE_DESCRIPTION("Analog Devices AD4170 SPI driver");
+MODULE_LICENSE("GPL");
--
2.47.2
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v2 2/7] iio: adc: Add basic support for AD4170
2025-04-28 12:28 ` [PATCH v2 2/7] iio: adc: Add basic support for AD4170 Marcelo Schmitt
@ 2025-05-02 11:28 ` Andy Shevchenko
2025-05-12 13:23 ` Marcelo Schmitt
2025-05-04 18:21 ` Jonathan Cameron
1 sibling, 1 reply; 27+ messages in thread
From: Andy Shevchenko @ 2025-05-02 11:28 UTC (permalink / raw)
To: Marcelo Schmitt
Cc: linux-iio, devicetree, linux-kernel, Ana-Maria Cusco, jic23, lars,
Michael.Hennerich, dlechner, nuno.sa, robh, krzk+dt, conor+dt,
marcelo.schmitt1
On Mon, Apr 28, 2025 at 09:28:03AM -0300, Marcelo Schmitt wrote:
> From: Ana-Maria Cusco <ana-maria.cusco@analog.com>
>
> Add support for the AD4170 ADC with the following features:
> - Single-shot read.
> - Analog front end PGA configuration.
> - Digital filter and sampling frequency configuration.
> - Calibration gain and offset configuration.
> - Differential and pseudo-differential input configuration.
...
> +/*
> + * Copyright (C) 2024 Analog Devices, Inc.
My calendar shows 2025...
> + * Author: Ana-Maria Cusco <ana-maria.cusco@analog.com>
> + * Author: Marcelo Schmitt <marcelo.schmitt@analog.com>
> + */
...
> +#define AD4170_DEFAULT_SAMP_RATE (125 * KILO)
HZ_PER_KHZ ?
...
> +/* Internal and external clock properties */
> +#define AD4170_INT_CLOCK_16MHZ (16 * MEGA)
HZ_PER_MHZ
> +#define AD4170_EXT_CLOCK_MHZ_MIN (1 * MEGA)
> +#define AD4170_EXT_CLOCK_MHZ_MAX (17 * MEGA)
Ditto. But are you sure that it's 17 and not 16?
...
> +static const unsigned int ad4170_sinc3_filt_fs_tbl[] = {
> + 4, 8, 12, 16, 20, 40, 48, 80, 100, 256, 500, 1000, 5000, 8332, 10000,
> + 25000, 50000, 65532,
Please, make something like 4 or 8 per line with a comment.
4, 8, 12, 16, 20, 40, 48, 80, /* 0 - 7 */
... /* 8 - 15 */
...
> +};
...
> +struct ad4170_chan_info {
> + int setup_num; /* Index to access state setup_infos array */
> + struct ad4170_setup setup; /* cached setup */
> + int input_range_uv;
> + u32 scale_tbl[10][2];
> + int offset_tbl[10];
> + bool initialized;
> + bool enabled;
`pahole` approved?
> +};
...
> +struct ad4170_state {
Ditto.
> + struct regmap *regmap;
> + struct spi_device *spi;
> + int vrefs_uv[AD4170_MAX_SUP];
> + struct mutex lock; /* Protect read-modify-write and multi write sequences */
> + struct iio_chan_spec chans[AD4170_MAX_CHANNELS];
> + struct ad4170_chan_info chan_infos[AD4170_MAX_CHANNELS];
> + struct ad4170_setup_info setup_infos[AD4170_MAX_SETUPS];
> + u32 mclk_hz;
> + int pins_fn[AD4170_NUM_ANALOG_PINS];
> + u32 int_pin_sel;
> + int sps_tbl[ARRAY_SIZE(ad4170_filt_names)][AD4170_MAX_FS_TBL_SIZE][2];
> + struct completion completion;
> + /*
> + * DMA (thus cache coherency maintenance) requires the transfer buffers
> + * to live in their own cache lines.
> + */
> + u8 tx_buf[AD4170_SPI_MAX_XFER_LEN] __aligned(IIO_DMA_MINALIGN);
> + u8 rx_buf[AD4170_SPI_MAX_XFER_LEN];
> +};
...
> +static int ad4170_debugfs_reg_access(struct iio_dev *indio_dev,
> + unsigned int reg, unsigned int writeval,
> + unsigned int *readval)
> +{
> + struct ad4170_state *st = iio_priv(indio_dev);
> + int ret = -EINVAL;
Redundant assignment.
> + if (readval)
> + ret = regmap_read(st->regmap, reg, readval);
> + else
> + ret = regmap_write(st->regmap, reg, writeval);
> +
> + return ret;
> +}
...
> +static int ad4170_find_setup(struct ad4170_state *st,
> + struct ad4170_setup *target_setup,
> + unsigned int *setup_num, bool *overwrite)
> +{
> + unsigned int i;
> +
> + *setup_num = AD4170_INVALID_SETUP;
> + *overwrite = false;
> +
> + for (i = 0; i < AD4170_MAX_SETUPS; i++) {
> + struct ad4170_setup_info *setup_info = &st->setup_infos[i];
> +
> + /* Immediately accept a matching setup. */
> + if (!memcmp(target_setup, &setup_info->setup,
> + sizeof(*target_setup))) {
Does this handle paddings okay?
> + *setup_num = i;
> + return 0;
> + }
> +
> + /* Ignore all setups which are used by enabled channels. */
> + if (setup_info->enabled_channels)
> + continue;
> +
> + /* Find the least used slot. */
> + if (*setup_num == AD4170_INVALID_SETUP ||
> + setup_info->channels < st->setup_infos[*setup_num].channels)
> + *setup_num = i;
> + }
> +
> + if (*setup_num == AD4170_INVALID_SETUP)
> + return -EINVAL;
> +
> + *overwrite = true;
> + return 0;
> +}
...
> +static int ad4170_link_channel_setup(struct ad4170_state *st,
> + unsigned int chan_addr,
> + unsigned int setup_num)
> +{
> + struct ad4170_setup_info *setup_info = &st->setup_infos[setup_num];
> + struct ad4170_chan_info *chan_info = &st->chan_infos[chan_addr];
> + int ret;
> +
> + ret = regmap_update_bits(st->regmap, AD4170_CHAN_SETUP_REG(chan_addr),
> + AD4170_CHAN_SETUP_SETUP_MSK,
> + FIELD_PREP(AD4170_CHAN_SETUP_SETUP_MSK,
> + setup_num));
I think it's fine to have these two on one line.
> + if (ret)
> + return ret;
> +
> + chan_info->setup_num = setup_num;
> + setup_info->channels++;
> + return 0;
> +}
...
> + /* Case 4 */
> + if (on_enable && chan_info->setup_num != AD4170_INVALID_SETUP)
> + return 0;
> +
> + if (!on_enable && !chan_info->enabled) {
> + if (chan_info->setup_num != AD4170_INVALID_SETUP)
> + /* Case 3 */
> + ad4170_unlink_channel(st, chan_addr);
> +
> + /* Cases 3 & 5 */
> + return 0;
> + }
I believe this can be refactored a bit.
/* Cases 3, 4, and 5 */
if (chan_info->setup_num != AD4170_INVALID_SETUP) {
/* Case 4 */
if (on_enable)
return 0;
/* Case 3 */
if (!chan_info->enabled) {
ad4170_unlink_channel(st, chan_addr);
return 0;
}
} else if (!on_enable && !chan_info->enabled) {
/* Case 5 */
return 0;
}
In my opinion it gives each case separated and hence better understanding of
the code flow. For the curiosity one may check the object file sizes (with help
of bloat-o-meter script).
...
> +static int ad4170_set_filter_type(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan,
> + unsigned int val)
> +{
> + struct ad4170_state *st = iio_priv(indio_dev);
> + struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
> + struct ad4170_setup *setup = &chan_info->setup;
> + unsigned int old_filter_fs, old_filter, filter_type_conf;
> + int ret = 0;
Redundant assignment.
...
> + switch (ain_n) {
> + case AD4170_CHAN_MAP_AVDD_AVSS_N:
> + *ain_voltage = (st->vrefs_uv[AD4170_AVDD_SUP]
> + - st->vrefs_uv[AD4170_AVSS_SUP]) / 5;
Please use better indentation and split.
... tmp;
tmp = st->vrefs_uv[AD4170_AVDD_SUP] - st->vrefs_uv[AD4170_AVSS_SUP];
*ain_voltage = tmp / 5;
> + return 0;
> + case AD4170_CHAN_MAP_IOVDD_DGND_N:
> + *ain_voltage = st->vrefs_uv[AD4170_IOVDD_SUP] / 5;
> + return 0;
> + case AD4170_CHAN_MAP_AVSS:
> + *ain_voltage = st->vrefs_uv[AD4170_AVSS_SUP];
> + return 0;
> + case AD4170_CHAN_MAP_DGND:
> + *ain_voltage = 0;
> + return 0;
> + case AD4170_CHAN_MAP_REFIN1_P:
> + if (st->vrefs_uv[AD4170_REFIN1P_SUP] == -ENODEV)
> + return dev_err_probe(dev, -ENODEV,
> + "input set to REFIN+ but ref not provided\n");
> +
> + *ain_voltage = st->vrefs_uv[AD4170_REFIN1P_SUP];
> + return 0;
> + case AD4170_CHAN_MAP_REFIN1_N:
> + if (st->vrefs_uv[AD4170_REFIN1N_SUP] == -ENODEV)
> + return dev_err_probe(dev, -ENODEV,
> + "input set to REFIN- but ref not provided\n");
> +
> + *ain_voltage = st->vrefs_uv[AD4170_REFIN1N_SUP];
> + return 0;
> + case AD4170_CHAN_MAP_REFIN2_P:
> + if (st->vrefs_uv[AD4170_REFIN2P_SUP] == -ENODEV)
> + return dev_err_probe(dev, -ENODEV,
> + "input set to REFIN2+ but ref not provided\n");
> +
> + *ain_voltage = st->vrefs_uv[AD4170_REFIN2P_SUP];
> + return 0;
> + case AD4170_CHAN_MAP_REFIN2_N:
> + if (st->vrefs_uv[AD4170_REFIN2N_SUP] == -ENODEV)
> + return dev_err_probe(dev, -ENODEV,
> + "input set to REFIN2- but ref not provided\n");
> +
> + *ain_voltage = st->vrefs_uv[AD4170_REFIN2N_SUP];
> + return 0;
> + case AD4170_CHAN_MAP_REFOUT:
> + /* REFOUT is 2.5V relative to AVSS so take that into account */
> + *ain_voltage = st->vrefs_uv[AD4170_AVSS_SUP] + (2500 * MILLI);
Using 2500000 here is probably slightly better choice as MILLI a bit ambiguous
(since the result is in MICROvolts).
> + return 0;
> + }
> + return -EINVAL;
Make this default case.
...
> +static int ad4170_validate_channel(struct ad4170_state *st,
> + struct iio_chan_spec const *chan)
> +{
> + int ret;
> +
> + ret = ad4170_validate_channel_input(st, chan->channel, false);
> + if (ret < 0)
Why ' < 0'? Same Q to all similar checks. (And here you even have it
inconsistent with the below)
> + return ret;
> +
> + return ad4170_validate_channel_input(st, chan->channel2,
> + !chan->differential);
> +}
...
> +static int ad4170_get_input_range(struct ad4170_state *st,
> + struct iio_chan_spec const *chan,
> + unsigned int ch_reg, unsigned int ref_sel)
> +{
> + bool bipolar = chan->scan_type.sign == 's';
> + struct device *dev = &st->spi->dev;
> + int refp, refn, ain_voltage, ret;
> +
> + switch (ref_sel) {
> + case AD4170_REF_REFIN1:
> + if (st->vrefs_uv[AD4170_REFIN1P_SUP] == -ENODEV ||
> + st->vrefs_uv[AD4170_REFIN1N_SUP] == -ENODEV)
> + return dev_err_probe(dev, -ENODEV,
> + "REFIN+, REFIN− selected but not provided\n");
Maybe
"REFIN± selected but not provided\n");
?
> + refp = st->vrefs_uv[AD4170_REFIN1P_SUP];
> + refn = st->vrefs_uv[AD4170_REFIN1N_SUP];
> + break;
> + case AD4170_REF_REFIN2:
> + if (st->vrefs_uv[AD4170_REFIN2P_SUP] == -ENODEV ||
> + st->vrefs_uv[AD4170_REFIN2N_SUP] == -ENODEV)
> + return dev_err_probe(dev, -ENODEV,
> + "REFIN2+, REFIN2− selected but not provided\n");
Ditto.
> + refp = st->vrefs_uv[AD4170_REFIN2P_SUP];
> + refn = st->vrefs_uv[AD4170_REFIN2N_SUP];
> + break;
> + case AD4170_REF_AVDD:
> + refp = st->vrefs_uv[AD4170_AVDD_SUP];
> + refn = st->vrefs_uv[AD4170_AVSS_SUP];
> + break;
> + case AD4170_REF_REFOUT:
> + /* REFOUT is 2.5 V relative to AVSS */
> + refp = st->vrefs_uv[AD4170_AVSS_SUP] + (2500 * MILLI);
2500000 ? Perhaps define this constant. I see it second time already.
> + refn = st->vrefs_uv[AD4170_AVSS_SUP];
> + break;
> + default:
> + return -EINVAL;
> + }
> + /*
> + * Find out the analog input range from the channel type, polarity, and
> + * voltage reference selection.
> + * AD4170 channels are either differential or pseudo-differential.
> + * Diff input voltage range: −VREF/gain to +VREF/gain (datasheet page 6)
> + * Pseudo-diff input voltage range: 0 to VREF/gain (datasheet page 6)
> + */
> + if (chan->differential) {
> + if (!bipolar)
> + return dev_err_probe(&st->spi->dev, -EINVAL,
> + "Channel %u differential unipolar\n",
> + ch_reg);
> +
> + /*
> + * Differential bipolar channel.
> + * avss-supply is never above 0V.
> + * Assuming refin1n-supply not above 0V.
> + * Assuming refin2n-supply not above 0V.
> + */
> + return refp + abs(refn);
> + }
> + /*
> + * Some configurations can lead to invalid setups.
> + * For example, if AVSS = -2.5V, REF_SELECT set to REFOUT (REFOUT/AVSS),
> + * and pseudo-diff channel configuration set, then the input range
> + * should go from 0V to +VREF (single-ended - datasheet pg 10), but
> + * REFOUT/AVSS range would be -2.5V to 0V.
> + * Check the positive reference is higher than 0V for pseudo-diff
> + * channels.
> + */
> + if (refp <= 0)
> + return dev_err_probe(&st->spi->dev, -EINVAL,
> + "REF+ <= GND for pseudo-diff chan %u\n",
> + ch_reg);
> +
> + if (bipolar)
> + return refp;
> +
> + /*
> + * Pseudo-differential unipolar channel.
> + * Input expected to swing from IN- to +VREF.
> + */
> + ret = ad4170_get_ain_voltage_uv(st, chan->channel2, &ain_voltage);
> + if (ret < 0)
> + return ret;
> +
> + if (refp - ain_voltage <= 0)
> + return dev_err_probe(&st->spi->dev, -EINVAL,
> + "Negative input >= REF+ for pseudo-diff chan %u\n",
> + ch_reg);
> +
> + return refp - ain_voltage;
> +}
...
> + settling_time_ms = DIV_ROUND_UP(6291164 * MILLI, st->mclk_hz);
Would it work on 32-bit? int*long == long.
...
> + ret = ad4170_get_ain_voltage_uv(st, chan->channel2, &ainm_voltage);
> + if (ret < 0)
Why ' < 0' ?
> + return dev_err_probe(&st->spi->dev, ret,
struct device = &st->spi->dev;
> + "Failed to fill scale table\n");
will help in this and many other cases to make them shorter.
...
> + nv = (u64)chan_info->input_range_uv * NANO;
> + lshift = (pga >> 3 & 1); /* handle cases 8 and 9 */
lshift = !!(pga & BIT(3));
?
> + rshift = precision_bits - bipolar + (pga & 0x7) - lshift;
GENMASK() ?
> + chan_info->scale_tbl[pga][0] = 0;
> + chan_info->scale_tbl[pga][1] = div_u64(nv >> rshift, MILLI);
...
> + for (i = 0; i < filt_fs_tbl_size; i++) {
> + if (st->sps_tbl[f_type][i][0] == val &&
> + st->sps_tbl[f_type][i][1] == val2)
> + break;
> + }
> + if (i >= filt_fs_tbl_size)
Why '>' ?
> + return -EINVAL;
...
> + ret = fwnode_property_read_u32_array(child, "diff-channels", pins,
> + ARRAY_SIZE(pins));
> + if (!ret) {
Use usual patter, checking for errors first.
> + chan->differential = true;
> + chan->channel = pins[0];
> + chan->channel2 = pins[1];
> + return 0;
> + }
> + return dev_err_probe(dev, ret,
> + "Channel must define one of diff-channels or single-channel.\n");
> +}
...
> +static int ad4170_parse_channels(struct iio_dev *indio_dev)
> +{
> + struct ad4170_state *st = iio_priv(indio_dev);
> + struct device *dev = &st->spi->dev;
> + unsigned int num_channels;
> + unsigned int chan_num;
> + int ret;
> +
> + num_channels = device_get_child_node_count(dev);
> +
Redundant blank line.
> + if (num_channels > AD4170_MAX_CHANNELS)
> + return dev_err_probe(dev, -EINVAL, "Too many channels\n");
> +
> + device_for_each_child_node_scoped(dev, child) {
> + ret = ad4170_parse_channel_node(indio_dev, child, chan_num++);
> + if (ret)
> + return ret;
> + }
> +
> + indio_dev->num_channels = num_channels;
> + indio_dev->channels = st->chans;
> + return 0;
> +}
...
> +static int ad4170_parse_firmware(struct iio_dev *indio_dev)
> +{
> + struct ad4170_state *st = iio_priv(indio_dev);
> + struct device *dev = &st->spi->dev;
> + int reg_data, ret, i;
Why i is signed? Ditto for many similar cases.
> + st->mclk_hz = AD4170_INT_CLOCK_16MHZ;
> +
> + for (i = 0; i < AD4170_NUM_ANALOG_PINS; i++)
> + st->pins_fn[i] = AD4170_PIN_UNASIGNED;
> +
> + /* On power on, device defaults to using SDO pin for data ready signal */
> + st->int_pin_sel = AD4170_INT_PIN_SDO;
> + ret = device_property_match_property_string(dev, "interrupt-names",
> + ad4170_int_pin_names,
> + ARRAY_SIZE(ad4170_int_pin_names));
> + if (ret >= 0)
> + st->int_pin_sel = ret;
> +
> + reg_data = FIELD_PREP(AD4170_PIN_MUXING_DIG_AUX1_CTRL_MSK,
> + st->int_pin_sel == AD4170_INT_PIN_DIG_AUX1 ?
> + AD4170_PIN_MUXING_DIG_AUX1_RDY :
> + AD4170_PIN_MUXING_DIG_AUX1_DISABLED);
> +
> + ret = regmap_update_bits(st->regmap, AD4170_PIN_MUXING_REG,
> + AD4170_PIN_MUXING_DIG_AUX1_CTRL_MSK, reg_data);
> + if (ret)
> + return ret;
> +
> + return ad4170_parse_channels(indio_dev);
> +}
...
This was really hard to review and I am sure I missed something.
Please, split this to 3+ patches (basic + feature1 + feature2 + ...).
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH v2 2/7] iio: adc: Add basic support for AD4170
2025-05-02 11:28 ` Andy Shevchenko
@ 2025-05-12 13:23 ` Marcelo Schmitt
0 siblings, 0 replies; 27+ messages in thread
From: Marcelo Schmitt @ 2025-05-12 13:23 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Marcelo Schmitt, linux-iio, devicetree, linux-kernel,
Ana-Maria Cusco, jic23, lars, Michael.Hennerich, dlechner,
nuno.sa, robh, krzk+dt, conor+dt
...
>
> > +#define AD4170_EXT_CLOCK_MHZ_MIN (1 * MEGA)
> > +#define AD4170_EXT_CLOCK_MHZ_MAX (17 * MEGA)
>
> Ditto. But are you sure that it's 17 and not 16?
The maximum external clock rates shown in the datasheet are 17 MHz.
The minimum clock low/high times are 27.6 ns, resulting in roughly 18 MHz.
So, the specifications indicate that 17 MHz clock would be okay to operate AD4170.
...
> ...
>
> > + nv = (u64)chan_info->input_range_uv * NANO;
> > + lshift = (pga >> 3 & 1); /* handle cases 8 and 9 */
>
> lshift = !!(pga & BIT(3));
>
> ?
>
> > + rshift = precision_bits - bipolar + (pga & 0x7) - lshift;
>
> GENMASK() ?
rshift = precision_bits - bipolar + (pga & GENMASK(2, 0)) - lshift;
?
> ...
>
> This was really hard to review and I am sure I missed something.
>
> Please, split this to 3+ patches (basic + feature1 + feature2 + ...).
Sorry about that. This part is so flexible that even basic ADC channel support
becomes quite complex due to the dynamic setup configurations and possible
combinations of input type (differential / pseudo-diff) and PGA. For v3, I split
calib gain, offset, and samp freq into separate patches. The PGA, though, is
harder to disentangle from the rest of the base driver.
Thanks,
Marcelo
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 2/7] iio: adc: Add basic support for AD4170
2025-04-28 12:28 ` [PATCH v2 2/7] iio: adc: Add basic support for AD4170 Marcelo Schmitt
2025-05-02 11:28 ` Andy Shevchenko
@ 2025-05-04 18:21 ` Jonathan Cameron
1 sibling, 0 replies; 27+ messages in thread
From: Jonathan Cameron @ 2025-05-04 18:21 UTC (permalink / raw)
To: Marcelo Schmitt
Cc: linux-iio, devicetree, linux-kernel, Ana-Maria Cusco, lars,
Michael.Hennerich, dlechner, nuno.sa, andy, robh, krzk+dt,
conor+dt, marcelo.schmitt1
On Mon, 28 Apr 2025 09:28:03 -0300
Marcelo Schmitt <marcelo.schmitt@analog.com> wrote:
> From: Ana-Maria Cusco <ana-maria.cusco@analog.com>
>
> Add support for the AD4170 ADC with the following features:
> - Single-shot read.
> - Analog front end PGA configuration.
> - Digital filter and sampling frequency configuration.
> - Calibration gain and offset configuration.
> - Differential and pseudo-differential input configuration.
>
> Signed-off-by: Ana-Maria Cusco <ana-maria.cusco@analog.com>
> Co-developed-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Various comments inline, but as Andy mentioned, this is not exactly bite sized
to review so the quality will suffer. I know I need to take a break from the screen
after this one! :) If you can break it up further that would be great.
Some smaller things like filter control are often relatively easy to separate
off.
Jonathan
> diff --git a/drivers/iio/adc/ad4170.c b/drivers/iio/adc/ad4170.c
> new file mode 100644
> index 000000000000..4d0af15cb48d
> --- /dev/null
> +++ b/drivers/iio/adc/ad4170.c
> @@ -0,0 +1,1888 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2024 Analog Devices, Inc.
> + * Author: Ana-Maria Cusco <ana-maria.cusco@analog.com>
> + * Author: Marcelo Schmitt <marcelo.schmitt@analog.com>
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/bitops.h>
> +#include <linux/delay.h>
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/iio/iio.h>
> +#include <linux/iio/sysfs.h>
This might belong in a later patch. Not sure we have custom
attrs in this one.
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/kernel.h>
> +#include <linux/math64.h>
> +#include <linux/module.h>
> +#include <linux/property.h>
> +#include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/spi/spi.h>
> +#include <linux/unaligned.h>
> +#include <linux/units.h>
> +#include <linux/util_macros.h>
> +/* AD4170 register constants */
> +
> +/* AD4170_CHAN_MAP_REG constants */
> +#define AD4170_CHAN_MAP_AIN0 0
> +#define AD4170_CHAN_MAP_AIN1 1
> +#define AD4170_CHAN_MAP_AIN2 2
> +#define AD4170_CHAN_MAP_AIN3 3
> +#define AD4170_CHAN_MAP_AIN4 4
> +#define AD4170_CHAN_MAP_AIN5 5
> +#define AD4170_CHAN_MAP_AIN6 6
> +#define AD4170_CHAN_MAP_AIN7 7
> +#define AD4170_CHAN_MAP_AIN8 8
Maybe a macro for these?
#define AD4170_CHAN_MAP_AIN(x) (x)
Perhaps it's not worth bothering. I didn't check!
> +#define AD4170_CHAN_MAP_TEMP_SENSOR 17
> +#define AD4170_CHAN_MAP_AVDD_AVSS_P 18
> +#define AD4170_CHAN_MAP_AVDD_AVSS_N 18
> +#define AD4170_CHAN_MAP_IOVDD_DGND_P 19
> +#define AD4170_CHAN_MAP_IOVDD_DGND_N 19
> +#define AD4170_CHAN_MAP_DAC_P 20
> +#define AD4170_CHAN_MAP_DAC_N 20
> +#define AD4170_CHAN_MAP_ALDO 21
> +#define AD4170_CHAN_MAP_DLDO 22
> +#define AD4170_CHAN_MAP_AVSS 23
> +#define AD4170_CHAN_MAP_DGND 24
> +#define AD4170_CHAN_MAP_REFIN1_P 25
> +#define AD4170_CHAN_MAP_REFIN1_N 26
> +#define AD4170_CHAN_MAP_REFIN2_P 27
> +#define AD4170_CHAN_MAP_REFIN2_N 28
> +#define AD4170_CHAN_MAP_REFOUT 29
> +/*
> + * There are 8 of each MISC, AFE, FILTER, FILTER_FS, OFFSET, and GAIN
> + * configuration registers. That is, there are 8 miscellaneous registers, MISC0
> + * to MISC7. Each MISC register is associated with a setup; MISCN is associated
> + * with setup number N. The other 5 above mentioned types of registers have
> + * analogous structure. A setup is a set of those registers. For example,
> + * setup 1 comprises of MISC1, AFE1, FILTER1, FILTER_FS1, OFFSET1, and GAIN1
> + * registers. Also, there are 16 CHANNEL_SETUP registers (CHANNEL_SETUP0 to
> + * CHANNEL_SETUP15). Each channel setup is associated with one of the 8 possible
> + * setups. Thus, AD4170 can support up to 16 channels but, since there are only
> + * 8 available setups, channels must share settings if more than 8 channels are
> + * configured.
> + */
> +struct ad4170_setup {
> + u16 misc;
> + u16 afe;
> + u16 filter;
> + u16 filter_fs;
> + u32 offset; /* For calibration purposes */
> + u32 gain; /* For calibration purposes */
> +};
> +
> +struct ad4170_setup_info {
> + struct ad4170_setup setup;
> + unsigned int enabled_channels;
> + unsigned int channels;
> +};
As mentioned below. We had some concerns about matching with memcpy on these
structures. Now I don't see holes today so in theory it is fine, but I think
we should still do an explicit matching function that checks field by field
just to avoid potential future issues.
>
> +struct ad4170_state {
> + struct regmap *regmap;
> + struct spi_device *spi;
> + int vrefs_uv[AD4170_MAX_SUP];
> + struct mutex lock; /* Protect read-modify-write and multi write sequences */
> + struct iio_chan_spec chans[AD4170_MAX_CHANNELS];
> + struct ad4170_chan_info chan_infos[AD4170_MAX_CHANNELS];
> + struct ad4170_setup_info setup_infos[AD4170_MAX_SETUPS];
> + u32 mclk_hz;
> + int pins_fn[AD4170_NUM_ANALOG_PINS];
> + u32 int_pin_sel;
> + int sps_tbl[ARRAY_SIZE(ad4170_filt_names)][AD4170_MAX_FS_TBL_SIZE][2];
> + struct completion completion;
> + /*
> + * DMA (thus cache coherency maintenance) requires the transfer buffers
> + * to live in their own cache lines.
> + */
> + u8 tx_buf[AD4170_SPI_MAX_XFER_LEN] __aligned(IIO_DMA_MINALIGN);
> + u8 rx_buf[AD4170_SPI_MAX_XFER_LEN];
> +};
> +
> +static int ad4170_debugfs_reg_access(struct iio_dev *indio_dev,
> + unsigned int reg, unsigned int writeval,
> + unsigned int *readval)
> +{
> + struct ad4170_state *st = iio_priv(indio_dev);
> + int ret = -EINVAL;
> +
> + if (readval)
> + ret = regmap_read(st->regmap, reg, readval);
return regmap_read()
> + else
> + ret = regmap_write(st->regmap, reg, writeval);
> +
> + return ret;
> +}
> +
> +static int ad4170_reg_read(void *context, unsigned int reg, unsigned int *val)
> +{
> + struct ad4170_state *st = context;
> + struct spi_transfer t[] = {
> + {
> + .tx_buf = st->tx_buf,
> + .len = 2,
> + },
> + {
> + .rx_buf = st->rx_buf,
> + },
> + };
> + unsigned int size;
> + int ret;
> +
> + ret = ad4170_get_reg_size(st, reg, &size);
> + if (ret)
> + return ret;
> +
> + put_unaligned_be16(AD4170_REG_READ_MASK | reg, st->tx_buf);
> + t[1].len = size;
> +
> + ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
> + if (ret)
> + return ret;
> +
> + switch (size) {
> + case 3:
> + *val = get_unaligned_be24(st->rx_buf);
> + break;
> + case 2:
> + *val = get_unaligned_be16(st->rx_buf);
> + break;
> + case 1:
> + *val = st->rx_buf[0];
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return 0;
Might as well return in all the good paths instead of break.
> +}
> +
> +static int ad4170_find_setup(struct ad4170_state *st,
> + struct ad4170_setup *target_setup,
> + unsigned int *setup_num, bool *overwrite)
> +{
> + unsigned int i;
> +
> + *setup_num = AD4170_INVALID_SETUP;
> + *overwrite = false;
> +
> + for (i = 0; i < AD4170_MAX_SETUPS; i++) {
> + struct ad4170_setup_info *setup_info = &st->setup_infos[i];
> +
> + /* Immediately accept a matching setup. */
> + if (!memcmp(target_setup, &setup_info->setup,
> + sizeof(*target_setup))) {
Didn't we run into concerns with holes, variable structure definitions etc
for these in other drivers and change them all to explicit field matches?
> + *setup_num = i;
> + return 0;
> + }
> +
> + /* Ignore all setups which are used by enabled channels. */
> + if (setup_info->enabled_channels)
> + continue;
> +
> + /* Find the least used slot. */
> + if (*setup_num == AD4170_INVALID_SETUP ||
> + setup_info->channels < st->setup_infos[*setup_num].channels)
> + *setup_num = i;
> + }
> +
> + if (*setup_num == AD4170_INVALID_SETUP)
> + return -EINVAL;
> +
> + *overwrite = true;
> + return 0;
> +}
> +
> +static int ad4170_set_filter_type(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan,
> + unsigned int val)
> +{
> +
> + if (!iio_device_claim_direct(indio_dev))
> + return -EBUSY;
> +
> + guard(mutex)(&st->lock);
> + /*
> + * The filters provide the same ODR for a given filter_fs value but
> + * there are different minimum and maximum filter_fs limits for each
> + * filter. The filter_fs value will be adjusted if the current filter_fs
> + * is out of the limits of the just requested filter. Since the
> + * filter_fs value affects the ODR (sampling_frequency), changing the
> + * filter may lead to a change in the sampling frequency.
> + */
> + old_filter = setup->filter;
> + old_filter_fs = setup->filter_fs;
> + if (val == AD4170_SINC5_AVG || val == AD4170_SINC3) {
> + if (setup->filter_fs < AD4170_SINC3_MIN_FS)
> + setup->filter_fs = AD4170_SINC3_MIN_FS;
> + if (setup->filter_fs > AD4170_SINC3_MAX_FS)
> + setup->filter_fs = AD4170_SINC3_MAX_FS;
> +
> + } else if (val == AD4170_SINC5) {
> + if (setup->filter_fs < AD4170_SINC5_MIN_FS)
> + setup->filter_fs = AD4170_SINC5_MIN_FS;
> + if (setup->filter_fs > AD4170_SINC5_MAX_FS)
> + setup->filter_fs = AD4170_SINC5_MAX_FS;
Smells like a clamp()?
> + }
> +static int __ad4170_read_sample(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan, int *val)
> +{
> + struct ad4170_state *st = iio_priv(indio_dev);
> + int settling_time_ms, ret;
> +
> + ret = ad4170_set_mode(st, AD4170_ADC_CTRL_MODE_SINGLE);
> + if (ret)
> + return ret;
> +
> + /*
> + * When a channel is manually selected by the user, the ADC needs an
> + * extra time to provide the first stable conversion. The ADC settling
> + * time depends on the filter type, filter frequency, and ADC clock
> + * frequency (see datasheet page 53). The maximum settling time among
> + * all filter configurations is 6291164 / fCLK. Use that formula to wait
> + * for sufficient time whatever the filter configuration may be.
> + */
> + settling_time_ms = DIV_ROUND_UP(6291164 * MILLI, st->mclk_hz);
> + reinit_completion(&st->completion);
No chance this triggers before we get here? I'd normally expect the reinit_completion
before the thing that might trigger it to be complete which I'd guess is the
ad4170_set_mode() call?
> + ret = wait_for_completion_timeout(&st->completion,
> + msecs_to_jiffies(settling_time_ms));
> + if (!ret)
> + dev_dbg(&st->spi->dev,
> + "No Data Ready signal. Reading after delay.\n");
> +
> + ret = regmap_read(st->regmap, AD4170_DATA_24B_REG, val);
> + if (ret)
> + return ret;
> +
> + if (chan->scan_type.sign == 's')
> + *val = sign_extend32(*val, chan->scan_type.realbits - 1);
> +
> + return 0;
> +}
> +
> +static int ad4170_read_sample(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan, int *val)
> +{
> + struct ad4170_state *st = iio_priv(indio_dev);
> + int ret;
> +
> + guard(mutex)(&st->lock);
> + /*
> + * The ADC sequences through all enabled channels. That can lead to
> + * incorrect channel being sampled if a previous read would have left a
> + * different channel enabled. Thus, always enable and disable the
> + * channel on single-shot read.
> + */
> + ret = ad4170_set_channel_enable(st, chan->address, true);
> + if (ret)
> + return ret;
> +
> + ret = __ad4170_read_sample(indio_dev, chan, val);
> + if (ret)
> + dev_err(&st->spi->dev, "failed to read sample: %d\n", ret);
I guess we print it which is better than nothing, but we also eat
the return code if the channel disable succeeds which is not good.
You will need to use multiple ret/ret2 here or duplicate the
set_channel_enable() code in an error path and main path.
> +
> + ret = ad4170_set_channel_enable(st, chan->address, false);
> + if (ret)
> + return ret;
> +
> + return IIO_VAL_INT;
> +}
> +
> +static int ad4170_read_raw(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan,
> + int *val, int *val2, long info)
> +{
> + struct ad4170_state *st = iio_priv(indio_dev);
> + struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
> + struct ad4170_setup *setup = &chan_info->setup;
> + enum ad4170_filter_type f_type;
> + unsigned int pga, fs_idx;
> + int ret;
> +
> + switch (info) {
> + case IIO_CHAN_INFO_RAW:
> + if (!iio_device_claim_direct(indio_dev))
> + return -EBUSY;
> +
> + ret = ad4170_read_sample(indio_dev, chan, val);
> + iio_device_release_direct(indio_dev);
> + return ret;
> + case IIO_CHAN_INFO_SCALE:
> + pga = FIELD_GET(AD4170_AFE_PGA_GAIN_MSK, setup->afe);
> + *val = chan_info->scale_tbl[pga][0];
> + *val2 = chan_info->scale_tbl[pga][1];
> + return IIO_VAL_INT_PLUS_NANO;
> + case IIO_CHAN_INFO_OFFSET:
> + pga = FIELD_GET(AD4170_AFE_PGA_GAIN_MSK, setup->afe);
> + *val = chan_info->offset_tbl[pga];
> + return IIO_VAL_INT;
> + case IIO_CHAN_INFO_SAMP_FREQ:
> + f_type = __ad4170_get_filter_type(setup->filter);
> + switch (f_type) {
> + case AD4170_SINC5_AVG:
> + case AD4170_SINC3:
> + fs_idx = find_closest(setup->filter_fs,
> + ad4170_sinc3_filt_fs_tbl,
> + ARRAY_SIZE(ad4170_sinc3_filt_fs_tbl));
> + *val = st->sps_tbl[f_type][fs_idx][0];
> + *val2 = st->sps_tbl[f_type][fs_idx][1];
> + break;
> + case AD4170_SINC5:
> + fs_idx = find_closest(setup->filter_fs,
> + ad4170_sinc5_filt_fs_tbl,
> + ARRAY_SIZE(ad4170_sinc5_filt_fs_tbl));
> + *val = st->sps_tbl[f_type][fs_idx][0];
> + *val2 = st->sps_tbl[f_type][fs_idx][1];
> + break;
> + default:
> + return -EINVAL;
> + }
> + return IIO_VAL_INT_PLUS_MICRO;
I'd return earlier where the breaks are to give a tiny bit simpler flow.
> + case IIO_CHAN_INFO_CALIBBIAS:
> + *val = setup->offset;
> + return IIO_VAL_INT;
> + case IIO_CHAN_INFO_CALIBSCALE:
> + *val = setup->gain;
> + return IIO_VAL_INT;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static int ad4170_fill_scale_tbl(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan)
> +{
> + struct ad4170_state *st = iio_priv(indio_dev);
> + struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
> + int bipolar = chan->scan_type.sign == 's' ? 1 : 0;
> + int precision_bits = chan->scan_type.realbits;
> + int pga, ainm_voltage, ret;
> + unsigned long long offset;
> +
> + ainm_voltage = 0;
> + ret = ad4170_get_ain_voltage_uv(st, chan->channel2, &ainm_voltage);
> + if (ret < 0)
> + return dev_err_probe(&st->spi->dev, ret,
> + "Failed to fill scale table\n");
> +
> + for (pga = 0; pga < AD4170_NUM_PGA_OPTIONS; pga++) {
> + u64 nv;
> + unsigned int lshift, rshift;
> +
> + /*
> + * The scale factor to get ADC output codes to values in mV
> + * units is given by:
> + * _scale = (input_range / gain) / 2^precision
> + * AD4170 gain is a power of 2 so the above can be written as
> + * _scale = input_range / 2^(precision + gain)
> + * Keep the input range in µV to avoid truncating the less
> + * significan bits when right shifting it so to preserve scale
> + * precision.
> + */
> + nv = (u64)chan_info->input_range_uv * NANO;
> + lshift = (pga >> 3 & 1); /* handle cases 8 and 9 */
I'm lost. Where did 8 and 9 come from?
> + rshift = precision_bits - bipolar + (pga & 0x7) - lshift;
> + chan_info->scale_tbl[pga][0] = 0;
> + chan_info->scale_tbl[pga][1] = div_u64(nv >> rshift, MILLI);
> +
> + /*
> + * If the negative input is not at GND, the conversion result
> + * (which is relative to IN-) will be offset by the level at IN-.
> + * Use the scale factor the other way around to go from a known
> + * voltage to the corresponding ADC output code.
> + * With that, we are able to get to what would be the output
> + * code for the voltage at the negative input.
> + * If the negative input is not fixed, there is no offset.
> + */
> + offset = ((unsigned long long)abs(ainm_voltage)) * MICRO;
> + offset = DIV_ROUND_CLOSEST_ULL(offset, chan_info->scale_tbl[pga][1]);
> +
> + /*
> + * After divided by the scale, offset will always fit into 31
> + * bits. For _raw + _offset to be relative to GND, the value
> + * provided as _offset is of opposite sign than the real offset.
> + */
> + if (ainm_voltage > 0)
> + chan_info->offset_tbl[pga] = -(int)(offset);
> + else
> + chan_info->offset_tbl[pga] = (int)(offset);
> + }
> + return 0;
> +}
> +
> +static int ad4170_read_avail(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan,
> + const int **vals, int *type, int *length,
> + long info)
> +{
> + struct ad4170_state *st = iio_priv(indio_dev);
> + struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
> + enum ad4170_filter_type f_type;
> +
> + switch (info) {
> + case IIO_CHAN_INFO_SCALE:
> + *vals = (int *)chan_info->scale_tbl;
> + *length = ARRAY_SIZE(chan_info->scale_tbl) * 2;
> + *type = IIO_VAL_INT_PLUS_NANO;
> + return IIO_AVAIL_LIST;
> + case IIO_CHAN_INFO_SAMP_FREQ:
> + f_type = ad4170_get_filter_type(indio_dev, chan);
> + switch (f_type) {
> + case AD4170_SINC5_AVG:
> + fallthrough;
If there is nothing in it, IIRC you can just skip the fallthrough.
case AD4170_SINC5_AVG:
case AD4170_SINC3:
*vals = ...
> + case AD4170_SINC3:
> + *vals = (int *)st->sps_tbl[f_type];
> + *length = ARRAY_SIZE(ad4170_sinc3_filt_fs_tbl) * 2;
> + break;
> + case AD4170_SINC5:
> + *vals = (int *)st->sps_tbl[f_type];
> + *length = ARRAY_SIZE(ad4170_sinc5_filt_fs_tbl) * 2;
> + break;
> + default:
> + return -EINVAL;
> + }
> + *type = IIO_VAL_INT_PLUS_MICRO;
> +
> + return IIO_AVAIL_LIST;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static int ad4170_set_pga(struct ad4170_state *st,
> + struct iio_chan_spec const *chan, int val, int val2)
> +{
> + struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
> + struct ad4170_setup *setup = &chan_info->setup;
> + unsigned int old_pga = FIELD_GET(AD4170_AFE_PGA_GAIN_MSK, setup->afe);
> + unsigned int pga;
> + int ret;
> +
> + for (pga = 0; pga < AD4170_NUM_PGA_OPTIONS; pga++) {
> + if (val == chan_info->scale_tbl[pga][0] &&
> + val2 == chan_info->scale_tbl[pga][1])
> + break;
> + }
> +
> + if (pga == AD4170_NUM_PGA_OPTIONS)
> + return -EINVAL;
> +
> + if (pga == old_pga)
> + return 0;
> +
> + guard(mutex)(&st->lock);
> + setup->afe &= ~AD4170_AFE_PGA_GAIN_MSK;
> + setup->afe |= FIELD_PREP(AD4170_AFE_PGA_GAIN_MSK, pga);
> +
> + ret = ad4170_write_channel_setup(st, chan->address, false);
> + if (ret) {
> + setup->afe &= ~AD4170_AFE_PGA_GAIN_MSK;
> + setup->afe |= FIELD_PREP(AD4170_AFE_PGA_GAIN_MSK, old_pga);
I'd
return ret;
> + }
> +
> + return ret;
return 0;
So the error path is nicely separated.
> +}
> +static int ad4170_parse_firmware(struct iio_dev *indio_dev)
> +{
> + struct ad4170_state *st = iio_priv(indio_dev);
> + struct device *dev = &st->spi->dev;
> + int reg_data, ret, i;
> +
> + st->mclk_hz = AD4170_INT_CLOCK_16MHZ;
> +
> + for (i = 0; i < AD4170_NUM_ANALOG_PINS; i++)
> + st->pins_fn[i] = AD4170_PIN_UNASIGNED;
> +
> + /* On power on, device defaults to using SDO pin for data ready signal */
> + st->int_pin_sel = AD4170_INT_PIN_SDO;
> + ret = device_property_match_property_string(dev, "interrupt-names",
> + ad4170_int_pin_names,
> + ARRAY_SIZE(ad4170_int_pin_names));
Hmm. This is unusual handling. Normally we just try to get the first interrupt by
name and if that fails move on to the second one. What you have here seems valid
just not a choice I recall seeing before.
> + if (ret >= 0)
> + st->int_pin_sel = ret;
> +
> + reg_data = FIELD_PREP(AD4170_PIN_MUXING_DIG_AUX1_CTRL_MSK,
> + st->int_pin_sel == AD4170_INT_PIN_DIG_AUX1 ?
> + AD4170_PIN_MUXING_DIG_AUX1_RDY :
> + AD4170_PIN_MUXING_DIG_AUX1_DISABLED);
> +
> + ret = regmap_update_bits(st->regmap, AD4170_PIN_MUXING_REG,
> + AD4170_PIN_MUXING_DIG_AUX1_CTRL_MSK, reg_data);
> + if (ret)
> + return ret;
> +
> + return ad4170_parse_channels(indio_dev);
> +}
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 3/7] iio: adc: ad4170: Add support for buffered data capture
2025-04-28 12:27 [PATCH v2 0/7] iio: adc: Add support for AD4170 series of ADCs Marcelo Schmitt
2025-04-28 12:27 ` [PATCH v2 1/7] dt-bindings: iio: adc: Add AD4170 Marcelo Schmitt
2025-04-28 12:28 ` [PATCH v2 2/7] iio: adc: Add basic support for AD4170 Marcelo Schmitt
@ 2025-04-28 12:28 ` Marcelo Schmitt
2025-04-29 22:00 ` Andy Shevchenko
2025-05-04 17:57 ` Jonathan Cameron
2025-04-28 12:28 ` [PATCH v2 4/7] iio: adc: ad4170: Add clock provider support Marcelo Schmitt
` (3 subsequent siblings)
6 siblings, 2 replies; 27+ messages in thread
From: Marcelo Schmitt @ 2025-04-28 12:28 UTC (permalink / raw)
To: linux-iio, devicetree, linux-kernel
Cc: jic23, lars, Michael.Hennerich, dlechner, nuno.sa, andy, robh,
krzk+dt, conor+dt, marcelo.schmitt1
Extend the AD4170 driver to allow buffered data capture in continuous read
mode. In continuous read mode, the chip skips the instruction phase and
outputs just ADC sample data, enabling faster sample rates to be reached.
The internal channel sequencer always starts sampling from channel 0 and
channel 0 must be enabled if more than one channel is selected for data
capture. The scan mask validation callback checks the aforementioned
condition is met.
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
changes since v1
- Using bitmap_weight().
- rx_buf changed from __be32 to u8 array to better cope with new regmap config.
drivers/iio/adc/Kconfig | 2 +
drivers/iio/adc/ad4170.c | 199 ++++++++++++++++++++++++++++++++++++++-
2 files changed, 199 insertions(+), 2 deletions(-)
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index d5d0308da007..9b4787c127fc 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -75,6 +75,8 @@ config AD4170
tristate "Analog Device AD4170 ADC Driver"
depends on SPI
select REGMAP_SPI
+ select IIO_BUFFER
+ select IIO_TRIGGERED_BUFFER
help
Say yes here to build support for Analog Devices AD4170 SPI analog
to digital converters (ADC).
diff --git a/drivers/iio/adc/ad4170.c b/drivers/iio/adc/ad4170.c
index 4d0af15cb48d..5fcf1c023ac2 100644
--- a/drivers/iio/adc/ad4170.c
+++ b/drivers/iio/adc/ad4170.c
@@ -10,8 +10,12 @@
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
+#include <linux/iio/buffer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
+#include <linux/iio/trigger.h>
+#include <linux/iio/trigger_consumer.h>
+#include <linux/iio/triggered_buffer.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
@@ -54,6 +58,7 @@
#define AD4170_FILTER_FS_REG(x) (0xC7 + 14 * (x))
#define AD4170_OFFSET_REG(x) (0xCA + 14 * (x))
#define AD4170_GAIN_REG(x) (0xCD + 14 * (x))
+#define AD4170_ADC_CTRL_CONT_READ_EXIT_REG 0x200 /* virtual reg */
#define AD4170_REG_READ_MASK BIT(14)
@@ -221,6 +226,7 @@ static const unsigned int ad4170_reg_size[] = {
[AD4170_OFFSET_REG(5) ... AD4170_GAIN_REG(5)] = 3,
[AD4170_OFFSET_REG(6) ... AD4170_GAIN_REG(6)] = 3,
[AD4170_OFFSET_REG(7) ... AD4170_GAIN_REG(7)] = 3,
+ [AD4170_ADC_CTRL_CONT_READ_EXIT_REG] = 0,
};
enum ad4170_ref_buf {
@@ -347,12 +353,16 @@ struct ad4170_state {
u32 int_pin_sel;
int sps_tbl[ARRAY_SIZE(ad4170_filt_names)][AD4170_MAX_FS_TBL_SIZE][2];
struct completion completion;
+ struct iio_trigger *trig;
+ struct spi_transfer xfer;
+ struct spi_message msg;
+ __be32 bounce_buffer[AD4170_MAX_CHANNELS];
/*
* DMA (thus cache coherency maintenance) requires the transfer buffers
* to live in their own cache lines.
*/
u8 tx_buf[AD4170_SPI_MAX_XFER_LEN] __aligned(IIO_DMA_MINALIGN);
- u8 rx_buf[AD4170_SPI_MAX_XFER_LEN];
+ u8 rx_buf[4];
};
static void ad4170_fill_sps_tbl(struct ad4170_state *st)
@@ -434,6 +444,10 @@ static int ad4170_reg_write(void *context, unsigned int reg, unsigned int val)
case 1:
st->tx_buf[2] = val;
break;
+ case 0:
+ /* Write continuous read exit code */
+ st->tx_buf[0] = AD4170_ADC_CTRL_CONT_READ_EXIT;
+ return spi_write(st->spi, st->tx_buf, 1);
default:
return -EINVAL;
}
@@ -843,6 +857,7 @@ static const struct iio_chan_spec ad4170_channel_template = {
.scan_type = {
.realbits = 24,
.storagebits = 32,
+ .shift = 8,
.endianness = IIO_BE,
},
};
@@ -1451,11 +1466,27 @@ static int ad4170_write_raw_get_fmt(struct iio_dev *indio_dev,
}
}
+static int ad4170_update_scan_mode(struct iio_dev *indio_dev,
+ const unsigned long *active_scan_mask)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ unsigned int chan_index;
+ int ret;
+
+ iio_for_each_active_channel(indio_dev, chan_index) {
+ ret = ad4170_set_channel_enable(st, chan_index, true);
+ if (ret)
+ return ret;
+ }
+ return 0;
+}
+
static const struct iio_info ad4170_info = {
.read_raw = ad4170_read_raw,
.read_avail = ad4170_read_avail,
.write_raw = ad4170_write_raw,
.write_raw_get_fmt = ad4170_write_raw_get_fmt,
+ .update_scan_mode = ad4170_update_scan_mode,
.debugfs_reg_access = ad4170_debugfs_reg_access,
};
@@ -1731,16 +1762,166 @@ static int ad4170_initial_config(struct iio_dev *indio_dev)
AD4170_ADC_CTRL_MULTI_DATA_REG_SEL_MSK);
}
+static int ad4170_prepare_spi_message(struct ad4170_state *st)
+{
+ /*
+ * Continuous data register read is enabled on buffer postenable so
+ * no instruction phase is needed meaning we don't need to send the
+ * register address to read data. Transfer only needs the read buffer.
+ */
+ st->xfer.rx_buf = &st->rx_buf;
+ st->xfer.len = BITS_TO_BYTES(ad4170_channel_template.scan_type.realbits);
+
+ spi_message_init_with_transfers(&st->msg, &st->xfer, 1);
+
+ return devm_spi_optimize_message(&st->spi->dev, st->spi, &st->msg);
+}
+
+static int ad4170_buffer_postenable(struct iio_dev *indio_dev)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ int ret;
+
+ ret = ad4170_set_mode(st, AD4170_ADC_CTRL_MODE_CONT);
+ if (ret < 0)
+ return ret;
+
+ /*
+ * Enables continuous data register read.
+ * This enables continuous read of the ADC Data register. The ADC must
+ * be in a continuous conversion mode.
+ */
+ return regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG,
+ AD4170_ADC_CTRL_CONT_READ_MSK,
+ FIELD_PREP(AD4170_ADC_CTRL_CONT_READ_MSK,
+ AD4170_ADC_CTRL_CONT_READ_ENABLE));
+}
+
+static int ad4170_buffer_predisable(struct iio_dev *indio_dev)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ int ret, i;
+
+ /*
+ * Use a high register address (virtual register) to request a write of
+ * 0xA5 to the ADC during the first 8 SCLKs of the ADC data read cycle,
+ * thus exiting continuous read.
+ */
+ ret = regmap_write(st->regmap, AD4170_ADC_CTRL_CONT_READ_EXIT_REG, 0);
+
+ ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG,
+ AD4170_ADC_CTRL_CONT_READ_MSK,
+ FIELD_PREP(AD4170_ADC_CTRL_CONT_READ_MSK,
+ AD4170_ADC_CTRL_CONT_READ_DISABLE));
+ if (ret)
+ return ret;
+
+ ret = ad4170_set_mode(st, AD4170_ADC_CTRL_MODE_IDLE);
+ if (ret)
+ return ret;
+
+ /*
+ * The ADC sequences through all the enabled channels (see datasheet
+ * page 95). That can lead to incorrect channel being read if a
+ * single-shot read (or buffered read with different active_scan_mask)
+ * is done after buffer disable. Disable all channels so only requested
+ * channels will be read.
+ */
+ for (i = 0; i < indio_dev->num_channels; i++) {
+ ret = ad4170_set_channel_enable(st, i, false);
+ if (ret)
+ return ret;
+ }
+ return ret;
+}
+
+static bool ad4170_validate_scan_mask(struct iio_dev *indio_dev,
+ const unsigned long *scan_mask)
+{
+ unsigned int masklength = iio_get_masklength(indio_dev);
+
+ /*
+ * The channel sequencer cycles through the enabled channels in
+ * sequential order, from channel 0 to channel 15, bypassing disabled
+ * channels. When more than one channel is enabled, channel 0 must
+ * always be enabled. See datasheet channel_en register description at
+ * page 95.
+ */
+ if (bitmap_weight(scan_mask, masklength) > 1)
+ return test_bit(0, scan_mask);
+
+ return true;
+}
+
+static const struct iio_buffer_setup_ops ad4170_buffer_ops = {
+ .postenable = ad4170_buffer_postenable,
+ .predisable = ad4170_buffer_predisable,
+ .validate_scan_mask = ad4170_validate_scan_mask,
+};
+
+static irqreturn_t ad4170_trigger_handler(int irq, void *p)
+{
+ struct iio_poll_func *pf = p;
+ struct iio_dev *indio_dev = pf->indio_dev;
+ struct ad4170_state *st = iio_priv(indio_dev);
+ int i, ret;
+
+ iio_for_each_active_channel(indio_dev, i) {
+ ret = spi_sync(st->spi, &st->msg);
+ if (ret)
+ goto err_out;
+
+ st->bounce_buffer[i] = get_unaligned_be32(st->rx_buf);
+ }
+
+ iio_push_to_buffers(indio_dev, st->bounce_buffer);
+err_out:
+ iio_trigger_notify_done(indio_dev->trig);
+ return IRQ_HANDLED;
+}
+
+static const struct iio_trigger_ops ad4170_trigger_ops = {
+ .validate_device = iio_trigger_validate_own_device,
+};
+
static irqreturn_t ad4170_irq_handler(int irq, void *dev_id)
{
struct iio_dev *indio_dev = dev_id;
struct ad4170_state *st = iio_priv(indio_dev);
- complete(&st->completion);
+ if (iio_buffer_enabled(indio_dev))
+ iio_trigger_poll(st->trig);
+ else
+ complete(&st->completion);
return IRQ_HANDLED;
};
+static int ad4170_trigger_setup(struct iio_dev *indio_dev)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ int ret;
+
+ st->trig = devm_iio_trigger_alloc(indio_dev->dev.parent, "%s-trig%d",
+ indio_dev->name,
+ iio_device_id(indio_dev));
+ if (!st->trig)
+ return -ENOMEM;
+
+ st->trig->ops = &ad4170_trigger_ops;
+ st->trig->dev.parent = indio_dev->dev.parent;
+
+ iio_trigger_set_drvdata(st->trig, indio_dev);
+ ret = devm_iio_trigger_register(indio_dev->dev.parent, st->trig);
+ if (ret)
+ return dev_err_probe(&st->spi->dev, ret,
+ "Failed to register trigger\n");
+
+ indio_dev->trig = iio_trigger_get(st->trig);
+
+ return 0;
+}
+
static int ad4170_regulator_setup(struct ad4170_state *st)
{
struct device *dev = &st->spi->dev;
@@ -1851,8 +2032,22 @@ static int ad4170_probe(struct spi_device *spi)
indio_dev->name, indio_dev);
if (ret)
return ret;
+
+ ret = ad4170_trigger_setup(indio_dev);
+ if (ret)
+ return ret;
}
+ ret = ad4170_prepare_spi_message(st);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to prepare SPI message\n");
+
+ ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
+ &ad4170_trigger_handler,
+ &ad4170_buffer_ops);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to setup read buffer\n");
+
return devm_iio_device_register(dev, indio_dev);
}
--
2.47.2
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v2 3/7] iio: adc: ad4170: Add support for buffered data capture
2025-04-28 12:28 ` [PATCH v2 3/7] iio: adc: ad4170: Add support for buffered data capture Marcelo Schmitt
@ 2025-04-29 22:00 ` Andy Shevchenko
2025-04-30 13:40 ` Marcelo Schmitt
2025-05-04 17:57 ` Jonathan Cameron
1 sibling, 1 reply; 27+ messages in thread
From: Andy Shevchenko @ 2025-04-29 22:00 UTC (permalink / raw)
To: Marcelo Schmitt
Cc: linux-iio, devicetree, linux-kernel, jic23, lars,
Michael.Hennerich, dlechner, nuno.sa, andy, robh, krzk+dt,
conor+dt, marcelo.schmitt1
On Mon, Apr 28, 2025 at 3:28 PM Marcelo Schmitt
<marcelo.schmitt@analog.com> wrote:
>
> Extend the AD4170 driver to allow buffered data capture in continuous read
> mode. In continuous read mode, the chip skips the instruction phase and
> outputs just ADC sample data, enabling faster sample rates to be reached.
> The internal channel sequencer always starts sampling from channel 0 and
> channel 0 must be enabled if more than one channel is selected for data
> capture. The scan mask validation callback checks the aforementioned
checks if the
> condition is met.
...
> +static int ad4170_prepare_spi_message(struct ad4170_state *st)
> +{
> + /*
> + * Continuous data register read is enabled on buffer postenable so
> + * no instruction phase is needed meaning we don't need to send the
> + * register address to read data. Transfer only needs the read buffer.
> + */
> + st->xfer.rx_buf = &st->rx_buf;
> + st->xfer.len = BITS_TO_BYTES(ad4170_channel_template.scan_type.realbits);
This will give, e.g., 3 for the realbits == 24. Is this expected?
> + spi_message_init_with_transfers(&st->msg, &st->xfer, 1);
> +
> + return devm_spi_optimize_message(&st->spi->dev, st->spi, &st->msg);
> +}
...
> +static int ad4170_buffer_predisable(struct iio_dev *indio_dev)
> +{
> + struct ad4170_state *st = iio_priv(indio_dev);
> + int ret, i;
Why is 'i' signed?
> + /*
> + * Use a high register address (virtual register) to request a write of
> + * 0xA5 to the ADC during the first 8 SCLKs of the ADC data read cycle,
> + * thus exiting continuous read.
> + */
> + ret = regmap_write(st->regmap, AD4170_ADC_CTRL_CONT_READ_EXIT_REG, 0);
No error check.
> + ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG,
> + AD4170_ADC_CTRL_CONT_READ_MSK,
> + FIELD_PREP(AD4170_ADC_CTRL_CONT_READ_MSK,
> + AD4170_ADC_CTRL_CONT_READ_DISABLE));
> + if (ret)
> + return ret;
> +
> + ret = ad4170_set_mode(st, AD4170_ADC_CTRL_MODE_IDLE);
> + if (ret)
> + return ret;
> +
> + /*
> + * The ADC sequences through all the enabled channels (see datasheet
> + * page 95). That can lead to incorrect channel being read if a
> + * single-shot read (or buffered read with different active_scan_mask)
> + * is done after buffer disable. Disable all channels so only requested
> + * channels will be read.
> + */
> + for (i = 0; i < indio_dev->num_channels; i++) {
> + ret = ad4170_set_channel_enable(st, i, false);
> + if (ret)
> + return ret;
> + }
> + return ret;
Wouldn't return 0; suffice?
> +}
...
> +static bool ad4170_validate_scan_mask(struct iio_dev *indio_dev,
> + const unsigned long *scan_mask)
> +{
> + unsigned int masklength = iio_get_masklength(indio_dev);
> +
> + /*
> + * The channel sequencer cycles through the enabled channels in
> + * sequential order, from channel 0 to channel 15, bypassing disabled
> + * channels. When more than one channel is enabled, channel 0 must
> + * always be enabled. See datasheet channel_en register description at
> + * page 95.
> + */
> + if (bitmap_weight(scan_mask, masklength) > 1)
> + return test_bit(0, scan_mask);
> + return true;
Hmm... Is it possible to get weight == 0 and true here?
> +}
...
> +static irqreturn_t ad4170_trigger_handler(int irq, void *p)
> +{
> + struct iio_poll_func *pf = p;
> + struct iio_dev *indio_dev = pf->indio_dev;
> + struct ad4170_state *st = iio_priv(indio_dev);
> + int i, ret;
Why is 'i' signed? (And even in the original case it's inconsistent to
the similar in another function)
> + iio_for_each_active_channel(indio_dev, i) {
> + ret = spi_sync(st->spi, &st->msg);
> + if (ret)
> + goto err_out;
> +
> + st->bounce_buffer[i] = get_unaligned_be32(st->rx_buf);
> + }
> +
> + iio_push_to_buffers(indio_dev, st->bounce_buffer);
> +err_out:
> + iio_trigger_notify_done(indio_dev->trig);
> + return IRQ_HANDLED;
> +}
...
> + return dev_err_probe(&st->spi->dev, ret,
> + "Failed to register trigger\n");
One line?
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH v2 3/7] iio: adc: ad4170: Add support for buffered data capture
2025-04-29 22:00 ` Andy Shevchenko
@ 2025-04-30 13:40 ` Marcelo Schmitt
2025-05-02 8:56 ` Andy Shevchenko
2025-05-04 17:27 ` Jonathan Cameron
0 siblings, 2 replies; 27+ messages in thread
From: Marcelo Schmitt @ 2025-04-30 13:40 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Marcelo Schmitt, linux-iio, devicetree, linux-kernel, jic23, lars,
Michael.Hennerich, dlechner, nuno.sa, andy, robh, krzk+dt,
conor+dt
Hi Andy, thank you for your review.
...
> > +static int ad4170_prepare_spi_message(struct ad4170_state *st)
> > +{
> > + /*
> > + * Continuous data register read is enabled on buffer postenable so
> > + * no instruction phase is needed meaning we don't need to send the
> > + * register address to read data. Transfer only needs the read buffer.
> > + */
> > + st->xfer.rx_buf = &st->rx_buf;
> > + st->xfer.len = BITS_TO_BYTES(ad4170_channel_template.scan_type.realbits);
>
> This will give, e.g., 3 for the realbits == 24. Is this expected?
Yes, in continuous read mode the ADC outputs just the conversion result bits
(24-bits) so a 3-byte length transfer is enough to get the conversion data for a
channel.
>
...
>
> > + return dev_err_probe(&st->spi->dev, ret,
> > + "Failed to register trigger\n");
>
> One line?
It goes up to 89 columns if make in one line. I know there are other places in
this driver where 80 columns are exceeded, but in this case it's easier to
avoid going beyond 80 columns without drying up the error message.
Anyway, I'll make it one line if it's confirmed to be the preferable way to have
it.
Thanks,
Marcelo
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH v2 3/7] iio: adc: ad4170: Add support for buffered data capture
2025-04-30 13:40 ` Marcelo Schmitt
@ 2025-05-02 8:56 ` Andy Shevchenko
2025-05-04 17:27 ` Jonathan Cameron
1 sibling, 0 replies; 27+ messages in thread
From: Andy Shevchenko @ 2025-05-02 8:56 UTC (permalink / raw)
To: Marcelo Schmitt
Cc: Marcelo Schmitt, linux-iio, devicetree, linux-kernel, jic23, lars,
Michael.Hennerich, dlechner, nuno.sa, robh, krzk+dt, conor+dt
On Wed, Apr 30, 2025 at 10:40:21AM -0300, Marcelo Schmitt wrote:
...
> > > + return dev_err_probe(&st->spi->dev, ret,
> > > + "Failed to register trigger\n");
> >
> > One line?
>
> It goes up to 89 columns if make in one line. I know there are other places in
> this driver where 80 columns are exceeded, but in this case it's easier to
> avoid going beyond 80 columns without drying up the error message.
> Anyway, I'll make it one line if it's confirmed to be the preferable way to have
> it.
The string literal endings are relaxed in the line limit for 10+ years...
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 3/7] iio: adc: ad4170: Add support for buffered data capture
2025-04-30 13:40 ` Marcelo Schmitt
2025-05-02 8:56 ` Andy Shevchenko
@ 2025-05-04 17:27 ` Jonathan Cameron
1 sibling, 0 replies; 27+ messages in thread
From: Jonathan Cameron @ 2025-05-04 17:27 UTC (permalink / raw)
To: Marcelo Schmitt
Cc: Andy Shevchenko, Marcelo Schmitt, linux-iio, devicetree,
linux-kernel, lars, Michael.Hennerich, dlechner, nuno.sa, andy,
robh, krzk+dt, conor+dt
On Wed, 30 Apr 2025 10:40:21 -0300
Marcelo Schmitt <marcelo.schmitt1@gmail.com> wrote:
> Hi Andy, thank you for your review.
>
> ...
> > > +static int ad4170_prepare_spi_message(struct ad4170_state *st)
> > > +{
> > > + /*
> > > + * Continuous data register read is enabled on buffer postenable so
> > > + * no instruction phase is needed meaning we don't need to send the
> > > + * register address to read data. Transfer only needs the read buffer.
> > > + */
> > > + st->xfer.rx_buf = &st->rx_buf;
> > > + st->xfer.len = BITS_TO_BYTES(ad4170_channel_template.scan_type.realbits);
> >
> > This will give, e.g., 3 for the realbits == 24. Is this expected?
>
> Yes, in continuous read mode the ADC outputs just the conversion result bits
> (24-bits) so a 3-byte length transfer is enough to get the conversion data for a
> channel.
>
> >
> ...
> >
> > > + return dev_err_probe(&st->spi->dev, ret,
> > > + "Failed to register trigger\n");
> >
> > One line?
>
> It goes up to 89 columns if make in one line. I know there are other places in
> this driver where 80 columns are exceeded, but in this case it's easier to
> avoid going beyond 80 columns without drying up the error message.
> Anyway, I'll make it one line if it's confirmed to be the preferable way to have
> it.
In here there are what I think are multiple ways to get to the same ultimate
device. (indio->dev.parent is used the line above). Better perhaps to
have one 'dev' that is appropriate for use in both places.
>
> Thanks,
> Marcelo
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 3/7] iio: adc: ad4170: Add support for buffered data capture
2025-04-28 12:28 ` [PATCH v2 3/7] iio: adc: ad4170: Add support for buffered data capture Marcelo Schmitt
2025-04-29 22:00 ` Andy Shevchenko
@ 2025-05-04 17:57 ` Jonathan Cameron
1 sibling, 0 replies; 27+ messages in thread
From: Jonathan Cameron @ 2025-05-04 17:57 UTC (permalink / raw)
To: Marcelo Schmitt
Cc: linux-iio, devicetree, linux-kernel, lars, Michael.Hennerich,
dlechner, nuno.sa, andy, robh, krzk+dt, conor+dt,
marcelo.schmitt1
On Mon, 28 Apr 2025 09:28:20 -0300
Marcelo Schmitt <marcelo.schmitt@analog.com> wrote:
> Extend the AD4170 driver to allow buffered data capture in continuous read
> mode. In continuous read mode, the chip skips the instruction phase and
> outputs just ADC sample data, enabling faster sample rates to be reached.
> The internal channel sequencer always starts sampling from channel 0 and
> channel 0 must be enabled if more than one channel is selected for data
> capture. The scan mask validation callback checks the aforementioned
> condition is met.
>
> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
A few minor things spotted inline.
Thanks,
Jonathan
> ---
> changes since v1
> - Using bitmap_weight().
> - rx_buf changed from __be32 to u8 array to better cope with new regmap config.
>
> drivers/iio/adc/Kconfig | 2 +
> drivers/iio/adc/ad4170.c | 199 ++++++++++++++++++++++++++++++++++++++-
> 2 files changed, 199 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index d5d0308da007..9b4787c127fc 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -75,6 +75,8 @@ config AD4170
> tristate "Analog Device AD4170 ADC Driver"
> depends on SPI
> select REGMAP_SPI
> + select IIO_BUFFER
> + select IIO_TRIGGERED_BUFFER
> help
> Say yes here to build support for Analog Devices AD4170 SPI analog
> to digital converters (ADC).
> diff --git a/drivers/iio/adc/ad4170.c b/drivers/iio/adc/ad4170.c
> index 4d0af15cb48d..5fcf1c023ac2 100644
> --- a/drivers/iio/adc/ad4170.c
> +++ b/drivers/iio/adc/ad4170.c
> @@ -10,8 +10,12 @@
> #include <linux/delay.h>
> #include <linux/device.h>
> #include <linux/err.h>
> +#include <linux/iio/buffer.h>
> #include <linux/iio/iio.h>
> #include <linux/iio/sysfs.h>
> +#include <linux/iio/trigger.h>
> +#include <linux/iio/trigger_consumer.h>
> +#include <linux/iio/triggered_buffer.h>
> #include <linux/interrupt.h>
> #include <linux/irq.h>
> #include <linux/kernel.h>
> @@ -54,6 +58,7 @@
> #define AD4170_FILTER_FS_REG(x) (0xC7 + 14 * (x))
> #define AD4170_OFFSET_REG(x) (0xCA + 14 * (x))
> #define AD4170_GAIN_REG(x) (0xCD + 14 * (x))
> +#define AD4170_ADC_CTRL_CONT_READ_EXIT_REG 0x200 /* virtual reg */
>
> #define AD4170_REG_READ_MASK BIT(14)
>
> @@ -221,6 +226,7 @@ static const unsigned int ad4170_reg_size[] = {
> [AD4170_OFFSET_REG(5) ... AD4170_GAIN_REG(5)] = 3,
> [AD4170_OFFSET_REG(6) ... AD4170_GAIN_REG(6)] = 3,
> [AD4170_OFFSET_REG(7) ... AD4170_GAIN_REG(7)] = 3,
> + [AD4170_ADC_CTRL_CONT_READ_EXIT_REG] = 0,
> };
>
> enum ad4170_ref_buf {
> @@ -347,12 +353,16 @@ struct ad4170_state {
> u32 int_pin_sel;
> int sps_tbl[ARRAY_SIZE(ad4170_filt_names)][AD4170_MAX_FS_TBL_SIZE][2];
> struct completion completion;
> + struct iio_trigger *trig;
> + struct spi_transfer xfer;
> + struct spi_message msg;
> + __be32 bounce_buffer[AD4170_MAX_CHANNELS];
> /*
> * DMA (thus cache coherency maintenance) requires the transfer buffers
> * to live in their own cache lines.
> */
> u8 tx_buf[AD4170_SPI_MAX_XFER_LEN] __aligned(IIO_DMA_MINALIGN);
> - u8 rx_buf[AD4170_SPI_MAX_XFER_LEN];
> + u8 rx_buf[4];
Why this change?
> };
> +
> +static int ad4170_buffer_postenable(struct iio_dev *indio_dev)
> +{
> + struct ad4170_state *st = iio_priv(indio_dev);
> + int ret;
> +
> + ret = ad4170_set_mode(st, AD4170_ADC_CTRL_MODE_CONT);
> + if (ret < 0)
> + return ret;
> +
> + /*
> + * Enables continuous data register read.
> + * This enables continuous read of the ADC Data register. The ADC must
First two sentences seem to say the same thing.
> + * be in a continuous conversion mode.
> + */
> + return regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG,
> + AD4170_ADC_CTRL_CONT_READ_MSK,
> + FIELD_PREP(AD4170_ADC_CTRL_CONT_READ_MSK,
> + AD4170_ADC_CTRL_CONT_READ_ENABLE));
> +}
> +
> +static int ad4170_buffer_predisable(struct iio_dev *indio_dev)
> +{
> + struct ad4170_state *st = iio_priv(indio_dev);
> + int ret, i;
> +
> + /*
> + * Use a high register address (virtual register) to request a write of
> + * 0xA5 to the ADC during the first 8 SCLKs of the ADC data read cycle,
> + * thus exiting continuous read.
> + */
> + ret = regmap_write(st->regmap, AD4170_ADC_CTRL_CONT_READ_EXIT_REG, 0);
> +
> + ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG,
> + AD4170_ADC_CTRL_CONT_READ_MSK,
> + FIELD_PREP(AD4170_ADC_CTRL_CONT_READ_MSK,
> + AD4170_ADC_CTRL_CONT_READ_DISABLE));
> + if (ret)
> + return ret;
> +
> + ret = ad4170_set_mode(st, AD4170_ADC_CTRL_MODE_IDLE);
> + if (ret)
> + return ret;
> +
> + /*
> + * The ADC sequences through all the enabled channels (see datasheet
> + * page 95). That can lead to incorrect channel being read if a
> + * single-shot read (or buffered read with different active_scan_mask)
> + * is done after buffer disable. Disable all channels so only requested
> + * channels will be read.
> + */
> + for (i = 0; i < indio_dev->num_channels; i++) {
> + ret = ad4170_set_channel_enable(st, i, false);
> + if (ret)
> + return ret;
> + }
> + return ret;
return 0; When we know we are in a good path we should make that clear.
> +}
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 4/7] iio: adc: ad4170: Add clock provider support
2025-04-28 12:27 [PATCH v2 0/7] iio: adc: Add support for AD4170 series of ADCs Marcelo Schmitt
` (2 preceding siblings ...)
2025-04-28 12:28 ` [PATCH v2 3/7] iio: adc: ad4170: Add support for buffered data capture Marcelo Schmitt
@ 2025-04-28 12:28 ` Marcelo Schmitt
2025-04-29 22:10 ` Andy Shevchenko
2025-05-06 8:21 ` kernel test robot
2025-04-28 12:28 ` [PATCH v2 5/7] iio: adc: ad4170: Add GPIO controller support Marcelo Schmitt
` (2 subsequent siblings)
6 siblings, 2 replies; 27+ messages in thread
From: Marcelo Schmitt @ 2025-04-28 12:28 UTC (permalink / raw)
To: linux-iio, devicetree, linux-kernel
Cc: jic23, lars, Michael.Hennerich, dlechner, nuno.sa, andy, robh,
krzk+dt, conor+dt, marcelo.schmitt1
The AD4170 chip can use an externally supplied clock at the XTAL2 pin, or
an external crystal connected to the XTAL1 and XTAL2 pins. Alternatively,
the AD4170 can provide it's 16 MHz internal clock at the XTAL2 pin. Extend
the AD4170 driver so it effectively uses the provided external clock, if
any, or supplies it's own clock as a clock provider.
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
changes since v1
- Added support for clock-output-names
drivers/iio/adc/Kconfig | 1 +
drivers/iio/adc/ad4170.c | 141 ++++++++++++++++++++++++++++++++++++++-
2 files changed, 141 insertions(+), 1 deletion(-)
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 9b4787c127fc..60eb79a7975f 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -77,6 +77,7 @@ config AD4170
select REGMAP_SPI
select IIO_BUFFER
select IIO_TRIGGERED_BUFFER
+ select COMMON_CLK
help
Say yes here to build support for Analog Devices AD4170 SPI analog
to digital converters (ADC).
diff --git a/drivers/iio/adc/ad4170.c b/drivers/iio/adc/ad4170.c
index 5fcf1c023ac2..b0c332cb5480 100644
--- a/drivers/iio/adc/ad4170.c
+++ b/drivers/iio/adc/ad4170.c
@@ -7,6 +7,8 @@
#include <linux/bitfield.h>
#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
@@ -48,6 +50,7 @@
#define AD4170_CONFIG_A_REG 0x00
#define AD4170_DATA_24B_REG 0x1E
#define AD4170_PIN_MUXING_REG 0x69
+#define AD4170_CLOCK_CTRL_REG 0x6B
#define AD4170_ADC_CTRL_REG 0x71
#define AD4170_CHAN_EN_REG 0x79
#define AD4170_CHAN_SETUP_REG(x) (0x81 + 4 * (x))
@@ -70,6 +73,9 @@
#define AD4170_PIN_MUXING_DIG_AUX1_CTRL_MSK GENMASK(5, 4)
#define AD4170_PIN_MUXING_SYNC_CTRL_MSK GENMASK(3, 2)
+/* AD4170_CLOCK_CTRL_REG */
+#define AD4170_CLOCK_CTRL_CLOCKSEL_MSK GENMASK(1, 0)
+
/* AD4170_ADC_CTRL_REG */
#define AD4170_ADC_CTRL_MULTI_DATA_REG_SEL_MSK BIT(7)
#define AD4170_ADC_CTRL_CONT_READ_MSK GENMASK(5, 4)
@@ -102,6 +108,12 @@
/* AD4170 register constants */
+/* AD4170_CLOCK_CTRL_REG constants */
+#define AD4170_CLOCK_CTRL_CLOCKSEL_INT 0x0
+#define AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT 0x1
+#define AD4170_CLOCK_CTRL_CLOCKSEL_EXT 0x2
+#define AD4170_CLOCK_CTRL_CLOCKSEL_EXT_XTAL 0x3
+
/* AD4170_CHAN_MAP_REG constants */
#define AD4170_CHAN_MAP_AIN0 0
#define AD4170_CHAN_MAP_AIN1 1
@@ -192,6 +204,7 @@ static const unsigned int ad4170_reg_size[] = {
[AD4170_CONFIG_A_REG] = 1,
[AD4170_DATA_24B_REG] = 3,
[AD4170_PIN_MUXING_REG] = 2,
+ [AD4170_CLOCK_CTRL_REG] = 2,
[AD4170_ADC_CTRL_REG] = 2,
[AD4170_CHAN_EN_REG] = 2,
/*
@@ -259,6 +272,10 @@ enum ad4170_regulator {
AD4170_MAX_SUP
};
+static const char *const ad4170_clk_sel[] = {
+ "ext-clk", "xtal"
+};
+
enum ad4170_int_pin_sel {
AD4170_INT_PIN_SDO,
AD4170_INT_PIN_DIG_AUX1,
@@ -349,6 +366,9 @@ struct ad4170_state {
struct ad4170_chan_info chan_infos[AD4170_MAX_CHANNELS];
struct ad4170_setup_info setup_infos[AD4170_MAX_SETUPS];
u32 mclk_hz;
+ unsigned int clock_ctrl;
+ struct clk *ext_clk;
+ struct clk_hw int_clk_hw;
int pins_fn[AD4170_NUM_ANALOG_PINS];
u32 int_pin_sel;
int sps_tbl[ARRAY_SIZE(ad4170_filt_names)][AD4170_MAX_FS_TBL_SIZE][2];
@@ -1665,13 +1685,132 @@ static int ad4170_parse_channels(struct iio_dev *indio_dev)
return 0;
}
+static struct ad4170_state *clk_hw_to_ad4170(struct clk_hw *hw)
+{
+ return container_of(hw, struct ad4170_state, int_clk_hw);
+}
+
+static unsigned long ad4170_sel_clk(struct ad4170_state *st,
+ unsigned int clk_sel)
+{
+ st->clock_ctrl &= ~AD4170_CLOCK_CTRL_CLOCKSEL_MSK;
+ st->clock_ctrl |= FIELD_PREP(AD4170_CLOCK_CTRL_CLOCKSEL_MSK, clk_sel);
+ return regmap_write(st->regmap, AD4170_CLOCK_CTRL_REG, st->clock_ctrl);
+}
+
+static unsigned long ad4170_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return AD4170_INT_CLOCK_16MHZ;
+}
+
+static int ad4170_clk_output_is_enabled(struct clk_hw *hw)
+{
+ struct ad4170_state *st = clk_hw_to_ad4170(hw);
+ u32 clk_sel;
+
+ clk_sel = FIELD_GET(AD4170_CLOCK_CTRL_CLOCKSEL_MSK, st->clock_ctrl);
+ return clk_sel == AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT;
+}
+
+static int ad4170_clk_output_prepare(struct clk_hw *hw)
+{
+ struct ad4170_state *st = clk_hw_to_ad4170(hw);
+
+ return ad4170_sel_clk(st, AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT);
+}
+
+static void ad4170_clk_output_unprepare(struct clk_hw *hw)
+{
+ struct ad4170_state *st = clk_hw_to_ad4170(hw);
+
+ ad4170_sel_clk(st, AD4170_CLOCK_CTRL_CLOCKSEL_INT);
+}
+
+static const struct clk_ops ad4170_int_clk_ops = {
+ .recalc_rate = ad4170_clk_recalc_rate,
+ .is_enabled = ad4170_clk_output_is_enabled,
+ .prepare = ad4170_clk_output_prepare,
+ .unprepare = ad4170_clk_output_unprepare,
+};
+
+static int ad4170_register_clk_provider(struct iio_dev *indio_dev)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ struct device *dev = indio_dev->dev.parent;
+ struct clk_init_data init = {};
+ int ret;
+
+ if (!IS_ENABLED(CONFIG_COMMON_CLK))
+ return 0;
+
+ if (device_property_read_string(dev, "clock-output-names", &init.name)) {
+ init.name = devm_kasprintf(dev, GFP_KERNEL, "%s-clk",
+ fwnode_get_name(dev_fwnode(dev)));
+ if (!init.name)
+ return -ENOMEM;
+ }
+
+ init.ops = &ad4170_int_clk_ops;
+
+ st->int_clk_hw.init = &init;
+ ret = devm_clk_hw_register(dev, &st->int_clk_hw);
+ if (ret)
+ return ret;
+
+ return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
+ &st->int_clk_hw);
+}
+
+static int ad4170_clock_select(struct iio_dev *indio_dev)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ struct device *dev = &st->spi->dev;
+ int ret;
+
+ st->mclk_hz = AD4170_INT_CLOCK_16MHZ;
+ ret = device_property_match_property_string(dev, "clock-names",
+ ad4170_clk_sel,
+ ARRAY_SIZE(ad4170_clk_sel));
+ if (ret < 0) {
+ /* Use internal clock reference */
+ st->clock_ctrl |= FIELD_PREP(AD4170_CLOCK_CTRL_CLOCKSEL_MSK,
+ AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT);
+ return ad4170_register_clk_provider(indio_dev);
+ }
+
+ /* Use external clock reference */
+ st->ext_clk = devm_clk_get_enabled(dev, ad4170_clk_sel[ret]);
+ if (IS_ERR(st->ext_clk))
+ return dev_err_probe(dev, PTR_ERR(st->ext_clk),
+ "Failed to get external clock\n");
+
+ st->clock_ctrl |= FIELD_PREP(AD4170_CLOCK_CTRL_CLOCKSEL_MSK,
+ AD4170_CLOCK_CTRL_CLOCKSEL_EXT + ret);
+
+ st->mclk_hz = clk_get_rate(st->ext_clk);
+ if (st->mclk_hz < AD4170_EXT_CLOCK_MHZ_MIN ||
+ st->mclk_hz > AD4170_EXT_CLOCK_MHZ_MAX) {
+ return dev_err_probe(dev, -EINVAL,
+ "Invalid external clock frequency %u\n",
+ st->mclk_hz);
+ }
+ return 0;
+}
+
static int ad4170_parse_firmware(struct iio_dev *indio_dev)
{
struct ad4170_state *st = iio_priv(indio_dev);
struct device *dev = &st->spi->dev;
int reg_data, ret, i;
- st->mclk_hz = AD4170_INT_CLOCK_16MHZ;
+ ret = ad4170_clock_select(indio_dev);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to setup device clock\n");
+
+ ret = regmap_write(st->regmap, AD4170_CLOCK_CTRL_REG, st->clock_ctrl);
+ if (ret)
+ return ret;
for (i = 0; i < AD4170_NUM_ANALOG_PINS; i++)
st->pins_fn[i] = AD4170_PIN_UNASIGNED;
--
2.47.2
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v2 4/7] iio: adc: ad4170: Add clock provider support
2025-04-28 12:28 ` [PATCH v2 4/7] iio: adc: ad4170: Add clock provider support Marcelo Schmitt
@ 2025-04-29 22:10 ` Andy Shevchenko
2025-05-06 8:21 ` kernel test robot
1 sibling, 0 replies; 27+ messages in thread
From: Andy Shevchenko @ 2025-04-29 22:10 UTC (permalink / raw)
To: Marcelo Schmitt
Cc: linux-iio, devicetree, linux-kernel, jic23, lars,
Michael.Hennerich, dlechner, nuno.sa, andy, robh, krzk+dt,
conor+dt, marcelo.schmitt1
On Mon, Apr 28, 2025 at 3:28 PM Marcelo Schmitt
<marcelo.schmitt@analog.com> wrote:
>
> The AD4170 chip can use an externally supplied clock at the XTAL2 pin, or
> an external crystal connected to the XTAL1 and XTAL2 pins. Alternatively,
> the AD4170 can provide it's 16 MHz internal clock at the XTAL2 pin. Extend
its
> the AD4170 driver so it effectively uses the provided external clock, if
> any, or supplies it's own clock as a clock provider.
its
...
> +static const char *const ad4170_clk_sel[] = {
> + "ext-clk", "xtal"
Keep trailing comma when it's not a oneliner assignment.
> +};
...
> +static int ad4170_register_clk_provider(struct iio_dev *indio_dev)
> +{
> + struct ad4170_state *st = iio_priv(indio_dev);
> + struct device *dev = indio_dev->dev.parent;
> + struct clk_init_data init = {};
> + int ret;
> +
> + if (!IS_ENABLED(CONFIG_COMMON_CLK))
> + return 0;
> +
> + if (device_property_read_string(dev, "clock-output-names", &init.name)) {
> + init.name = devm_kasprintf(dev, GFP_KERNEL, "%s-clk",
> + fwnode_get_name(dev_fwnode(dev)));
Why not %pfw ?
> + if (!init.name)
> + return -ENOMEM;
> + }
> +
> + init.ops = &ad4170_int_clk_ops;
> +
> + st->int_clk_hw.init = &init;
> + ret = devm_clk_hw_register(dev, &st->int_clk_hw);
> + if (ret)
> + return ret;
> +
> + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
> + &st->int_clk_hw);
> +}
...
> + ret = ad4170_clock_select(indio_dev);
> + if (ret < 0)
Why ' < 0' part?
> + return dev_err_probe(dev, ret, "Failed to setup device clock\n");
> +
> + ret = regmap_write(st->regmap, AD4170_CLOCK_CTRL_REG, st->clock_ctrl);
> + if (ret)
> + return ret;
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH v2 4/7] iio: adc: ad4170: Add clock provider support
2025-04-28 12:28 ` [PATCH v2 4/7] iio: adc: ad4170: Add clock provider support Marcelo Schmitt
2025-04-29 22:10 ` Andy Shevchenko
@ 2025-05-06 8:21 ` kernel test robot
1 sibling, 0 replies; 27+ messages in thread
From: kernel test robot @ 2025-05-06 8:21 UTC (permalink / raw)
To: Marcelo Schmitt, linux-iio, devicetree, linux-kernel
Cc: Paul Gazzillo, Necip Fazil Yildiran, oe-kbuild-all, jic23, lars,
Michael.Hennerich, dlechner, nuno.sa, andy, robh, krzk+dt,
conor+dt, marcelo.schmitt1
Hi Marcelo,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 1c2409fe38d5c19015d69851d15ba543d1911932]
url: https://github.com/intel-lab-lkp/linux/commits/Marcelo-Schmitt/dt-bindings-iio-adc-Add-AD4170/20250428-222010
base: 1c2409fe38d5c19015d69851d15ba543d1911932
patch link: https://lore.kernel.org/r/bede8227189637568f9425cd6848e21be33c2fd2.1745841276.git.marcelo.schmitt%40analog.com
patch subject: [PATCH v2 4/7] iio: adc: ad4170: Add clock provider support
config: sh-kismet-CONFIG_COMMON_CLK-CONFIG_AD4170-0-0 (https://download.01.org/0day-ci/archive/20250506/202505061552.mYM50gr5-lkp@intel.com/config)
reproduce: (https://download.01.org/0day-ci/archive/20250506/202505061552.mYM50gr5-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202505061552.mYM50gr5-lkp@intel.com/
kismet warnings: (new ones prefixed by >>)
>> kismet: WARNING: unmet direct dependencies detected for COMMON_CLK when selected by AD4170
WARNING: unmet direct dependencies detected for COMMON_CLK
Depends on [n]: !HAVE_LEGACY_CLK [=y]
Selected by [y]:
- AD4170 [=y] && IIO [=y] && SPI [=y]
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 5/7] iio: adc: ad4170: Add GPIO controller support
2025-04-28 12:27 [PATCH v2 0/7] iio: adc: Add support for AD4170 series of ADCs Marcelo Schmitt
` (3 preceding siblings ...)
2025-04-28 12:28 ` [PATCH v2 4/7] iio: adc: ad4170: Add clock provider support Marcelo Schmitt
@ 2025-04-28 12:28 ` Marcelo Schmitt
2025-04-29 22:14 ` Andy Shevchenko
2025-05-04 17:50 ` Jonathan Cameron
2025-04-28 12:29 ` [PATCH v2 6/7] iio: adc: ad4170: Add support for internal temperature sensor Marcelo Schmitt
2025-04-28 12:29 ` [PATCH v2 7/7] iio: adc: ad4170: Add support for weigh scale and RTD sensors Marcelo Schmitt
6 siblings, 2 replies; 27+ messages in thread
From: Marcelo Schmitt @ 2025-04-28 12:28 UTC (permalink / raw)
To: linux-iio, devicetree, linux-kernel
Cc: jic23, lars, Michael.Hennerich, dlechner, nuno.sa, andy, robh,
krzk+dt, conor+dt, marcelo.schmitt1
The AD4170 has four multifunctional pins that can be used as GPIOs. The
GPIO functionality can be accessed when the AD4170 chip is not busy
performing continuous data capture or handling any other register
read/write request. Also, the AD4170 does not provide any interrupt based
on GPIO pin states so AD4170 GPIOs can't be used as interrupt sources.
Implement gpio_chip callbacks to make AD4170 GPIO pins controllable through
the gpiochip interface.
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
changes since v1
- Call gpio_set() at begining of gpio_direction_output() instead of at the end of it.
- Return -EPERM if try to set a GPIO configured for input.
- Now locking on state mutex before setting output GPIO values.
- Used gpiochio init_valid_mask() to only init available GPIOs.
drivers/iio/adc/Kconfig | 1 +
drivers/iio/adc/ad4170.c | 191 ++++++++++++++++++++++++++++++++++++++-
2 files changed, 191 insertions(+), 1 deletion(-)
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 60eb79a7975f..ad141bf48679 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -78,6 +78,7 @@ config AD4170
select IIO_BUFFER
select IIO_TRIGGERED_BUFFER
select COMMON_CLK
+ select GPIOLIB
help
Say yes here to build support for Analog Devices AD4170 SPI analog
to digital converters (ADC).
diff --git a/drivers/iio/adc/ad4170.c b/drivers/iio/adc/ad4170.c
index b0c332cb5480..612676c1c88a 100644
--- a/drivers/iio/adc/ad4170.c
+++ b/drivers/iio/adc/ad4170.c
@@ -12,6 +12,7 @@
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
+#include <linux/gpio/driver.h>
#include <linux/iio/buffer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
@@ -61,6 +62,9 @@
#define AD4170_FILTER_FS_REG(x) (0xC7 + 14 * (x))
#define AD4170_OFFSET_REG(x) (0xCA + 14 * (x))
#define AD4170_GAIN_REG(x) (0xCD + 14 * (x))
+#define AD4170_GPIO_MODE_REG 0x191
+#define AD4170_GPIO_OUTPUT_REG 0x193
+#define AD4170_GPIO_INPUT_REG 0x195
#define AD4170_ADC_CTRL_CONT_READ_EXIT_REG 0x200 /* virtual reg */
#define AD4170_REG_READ_MASK BIT(14)
@@ -170,6 +174,7 @@
/* Device properties and auxiliary constants */
#define AD4170_NUM_ANALOG_PINS 9
+#define AD4170_NUM_GPIO_PINS 4
#define AD4170_MAX_CHANNELS 16
#define AD4170_MAX_ANALOG_PINS 8
#define AD4170_MAX_SETUPS 8
@@ -239,6 +244,9 @@ static const unsigned int ad4170_reg_size[] = {
[AD4170_OFFSET_REG(5) ... AD4170_GAIN_REG(5)] = 3,
[AD4170_OFFSET_REG(6) ... AD4170_GAIN_REG(6)] = 3,
[AD4170_OFFSET_REG(7) ... AD4170_GAIN_REG(7)] = 3,
+ [AD4170_GPIO_MODE_REG] = 2,
+ [AD4170_GPIO_OUTPUT_REG] = 2,
+ [AD4170_GPIO_INPUT_REG] = 2,
[AD4170_ADC_CTRL_CONT_READ_EXIT_REG] = 0,
};
@@ -370,6 +378,7 @@ struct ad4170_state {
struct clk *ext_clk;
struct clk_hw int_clk_hw;
int pins_fn[AD4170_NUM_ANALOG_PINS];
+ struct gpio_chip gpiochip;
u32 int_pin_sel;
int sps_tbl[ARRAY_SIZE(ad4170_filt_names)][AD4170_MAX_FS_TBL_SIZE][2];
struct completion completion;
@@ -1525,6 +1534,175 @@ static int ad4170_soft_reset(struct ad4170_state *st)
return 0;
}
+static int ad4170_gpio_get(struct gpio_chip *gc, unsigned int offset)
+{
+ struct iio_dev *indio_dev = gpiochip_get_data(gc);
+ struct ad4170_state *st = iio_priv(indio_dev);
+ unsigned int val;
+ int ret;
+
+ if (!iio_device_claim_direct(indio_dev))
+ return -EBUSY;
+
+ ret = regmap_read(st->regmap, AD4170_GPIO_MODE_REG, &val);
+ if (ret)
+ goto err_release;
+
+ /*
+ * If the GPIO is configured as an input, read the current value from
+ * AD4170_GPIO_INPUT_REG. Otherwise, read the input value from
+ * AD4170_GPIO_OUTPUT_REG.
+ */
+ if (val & BIT(offset * 2))
+ ret = regmap_read(st->regmap, AD4170_GPIO_INPUT_REG, &val);
+ else
+ ret = regmap_read(st->regmap, AD4170_GPIO_OUTPUT_REG, &val);
+ if (ret)
+ goto err_release;
+
+ ret = !!(val & BIT(offset));
+err_release:
+ iio_device_release_direct(indio_dev);
+
+ return ret;
+}
+
+static int ad4170_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
+{
+ struct iio_dev *indio_dev = gpiochip_get_data(gc);
+ struct ad4170_state *st = iio_priv(indio_dev);
+ unsigned int val;
+ int ret;
+
+ if (!iio_device_claim_direct(indio_dev))
+ return -EBUSY;
+
+ guard(mutex)(&st->lock);
+ ret = regmap_read(st->regmap, AD4170_GPIO_MODE_REG, &val);
+ if (ret)
+ goto err_release;
+
+ if (val & BIT(offset * 2 + 1))
+ ret = regmap_update_bits(st->regmap, AD4170_GPIO_OUTPUT_REG,
+ BIT(offset), value << offset);
+ else
+ ret = -EPERM;
+
+err_release:
+ iio_device_release_direct(indio_dev);
+ return ret;
+}
+
+static int ad4170_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
+{
+ struct iio_dev *indio_dev = gpiochip_get_data(gc);
+ struct ad4170_state *st = iio_priv(indio_dev);
+ unsigned int val;
+ int ret;
+
+ if (!iio_device_claim_direct(indio_dev))
+ return -EBUSY;
+
+ ret = regmap_read(st->regmap, AD4170_GPIO_MODE_REG, &val);
+ if (ret)
+ goto err_release;
+
+ if (val & BIT(offset * 2 + 1))
+ ret = GPIO_LINE_DIRECTION_OUT;
+ else
+ ret = GPIO_LINE_DIRECTION_IN;
+
+err_release:
+ iio_device_release_direct(indio_dev);
+
+ return ret;
+}
+
+static int ad4170_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
+{
+ struct iio_dev *indio_dev = gpiochip_get_data(gc);
+ struct ad4170_state *st = iio_priv(indio_dev);
+ int ret;
+
+ if (!iio_device_claim_direct(indio_dev))
+ return -EBUSY;
+
+ ret = regmap_clear_bits(st->regmap, AD4170_GPIO_MODE_REG,
+ BIT(offset * 2 + 1));
+ if (ret)
+ goto err_release;
+
+ ret = regmap_set_bits(st->regmap, AD4170_GPIO_MODE_REG,
+ BIT(offset * 2));
+
+err_release:
+ iio_device_release_direct(indio_dev);
+
+ return ret;
+}
+
+static int ad4170_gpio_direction_output(struct gpio_chip *gc,
+ unsigned int offset, int value)
+{
+ struct iio_dev *indio_dev = gpiochip_get_data(gc);
+ struct ad4170_state *st = iio_priv(indio_dev);
+ int ret;
+
+ ret = ad4170_gpio_set(gc, offset, value);
+ if (ret)
+ return ret;
+
+ if (!iio_device_claim_direct(indio_dev))
+ return -EBUSY;
+
+ ret = regmap_clear_bits(st->regmap, AD4170_GPIO_MODE_REG,
+ BIT(offset * 2));
+ if (ret)
+ goto err_release;
+
+ ret = regmap_set_bits(st->regmap, AD4170_GPIO_MODE_REG,
+ BIT(offset * 2 + 1));
+
+err_release:
+ iio_device_release_direct(indio_dev);
+
+ return ret;
+}
+
+static int ad4170_gpio_init_valid_mask(struct gpio_chip *gc,
+ unsigned long *valid_mask,
+ unsigned int ngpios)
+{
+ struct ad4170_state *st = gpiochip_get_data(gc);
+ unsigned int i;
+
+ /* Only expose GPIOs that were not assigned any other function. */
+ for (i = 0; i < ngpios; i++)
+ __assign_bit(i, valid_mask, st->gpio_fn[i] == AD4170_PIN_UNASIGNED);
+
+ return 0;
+}
+
+static int ad4170_gpio_init(struct iio_dev *indio_dev)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+
+ st->gpiochip.label = "ad4170_gpios";
+ st->gpiochip.base = -1;
+ st->gpiochip.ngpio = AD4170_NUM_GPIO_PINS;
+ st->gpiochip.parent = &st->spi->dev;
+ st->gpiochip.can_sleep = true;
+ st->gpiochip.init_valid_mask = ad4170_gpio_init_valid_mask;
+ st->gpiochip.get_direction = ad4170_gpio_get_direction;
+ st->gpiochip.direction_input = ad4170_gpio_direction_input;
+ st->gpiochip.direction_output = ad4170_gpio_direction_output;
+ st->gpiochip.get = ad4170_gpio_get;
+ st->gpiochip.set_rv = ad4170_gpio_set;
+ st->gpiochip.owner = THIS_MODULE;
+
+ return devm_gpiochip_add_data(&st->spi->dev, &st->gpiochip, indio_dev);
+}
+
static int ad4170_parse_reference(struct ad4170_state *st,
struct fwnode_handle *child,
struct ad4170_setup *setup)
@@ -1833,7 +2011,18 @@ static int ad4170_parse_firmware(struct iio_dev *indio_dev)
if (ret)
return ret;
- return ad4170_parse_channels(indio_dev);
+ ret = ad4170_parse_channels(indio_dev);
+ if (ret)
+ return ret;
+
+ /* Only create a GPIO chip if flagged for it */
+ if (device_property_read_bool(&st->spi->dev, "gpio-controller")) {
+ ret = ad4170_gpio_init(indio_dev);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
}
static int ad4170_initial_config(struct iio_dev *indio_dev)
--
2.47.2
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v2 5/7] iio: adc: ad4170: Add GPIO controller support
2025-04-28 12:28 ` [PATCH v2 5/7] iio: adc: ad4170: Add GPIO controller support Marcelo Schmitt
@ 2025-04-29 22:14 ` Andy Shevchenko
2025-05-04 17:50 ` Jonathan Cameron
1 sibling, 0 replies; 27+ messages in thread
From: Andy Shevchenko @ 2025-04-29 22:14 UTC (permalink / raw)
To: Marcelo Schmitt
Cc: linux-iio, devicetree, linux-kernel, jic23, lars,
Michael.Hennerich, dlechner, nuno.sa, andy, robh, krzk+dt,
conor+dt, marcelo.schmitt1
On Mon, Apr 28, 2025 at 3:29 PM Marcelo Schmitt
<marcelo.schmitt@analog.com> wrote:
>
> The AD4170 has four multifunctional pins that can be used as GPIOs. The
> GPIO functionality can be accessed when the AD4170 chip is not busy
> performing continuous data capture or handling any other register
> read/write request. Also, the AD4170 does not provide any interrupt based
> on GPIO pin states so AD4170 GPIOs can't be used as interrupt sources.
>
> Implement gpio_chip callbacks to make AD4170 GPIO pins controllable through
> the gpiochip interface.
...
> +static int ad4170_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
> +{
> + struct iio_dev *indio_dev = gpiochip_get_data(gc);
> + struct ad4170_state *st = iio_priv(indio_dev);
> + unsigned int val;
> + int ret;
> +
> + if (!iio_device_claim_direct(indio_dev))
> + return -EBUSY;
> +
> + guard(mutex)(&st->lock);
> + ret = regmap_read(st->regmap, AD4170_GPIO_MODE_REG, &val);
> + if (ret)
> + goto err_release;
> +
> + if (val & BIT(offset * 2 + 1))
> + ret = regmap_update_bits(st->regmap, AD4170_GPIO_OUTPUT_REG,
> + BIT(offset), value << offset);
Haven't you seen my previous review (v1)? I asked what if the value is > 1?
I also recommended looking at regmap_assign_bits().
> + else
> + ret = -EPERM;
> +
> +err_release:
> + iio_device_release_direct(indio_dev);
> + return ret;
> +}
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH v2 5/7] iio: adc: ad4170: Add GPIO controller support
2025-04-28 12:28 ` [PATCH v2 5/7] iio: adc: ad4170: Add GPIO controller support Marcelo Schmitt
2025-04-29 22:14 ` Andy Shevchenko
@ 2025-05-04 17:50 ` Jonathan Cameron
1 sibling, 0 replies; 27+ messages in thread
From: Jonathan Cameron @ 2025-05-04 17:50 UTC (permalink / raw)
To: Marcelo Schmitt
Cc: linux-iio, devicetree, linux-kernel, lars, Michael.Hennerich,
dlechner, nuno.sa, andy, robh, krzk+dt, conor+dt,
marcelo.schmitt1
On Mon, 28 Apr 2025 09:28:55 -0300
Marcelo Schmitt <marcelo.schmitt@analog.com> wrote:
> The AD4170 has four multifunctional pins that can be used as GPIOs. The
> GPIO functionality can be accessed when the AD4170 chip is not busy
> performing continuous data capture or handling any other register
> read/write request. Also, the AD4170 does not provide any interrupt based
> on GPIO pin states so AD4170 GPIOs can't be used as interrupt sources.
>
> Implement gpio_chip callbacks to make AD4170 GPIO pins controllable through
> the gpiochip interface.
>
> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
For GPIO controllers, even ones outside of driver/gpio we generally +CC the maintainer
and list. They don't have to comment but that at least gets it on their radar if
we are misusing the GPIO chip infrastructure!
Make sure to do that on v3.
In meantime I didn't look hard, but I'm not immediately seeing why we have to disable
the gpios when switching direction.
Jonathan
>
> +
> +static int ad4170_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
> +{
> + struct iio_dev *indio_dev = gpiochip_get_data(gc);
> + struct ad4170_state *st = iio_priv(indio_dev);
> + int ret;
> +
> + if (!iio_device_claim_direct(indio_dev))
> + return -EBUSY;
> +
> + ret = regmap_clear_bits(st->regmap, AD4170_GPIO_MODE_REG,
> + BIT(offset * 2 + 1));
> + if (ret)
> + goto err_release;
> +
> + ret = regmap_set_bits(st->regmap, AD4170_GPIO_MODE_REG,
> + BIT(offset * 2));
As below. If we have to go via disabled, then we need a comment on why.
> +
> +err_release:
> + iio_device_release_direct(indio_dev);
> +
> + return ret;
> +}
> +
> +static int ad4170_gpio_direction_output(struct gpio_chip *gc,
> + unsigned int offset, int value)
> +{
> + struct iio_dev *indio_dev = gpiochip_get_data(gc);
> + struct ad4170_state *st = iio_priv(indio_dev);
> + int ret;
> +
> + ret = ad4170_gpio_set(gc, offset, value);
> + if (ret)
> + return ret;
> +
> + if (!iio_device_claim_direct(indio_dev))
> + return -EBUSY;
> +
> + ret = regmap_clear_bits(st->regmap, AD4170_GPIO_MODE_REG,
> + BIT(offset * 2));
This is odd enough that if required it needs a comment.
I suspect you can just directly update both bits in one write though
and this should be a regmap_update_bits() setting the two bit
field to the value 2 which is output (vs 1 which is input).
> + if (ret)
> + goto err_release;
> +
> + ret = regmap_set_bits(st->regmap, AD4170_GPIO_MODE_REG,
> + BIT(offset * 2 + 1));
> +
> +err_release:
> + iio_device_release_direct(indio_dev);
> +
> + return ret;
> +}
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 6/7] iio: adc: ad4170: Add support for internal temperature sensor
2025-04-28 12:27 [PATCH v2 0/7] iio: adc: Add support for AD4170 series of ADCs Marcelo Schmitt
` (4 preceding siblings ...)
2025-04-28 12:28 ` [PATCH v2 5/7] iio: adc: ad4170: Add GPIO controller support Marcelo Schmitt
@ 2025-04-28 12:29 ` Marcelo Schmitt
2025-04-29 22:16 ` Andy Shevchenko
2025-05-04 17:44 ` Jonathan Cameron
2025-04-28 12:29 ` [PATCH v2 7/7] iio: adc: ad4170: Add support for weigh scale and RTD sensors Marcelo Schmitt
6 siblings, 2 replies; 27+ messages in thread
From: Marcelo Schmitt @ 2025-04-28 12:29 UTC (permalink / raw)
To: linux-iio, devicetree, linux-kernel
Cc: jic23, lars, Michael.Hennerich, dlechner, nuno.sa, andy, robh,
krzk+dt, conor+dt, marcelo.schmitt1
The AD4170 has an internal temperature sensor that can be read using the
ADC. Whenever possible, configure an IIO channel to provide the chip's
temperature.
Reviewed-by: Nuno Sá <nuno.sa@analog.com>
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
changes since v1:
- Dropped a unneeded comment
- Collected review tag
drivers/iio/adc/ad4170.c | 72 ++++++++++++++++++++++++++++++++++++++--
1 file changed, 69 insertions(+), 3 deletions(-)
diff --git a/drivers/iio/adc/ad4170.c b/drivers/iio/adc/ad4170.c
index 612676c1c88a..335b4194c7eb 100644
--- a/drivers/iio/adc/ad4170.c
+++ b/drivers/iio/adc/ad4170.c
@@ -891,6 +891,27 @@ static const struct iio_chan_spec ad4170_channel_template = {
},
};
+static const struct iio_chan_spec ad4170_temp_channel_template = {
+ .type = IIO_TEMP,
+ .indexed = 0,
+ .channel = 17,
+ .channel2 = 17,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
+ BIT(IIO_CHAN_INFO_SCALE) |
+ BIT(IIO_CHAN_INFO_OFFSET) |
+ BIT(IIO_CHAN_INFO_CALIBSCALE) |
+ BIT(IIO_CHAN_INFO_CALIBBIAS) |
+ BIT(IIO_CHAN_INFO_SAMP_FREQ),
+ .info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
+ .scan_type = {
+ .sign = 's',
+ .realbits = 24,
+ .storagebits = 32,
+ .shift = 8,
+ .endianness = IIO_BE,
+ },
+};
+
/*
* Receives the number of a multiplexed AD4170 input (ain_n), and stores the
* voltage (in µV) of the specified input into ain_voltage. If the input number
@@ -1189,9 +1210,27 @@ static int ad4170_read_raw(struct iio_dev *indio_dev,
return ret;
case IIO_CHAN_INFO_SCALE:
pga = FIELD_GET(AD4170_AFE_PGA_GAIN_MSK, setup->afe);
- *val = chan_info->scale_tbl[pga][0];
- *val2 = chan_info->scale_tbl[pga][1];
- return IIO_VAL_INT_PLUS_NANO;
+ switch (chan->type) {
+ case IIO_VOLTAGE:
+ *val = chan_info->scale_tbl[pga][0];
+ *val2 = chan_info->scale_tbl[pga][1];
+ return IIO_VAL_INT_PLUS_NANO;
+
+ case IIO_TEMP:
+ /*
+ * The scale_tbl converts output codes to mV units so
+ * multiply by MILLI to make the factor convert to µV.
+ * Then, apply the temperature sensor change sensitivity
+ * of 477 μV/K. Finally, multiply the result by MILLI
+ * again to comply with milli degrees Celsius IIO ABI.
+ */
+ *val = 0;
+ *val2 = DIV_ROUND_CLOSEST(chan_info->scale_tbl[pga][1] * MILLI,
+ 477) * MILLI;
+ return IIO_VAL_INT_PLUS_NANO;
+ default:
+ return -EINVAL;
+ }
case IIO_CHAN_INFO_OFFSET:
pga = FIELD_GET(AD4170_AFE_PGA_GAIN_MSK, setup->afe);
*val = chan_info->offset_tbl[pga];
@@ -1852,12 +1891,39 @@ static int ad4170_parse_channels(struct iio_dev *indio_dev)
if (num_channels > AD4170_MAX_CHANNELS)
return dev_err_probe(dev, -EINVAL, "Too many channels\n");
+ /* Add one for temperature */
+ num_channels = min(num_channels + 1, AD4170_MAX_CHANNELS);
+
device_for_each_child_node_scoped(dev, child) {
ret = ad4170_parse_channel_node(indio_dev, child, chan_num++);
if (ret)
return ret;
}
+ /*
+ * Add internal temperature sensor channel if the maximum number of
+ * channels has not been reached.
+ */
+ if (num_channels < AD4170_MAX_CHANNELS) {
+ struct ad4170_setup *setup = &st->chan_infos[chan_num].setup;
+
+ st->chans[chan_num] = ad4170_temp_channel_template;
+ st->chans[chan_num].address = chan_num;
+ st->chans[chan_num].scan_index = chan_num;
+
+ st->chan_infos[chan_num].setup_num = AD4170_INVALID_SETUP;
+ st->chan_infos[chan_num].initialized = true;
+
+ setup->afe |= FIELD_PREP(AD4170_AFE_REF_SELECT_MSK,
+ AD4170_REF_AVDD);
+
+ ret = ad4170_get_input_range(st, &st->chans[chan_num], chan_num,
+ AD4170_REF_AVDD);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Invalid input config\n");
+
+ st->chan_infos[chan_num].input_range_uv = ret;
+ }
indio_dev->num_channels = num_channels;
indio_dev->channels = st->chans;
return 0;
--
2.47.2
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v2 6/7] iio: adc: ad4170: Add support for internal temperature sensor
2025-04-28 12:29 ` [PATCH v2 6/7] iio: adc: ad4170: Add support for internal temperature sensor Marcelo Schmitt
@ 2025-04-29 22:16 ` Andy Shevchenko
2025-05-04 17:44 ` Jonathan Cameron
1 sibling, 0 replies; 27+ messages in thread
From: Andy Shevchenko @ 2025-04-29 22:16 UTC (permalink / raw)
To: Marcelo Schmitt
Cc: linux-iio, devicetree, linux-kernel, jic23, lars,
Michael.Hennerich, dlechner, nuno.sa, andy, robh, krzk+dt,
conor+dt, marcelo.schmitt1
On Mon, Apr 28, 2025 at 3:29 PM Marcelo Schmitt
<marcelo.schmitt@analog.com> wrote:
>
> The AD4170 has an internal temperature sensor that can be read using the
> ADC. Whenever possible, configure an IIO channel to provide the chip's
> temperature.
...
> + case IIO_TEMP:
> + /*
> + * The scale_tbl converts output codes to mV units so
> + * multiply by MILLI to make the factor convert to µV.
> + * Then, apply the temperature sensor change sensitivity
> + * of 477 μV/K. Finally, multiply the result by MILLI
> + * again to comply with milli degrees Celsius IIO ABI.
> + */
> + *val = 0;
> + *val2 = DIV_ROUND_CLOSEST(chan_info->scale_tbl[pga][1] * MILLI,
> + 477) * MILLI;
Do not wrap lines like this. Use a logical approach, i.e. the '477) *'
part should be on the previous line.
> + return IIO_VAL_INT_PLUS_NANO;
> + default:
> + return -EINVAL;
> + }
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 6/7] iio: adc: ad4170: Add support for internal temperature sensor
2025-04-28 12:29 ` [PATCH v2 6/7] iio: adc: ad4170: Add support for internal temperature sensor Marcelo Schmitt
2025-04-29 22:16 ` Andy Shevchenko
@ 2025-05-04 17:44 ` Jonathan Cameron
1 sibling, 0 replies; 27+ messages in thread
From: Jonathan Cameron @ 2025-05-04 17:44 UTC (permalink / raw)
To: Marcelo Schmitt
Cc: linux-iio, devicetree, linux-kernel, lars, Michael.Hennerich,
dlechner, nuno.sa, andy, robh, krzk+dt, conor+dt,
marcelo.schmitt1
On Mon, 28 Apr 2025 09:29:12 -0300
Marcelo Schmitt <marcelo.schmitt@analog.com> wrote:
> The AD4170 has an internal temperature sensor that can be read using the
> ADC. Whenever possible, configure an IIO channel to provide the chip's
> temperature.
>
> Reviewed-by: Nuno Sá <nuno.sa@analog.com>
> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
One trivial comment below.
I don't mind that much given you already did it this way though.
> /*
> * Receives the number of a multiplexed AD4170 input (ain_n), and stores the
> * voltage (in µV) of the specified input into ain_voltage. If the input number
> @@ -1189,9 +1210,27 @@ static int ad4170_read_raw(struct iio_dev *indio_dev,
> return ret;
> case IIO_CHAN_INFO_SCALE:
> pga = FIELD_GET(AD4170_AFE_PGA_GAIN_MSK, setup->afe);
> - *val = chan_info->scale_tbl[pga][0];
> - *val2 = chan_info->scale_tbl[pga][1];
> - return IIO_VAL_INT_PLUS_NANO;
> + switch (chan->type) {
> + case IIO_VOLTAGE:
When you know you are going to have changes like this in later patches
in the same posted series it is fine to make the diff smaller by
using a switch from the start.
Occasionally you'll get a comment from someone like me who can't
hold the whole set in my head and misses that is what is going on.
Just reply to say it was diff minimization and likely no one will ever
mind!
> + *val = chan_info->scale_tbl[pga][0];
> + *val2 = chan_info->scale_tbl[pga][1];
> + return IIO_VAL_INT_PLUS_NANO;
> +
> + case IIO_TEMP:
> + /*
> + * The scale_tbl converts output codes to mV units so
> + * multiply by MILLI to make the factor convert to µV.
> + * Then, apply the temperature sensor change sensitivity
> + * of 477 μV/K. Finally, multiply the result by MILLI
> + * again to comply with milli degrees Celsius IIO ABI.
> + */
> + *val = 0;
> + *val2 = DIV_ROUND_CLOSEST(chan_info->scale_tbl[pga][1] * MILLI,
> + 477) * MILLI;
> + return IIO_VAL_INT_PLUS_NANO;
> + default:
> + return -EINVAL;
> + }
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 7/7] iio: adc: ad4170: Add support for weigh scale and RTD sensors
2025-04-28 12:27 [PATCH v2 0/7] iio: adc: Add support for AD4170 series of ADCs Marcelo Schmitt
` (5 preceding siblings ...)
2025-04-28 12:29 ` [PATCH v2 6/7] iio: adc: ad4170: Add support for internal temperature sensor Marcelo Schmitt
@ 2025-04-28 12:29 ` Marcelo Schmitt
2025-04-29 22:26 ` Andy Shevchenko
` (2 more replies)
6 siblings, 3 replies; 27+ messages in thread
From: Marcelo Schmitt @ 2025-04-28 12:29 UTC (permalink / raw)
To: linux-iio, devicetree, linux-kernel
Cc: jic23, lars, Michael.Hennerich, dlechner, nuno.sa, andy, robh,
krzk+dt, conor+dt, marcelo.schmitt1
The AD4170 design has features to aid interfacing with weigh scale and RTD
sensors that are expected to be setup with external circuitry for proper
sensor operation. A key characteristic of those sensors is that the circuit
they are in must be excited with a pair of signals. The external circuit
can be excited either by voltage supply or by AD4170 excitation signals.
The sensor can then be read through a different pair of lines that are
connected to AD4170 ADC.
Configure AD4170 to handle external circuit sensors.
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
changes since v1:
- Improved to support more than one external sensor connected.
drivers/iio/adc/ad4170.c | 375 ++++++++++++++++++++++++++++++++++++++-
1 file changed, 372 insertions(+), 3 deletions(-)
diff --git a/drivers/iio/adc/ad4170.c b/drivers/iio/adc/ad4170.c
index 335b4194c7eb..9e4a9b524dd4 100644
--- a/drivers/iio/adc/ad4170.c
+++ b/drivers/iio/adc/ad4170.c
@@ -62,6 +62,8 @@
#define AD4170_FILTER_FS_REG(x) (0xC7 + 14 * (x))
#define AD4170_OFFSET_REG(x) (0xCA + 14 * (x))
#define AD4170_GAIN_REG(x) (0xCD + 14 * (x))
+#define AD4170_V_BIAS_REG 0x135
+#define AD4170_CURRENT_SRC_REG(x) (0x139 + 2 * (x))
#define AD4170_GPIO_MODE_REG 0x191
#define AD4170_GPIO_OUTPUT_REG 0x193
#define AD4170_GPIO_INPUT_REG 0x195
@@ -110,6 +112,10 @@
/* AD4170_FILTER_REG */
#define AD4170_FILTER_FILTER_TYPE_MSK GENMASK(3, 0)
+/* AD4170_CURRENT_SRC_REG */
+#define AD4170_CURRENT_SRC_I_OUT_PIN_MSK GENMASK(12, 8)
+#define AD4170_CURRENT_SRC_I_OUT_VAL_MSK GENMASK(2, 0)
+
/* AD4170 register constants */
/* AD4170_CLOCK_CTRL_REG constants */
@@ -171,6 +177,21 @@
#define AD4170_FILTER_FILTER_TYPE_SINC5 0x4
#define AD4170_FILTER_FILTER_TYPE_SINC3 0x6
+/* AD4170_CURRENT_SRC_REG constants */
+#define AD4170_CURRENT_SRC_I_OUT_PIN_AIN0 0
+#define AD4170_CURRENT_SRC_I_OUT_PIN_AIN1 1
+#define AD4170_CURRENT_SRC_I_OUT_PIN_AIN2 2
+#define AD4170_CURRENT_SRC_I_OUT_PIN_AIN3 3
+#define AD4170_CURRENT_SRC_I_OUT_PIN_AIN4 4
+#define AD4170_CURRENT_SRC_I_OUT_PIN_AIN5 5
+#define AD4170_CURRENT_SRC_I_OUT_PIN_AIN6 6
+#define AD4170_CURRENT_SRC_I_OUT_PIN_AIN7 7
+#define AD4170_CURRENT_SRC_I_OUT_PIN_AIN8 8
+#define AD4170_CURRENT_SRC_I_OUT_PIN_GPIO0 17
+#define AD4170_CURRENT_SRC_I_OUT_PIN_GPIO1 18
+#define AD4170_CURRENT_SRC_I_OUT_PIN_GPIO2 19
+#define AD4170_CURRENT_SRC_I_OUT_PIN_GPIO3 20
+
/* Device properties and auxiliary constants */
#define AD4170_NUM_ANALOG_PINS 9
@@ -204,6 +225,15 @@
#define AD4170_PIN_UNASIGNED 0x00
#define AD4170_PIN_ANALOG_IN 0x01
#define AD4170_PIN_CURRENT_OUT 0x02
+#define AD4170_PIN_VBIAS 0x04
+
+/* GPIO pin functions */
+#define AD4170_GPIO_UNASIGNED 0x00
+#define AD4170_GPIO_AC_EXCITATION 0x02
+#define AD4170_GPIO_OUTPUT 0x04
+
+/* Current source */
+#define AD4170_CURRENT_SRC_DISABLED 0xFF
static const unsigned int ad4170_reg_size[] = {
[AD4170_CONFIG_A_REG] = 1,
@@ -244,6 +274,8 @@ static const unsigned int ad4170_reg_size[] = {
[AD4170_OFFSET_REG(5) ... AD4170_GAIN_REG(5)] = 3,
[AD4170_OFFSET_REG(6) ... AD4170_GAIN_REG(6)] = 3,
[AD4170_OFFSET_REG(7) ... AD4170_GAIN_REG(7)] = 3,
+ [AD4170_V_BIAS_REG] = 2,
+ [AD4170_CURRENT_SRC_REG(0) ... AD4170_CURRENT_SRC_REG(3)] = 2,
[AD4170_GPIO_MODE_REG] = 2,
[AD4170_GPIO_OUTPUT_REG] = 2,
[AD4170_GPIO_INPUT_REG] = 2,
@@ -305,6 +337,33 @@ static const unsigned int ad4170_sinc5_filt_fs_tbl[] = {
1, 2, 4, 8, 12, 16, 20, 40, 48, 80, 100, 256,
};
+static const unsigned int ad4170_iout_pin_tbl[] = {
+ AD4170_CURRENT_SRC_I_OUT_PIN_AIN0,
+ AD4170_CURRENT_SRC_I_OUT_PIN_AIN1,
+ AD4170_CURRENT_SRC_I_OUT_PIN_AIN2,
+ AD4170_CURRENT_SRC_I_OUT_PIN_AIN3,
+ AD4170_CURRENT_SRC_I_OUT_PIN_AIN4,
+ AD4170_CURRENT_SRC_I_OUT_PIN_AIN5,
+ AD4170_CURRENT_SRC_I_OUT_PIN_AIN6,
+ AD4170_CURRENT_SRC_I_OUT_PIN_AIN7,
+ AD4170_CURRENT_SRC_I_OUT_PIN_AIN8,
+ AD4170_CURRENT_SRC_I_OUT_PIN_GPIO0,
+ AD4170_CURRENT_SRC_I_OUT_PIN_GPIO1,
+ AD4170_CURRENT_SRC_I_OUT_PIN_GPIO2,
+ AD4170_CURRENT_SRC_I_OUT_PIN_GPIO3,
+};
+
+static const unsigned int ad4170_iout_current_ua_tbl[] = {
+ 0, 10, 50, 100, 250, 500, 1000, 1500
+};
+
+enum ad4170_sensor_type {
+ AD4170_WEIGH_SCALE_SENSOR = 0,
+ AD4170_RTD_SENSOR = 1,
+ AD4170_THERMOCOUPLE_SENSOR = 2,
+ AD4170_ADC_SENSOR = 3,
+};
+
struct ad4170_chip_info {
const char *name;
};
@@ -378,6 +437,8 @@ struct ad4170_state {
struct clk *ext_clk;
struct clk_hw int_clk_hw;
int pins_fn[AD4170_NUM_ANALOG_PINS];
+ int gpio_fn[AD4170_NUM_GPIO_PINS];
+ unsigned int cur_src_pins[AD4170_NUM_CURRENT_SRC];
struct gpio_chip gpiochip;
u32 int_pin_sel;
int sps_tbl[ARRAY_SIZE(ad4170_filt_names)][AD4170_MAX_FS_TBL_SIZE][2];
@@ -925,6 +986,19 @@ static int ad4170_get_ain_voltage_uv(struct ad4170_state *st, int ain_n,
struct device *dev = &st->spi->dev;
*ain_voltage = 0;
+ /*
+ * The voltage bias (vbias) sets the common-mode voltage of the channel
+ * to (AVDD + AVSS)/2. If provided, AVSS supply provides the magnitude
+ * (absolute value) of the negative voltage supplied to the AVSS pin.
+ * So, we do AVDD - AVSS to compute the DC voltage generated by the bias
+ * voltage generator.
+ */
+ if (st->pins_fn[ain_n] & AD4170_PIN_VBIAS) {
+ *ain_voltage = (st->vrefs_uv[AD4170_AVDD_SUP]
+ - st->vrefs_uv[AD4170_AVSS_SUP]) / 2;
+ return 0;
+ }
+
if (ain_n <= AD4170_CHAN_MAP_TEMP_SENSOR)
return 0;
@@ -1742,6 +1816,266 @@ static int ad4170_gpio_init(struct iio_dev *indio_dev)
return devm_gpiochip_add_data(&st->spi->dev, &st->gpiochip, indio_dev);
}
+static int _ad4170_find_table_index(const unsigned int *tbl, size_t len,
+ unsigned int val)
+{
+ unsigned int i;
+
+ for (i = 0; i < len; i++)
+ if (tbl[i] == val)
+ return i;
+
+ return -EINVAL;
+}
+
+#define ad4170_find_table_index(table, val) \
+ _ad4170_find_table_index(table, ARRAY_SIZE(table), val)
+
+static int ad4170_validate_excitation_pins(struct ad4170_state *st,
+ u32 *exc_pins, int num_exc_pins)
+{
+ struct device *dev = &st->spi->dev;
+ int ret, i;
+
+ for (i = 0; i < num_exc_pins; i++) {
+ unsigned int pin = exc_pins[i];
+
+ ret = ad4170_find_table_index(ad4170_iout_pin_tbl, pin);
+ if (ret < 0)
+ return dev_err_probe(dev, ret,
+ "Invalid excitation pin: %u\n",
+ pin);
+
+ if (pin <= AD4170_MAX_ANALOG_PINS) {
+ if (st->pins_fn[pin] != AD4170_PIN_UNASIGNED)
+ return dev_err_probe(dev, -EINVAL,
+ "Pin %u already used with fn %u\n",
+ pin, st->pins_fn[pin]);
+
+ st->pins_fn[pin] |= AD4170_PIN_CURRENT_OUT;
+ } else {
+ unsigned int gpio = pin - AD4170_CURRENT_SRC_I_OUT_PIN_GPIO0;
+
+ if (st->gpio_fn[gpio] != AD4170_GPIO_UNASIGNED)
+ return dev_err_probe(dev, -EINVAL,
+ "GPIO %u already used with fn %u\n",
+ gpio, st->gpio_fn[gpio]);
+
+ st->gpio_fn[gpio] |= AD4170_GPIO_AC_EXCITATION;
+ }
+ }
+ return 0;
+}
+
+static int ad4170_setup_current_src(struct ad4170_state *st,
+ struct fwnode_handle *child,
+ struct ad4170_setup *setup, u32 *exc_pins,
+ int num_exc_pins, int exc_cur, bool ac_excited)
+{
+ unsigned int current_src, i, j;
+ int ret;
+
+ for (i = 0; i < num_exc_pins; i++) {
+ unsigned int pin = exc_pins[i];
+
+ current_src |= FIELD_PREP(AD4170_CURRENT_SRC_I_OUT_PIN_MSK, pin);
+ current_src |= FIELD_PREP(AD4170_CURRENT_SRC_I_OUT_VAL_MSK, exc_cur);
+
+ for (j = 0; j < AD4170_NUM_CURRENT_SRC; j++) {
+ /*
+ * Excitation current chopping is configured in pairs.
+ * If current chopping configured and the first end of
+ * the current source pair has already been assigned,
+ * skip to the next pair of output currents.
+ */
+ if (ac_excited && j % 2 != 0)
+ continue;
+
+ if (st->cur_src_pins[j] == AD4170_CURRENT_SRC_DISABLED) {
+ st->cur_src_pins[j] = pin;
+ break;
+ }
+ }
+ if (j == AD4170_NUM_CURRENT_SRC)
+ return dev_err_probe(&st->spi->dev, -EINVAL,
+ "Failed to setup IOUT at pin %u\n",
+ pin);
+
+ ret = regmap_write(st->regmap, AD4170_CURRENT_SRC_REG(j),
+ current_src);
+ if (ret)
+ return ret;
+ }
+
+ if (ac_excited && num_exc_pins > 1) {
+ unsigned int exc_cur_pair;
+
+ if (st->cur_src_pins[0] == exc_pins[0])
+ exc_cur_pair = 1;
+ else
+ exc_cur_pair = 2;
+
+ /*
+ * Configure excitation currents chopping.
+ * Chop two pairs if using four excitation currents.
+ */
+ setup->misc |= FIELD_PREP(AD4170_MISC_CHOP_IEXC_MSK,
+ num_exc_pins == 2 ? exc_cur_pair : 3);
+ }
+
+ return 0;
+}
+
+static int ad4170_setup_bridge(struct ad4170_state *st,
+ struct fwnode_handle *child,
+ struct ad4170_setup *setup, u32 *exc_pins,
+ int num_exc_pins, int exc_cur, bool ac_excited)
+{
+ int ret;
+
+ /*
+ * If a specific current is provided through
+ * adi,excitation-current-microamp, set excitation pins provided through
+ * adi,excitation-pins to AC excite the bridge circuit. Else, use
+ * predefined ACX1, ACX1 negated, ACX2, ACX2 negated signals to AC
+ * excite the bridge. Those signals are output on GPIO2, GPIO0, GPIO3,
+ * and GPIO1, respectively. If only two pins are specified for AC
+ * excitation, use ACX1 and ACX2.
+ *
+ * Also, to avoid any short-circuit condition when more than one channel
+ * is enabled, set GPIO2 and GPIO0 high, and set GPIO1 and GPIO3 low to
+ * DC excite the bridge whenever a channel without AC excitation is
+ * selected. That is needed because GPIO pins are controlled by the next
+ * highest priority GPIO function when a channel doesn't enable AC
+ * excitation. See datasheet Figure 113 Weigh Scale (AC Excitation) for
+ * an example circuit diagram.
+ */
+ if (exc_cur == 0 && ac_excited) {
+ if (num_exc_pins == 2) {
+ setup->misc |= FIELD_PREP(AD4170_MISC_CHOP_ADC_MSK, 0x3);
+ ret = regmap_set_bits(st->regmap,
+ AD4170_GPIO_MODE_REG,
+ BIT(7) | BIT(5));
+ if (ret)
+ return ret;
+
+ ret = regmap_set_bits(st->regmap,
+ AD4170_GPIO_OUTPUT_REG,
+ BIT(3) | BIT(2));
+ if (ret)
+ return ret;
+
+ st->gpio_fn[3] |= AD4170_GPIO_OUTPUT;
+ st->gpio_fn[2] |= AD4170_GPIO_OUTPUT;
+ } else {
+ setup->misc |= FIELD_PREP(AD4170_MISC_CHOP_ADC_MSK, 0x2);
+ ret = regmap_set_bits(st->regmap,
+ AD4170_GPIO_MODE_REG,
+ BIT(7) | BIT(5) | BIT(3) | BIT(1));
+ if (ret)
+ return ret;
+
+ ret = regmap_set_bits(st->regmap,
+ AD4170_GPIO_OUTPUT_REG,
+ BIT(3) | BIT(2) | BIT(1) | BIT(0));
+ if (ret)
+ return ret;
+
+ st->gpio_fn[3] |= AD4170_GPIO_OUTPUT;
+ st->gpio_fn[2] |= AD4170_GPIO_OUTPUT;
+ st->gpio_fn[1] |= AD4170_GPIO_OUTPUT;
+ st->gpio_fn[0] |= AD4170_GPIO_OUTPUT;
+ }
+
+ return 0;
+ }
+
+ return ad4170_setup_current_src(st, child, setup, exc_pins,
+ num_exc_pins, exc_cur, ac_excited);
+}
+
+static int ad4170_setup_rtd(struct ad4170_state *st,
+ struct fwnode_handle *child,
+ struct ad4170_setup *setup, u32 *exc_pins,
+ int num_exc_pins, int exc_cur, bool ac_excited)
+{
+ return ad4170_setup_current_src(st, child, setup, exc_pins,
+ num_exc_pins, exc_cur, ac_excited);
+}
+
+static int ad4170_parse_external_sensor(struct ad4170_state *st,
+ struct fwnode_handle *child,
+ struct ad4170_setup *setup,
+ struct iio_chan_spec *chan, u8 s_type)
+{
+ unsigned int num_exc_pins, exc_cur, reg_val;
+ struct device *dev = &st->spi->dev;
+ u32 pins[2], exc_pins[4];
+ bool ac_excited, vbias;
+ int ret;
+
+ ret = fwnode_property_read_u32_array(child, "diff-channels", pins,
+ ARRAY_SIZE(pins));
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to read sensor diff-channels\n");
+
+ chan->differential = true;
+ chan->channel = pins[0];
+ chan->channel2 = pins[1];
+
+ ac_excited = fwnode_property_read_bool(child, "adi,excitation-ac");
+
+ num_exc_pins = fwnode_property_count_u32(child, "adi,excitation-pins");
+ if (num_exc_pins != 1 && num_exc_pins != 2 && num_exc_pins != 4)
+ return dev_err_probe(dev, -EINVAL,
+ "Invalid number of excitation pins\n");
+
+ ret = fwnode_property_read_u32_array(child, "adi,excitation-pins",
+ exc_pins, num_exc_pins);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to read adi,excitation-pins\n");
+
+ ret = ad4170_validate_excitation_pins(st, exc_pins, num_exc_pins);
+ if (ret)
+ return ret;
+
+ exc_cur = 0;
+ ret = fwnode_property_read_u32(child, "adi,excitation-current-microamp",
+ &exc_cur);
+ if (ret && s_type == AD4170_RTD_SENSOR)
+ return dev_err_probe(dev, ret,
+ "Failed to read adi,excitation-current-microamp\n");
+
+ ret = ad4170_find_table_index(ad4170_iout_current_ua_tbl, exc_cur);
+ if (ret < 0)
+ return dev_err_probe(dev, ret,
+ "Invalid excitation current: %uuA\n",
+ exc_cur);
+
+ /* Get the excitation current configuration value */
+ exc_cur = ret;
+
+ if (s_type == AD4170_THERMOCOUPLE_SENSOR) {
+ vbias = fwnode_property_read_bool(child, "adi,vbias");
+ if (vbias) {
+ st->pins_fn[chan->channel2] |= AD4170_PIN_VBIAS;
+ reg_val = BIT(chan->channel2);
+ return regmap_write(st->regmap, AD4170_V_BIAS_REG,
+ reg_val);
+ }
+ }
+ if (s_type == AD4170_WEIGH_SCALE_SENSOR) {
+ ret = ad4170_setup_bridge(st, child, setup, exc_pins,
+ num_exc_pins, exc_cur, ac_excited);
+ } else {
+ ret = ad4170_setup_rtd(st, child, setup, exc_pins, num_exc_pins,
+ exc_cur, ac_excited);
+ }
+ return ret;
+}
+
static int ad4170_parse_reference(struct ad4170_state *st,
struct fwnode_handle *child,
struct ad4170_setup *setup)
@@ -1823,6 +2157,7 @@ static int ad4170_parse_channel_node(struct iio_dev *indio_dev,
struct ad4170_state *st = iio_priv(indio_dev);
struct device *dev = &st->spi->dev;
struct ad4170_chan_info *chan_info;
+ u8 s_type = AD4170_ADC_SENSOR;
struct ad4170_setup *setup;
struct iio_chan_spec *chan;
unsigned int ch_reg;
@@ -1854,10 +2189,34 @@ static int ad4170_parse_channel_node(struct iio_dev *indio_dev,
if (ret)
return ret;
- ret = ad4170_parse_adc_channel_type(dev, child, chan);
- if (ret < 0)
- return ret;
+ ret = fwnode_property_read_u8(child, "adi,sensor-type", &s_type);
+ if (!ret) {
+ if (s_type > AD4170_THERMOCOUPLE_SENSOR)
+ return dev_err_probe(dev, ret,
+ "Invalid adi,sensor-type: %u\n",
+ s_type);
+ }
+ switch (s_type) {
+ case AD4170_ADC_SENSOR:
+ ret = ad4170_parse_adc_channel_type(dev, child, chan);
+ if (ret < 0)
+ return ret;
+
+ break;
+ case AD4170_WEIGH_SCALE_SENSOR:
+ fallthrough;
+ case AD4170_THERMOCOUPLE_SENSOR:
+ fallthrough;
+ case AD4170_RTD_SENSOR:
+ ret = ad4170_parse_external_sensor(st, child, setup, chan,
+ s_type);
+ if (ret < 0)
+ return ret;
+ break;
+ default:
+ return -EINVAL;
+ }
bipolar = fwnode_property_read_bool(child, "bipolar");
setup->afe |= FIELD_PREP(AD4170_AFE_BIPOLAR_MSK, bipolar);
if (bipolar)
@@ -2059,6 +2418,12 @@ static int ad4170_parse_firmware(struct iio_dev *indio_dev)
for (i = 0; i < AD4170_NUM_ANALOG_PINS; i++)
st->pins_fn[i] = AD4170_PIN_UNASIGNED;
+ for (i = 0; i < AD4170_NUM_GPIO_PINS; i++)
+ st->gpio_fn[i] = AD4170_GPIO_UNASIGNED;
+
+ for (i = 0; i < AD4170_NUM_CURRENT_SRC; i++)
+ st->cur_src_pins[i] = AD4170_CURRENT_SRC_DISABLED;
+
/* On power on, device defaults to using SDO pin for data ready signal */
st->int_pin_sel = AD4170_INT_PIN_SDO;
ret = device_property_match_property_string(dev, "interrupt-names",
@@ -2083,6 +2448,10 @@ static int ad4170_parse_firmware(struct iio_dev *indio_dev)
/* Only create a GPIO chip if flagged for it */
if (device_property_read_bool(&st->spi->dev, "gpio-controller")) {
+ for (i = 0; i < AD4170_NUM_GPIO_PINS; i++)
+ if (st->gpio_fn[i] != AD4170_GPIO_UNASIGNED)
+ return 0;
+
ret = ad4170_gpio_init(indio_dev);
if (ret)
return ret;
--
2.47.2
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v2 7/7] iio: adc: ad4170: Add support for weigh scale and RTD sensors
2025-04-28 12:29 ` [PATCH v2 7/7] iio: adc: ad4170: Add support for weigh scale and RTD sensors Marcelo Schmitt
@ 2025-04-29 22:26 ` Andy Shevchenko
2025-05-01 19:50 ` kernel test robot
2025-05-04 17:42 ` Jonathan Cameron
2 siblings, 0 replies; 27+ messages in thread
From: Andy Shevchenko @ 2025-04-29 22:26 UTC (permalink / raw)
To: Marcelo Schmitt
Cc: linux-iio, devicetree, linux-kernel, jic23, lars,
Michael.Hennerich, dlechner, nuno.sa, andy, robh, krzk+dt,
conor+dt, marcelo.schmitt1
On Mon, Apr 28, 2025 at 3:30 PM Marcelo Schmitt
<marcelo.schmitt@analog.com> wrote:
>
> The AD4170 design has features to aid interfacing with weigh scale and RTD
> sensors that are expected to be setup with external circuitry for proper
> sensor operation. A key characteristic of those sensors is that the circuit
> they are in must be excited with a pair of signals. The external circuit
> can be excited either by voltage supply or by AD4170 excitation signals.
> The sensor can then be read through a different pair of lines that are
> connected to AD4170 ADC.
>
> Configure AD4170 to handle external circuit sensors.
...
> +static const unsigned int ad4170_iout_current_ua_tbl[] = {
> + 0, 10, 50, 100, 250, 500, 1000, 1500
Leave trailing comma.
> +};
...
> + if (st->pins_fn[ain_n] & AD4170_PIN_VBIAS) {
> + *ain_voltage = (st->vrefs_uv[AD4170_AVDD_SUP]
> + - st->vrefs_uv[AD4170_AVSS_SUP]) / 2;
Don't wrap like this, keep the logical split, and looking at this I
would just put it either on a single line, or use a temporary variable
for the expression in parentheses.
> + return 0;
> + }
...
> +static int ad4170_validate_excitation_pins(struct ad4170_state *st,
> + u32 *exc_pins, int num_exc_pins)
> +{
> + struct device *dev = &st->spi->dev;
> + int ret, i;
Should 'i' be signed?
> + for (i = 0; i < num_exc_pins; i++) {
> + unsigned int pin = exc_pins[i];
> +
> + ret = ad4170_find_table_index(ad4170_iout_pin_tbl, pin);
> + if (ret < 0)
> + return dev_err_probe(dev, ret,
> + "Invalid excitation pin: %u\n",
> + pin);
> +
> + if (pin <= AD4170_MAX_ANALOG_PINS) {
> + if (st->pins_fn[pin] != AD4170_PIN_UNASIGNED)
> + return dev_err_probe(dev, -EINVAL,
> + "Pin %u already used with fn %u\n",
> + pin, st->pins_fn[pin]);
> +
> + st->pins_fn[pin] |= AD4170_PIN_CURRENT_OUT;
> + } else {
> + unsigned int gpio = pin - AD4170_CURRENT_SRC_I_OUT_PIN_GPIO0;
> +
> + if (st->gpio_fn[gpio] != AD4170_GPIO_UNASIGNED)
> + return dev_err_probe(dev, -EINVAL,
> + "GPIO %u already used with fn %u\n",
> + gpio, st->gpio_fn[gpio]);
> +
> + st->gpio_fn[gpio] |= AD4170_GPIO_AC_EXCITATION;
> + }
> + }
> + return 0;
> +}
...
Also consider inverting the conditional in ad4170_setup_bridge() to
drop indentation level in a lot of LoCs.
...
> + switch (s_type) {
> + case AD4170_ADC_SENSOR:
> + ret = ad4170_parse_adc_channel_type(dev, child, chan);
> + if (ret < 0)
Why ' < 0'?
> + return ret;
> +
> + break;
> + case AD4170_WEIGH_SCALE_SENSOR:
> + fallthrough;
> + case AD4170_THERMOCOUPLE_SENSOR:
> + fallthrough;
> + case AD4170_RTD_SENSOR:
> + ret = ad4170_parse_external_sensor(st, child, setup, chan,
> + s_type);
> + if (ret < 0)
Ditto.
> + return ret;
>
> + break;
> + default:
> + return -EINVAL;
> + }
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH v2 7/7] iio: adc: ad4170: Add support for weigh scale and RTD sensors
2025-04-28 12:29 ` [PATCH v2 7/7] iio: adc: ad4170: Add support for weigh scale and RTD sensors Marcelo Schmitt
2025-04-29 22:26 ` Andy Shevchenko
@ 2025-05-01 19:50 ` kernel test robot
2025-05-04 17:42 ` Jonathan Cameron
2 siblings, 0 replies; 27+ messages in thread
From: kernel test robot @ 2025-05-01 19:50 UTC (permalink / raw)
To: Marcelo Schmitt, linux-iio, devicetree, linux-kernel
Cc: oe-kbuild-all, jic23, lars, Michael.Hennerich, dlechner, nuno.sa,
andy, robh, krzk+dt, conor+dt, marcelo.schmitt1
Hi Marcelo,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 1c2409fe38d5c19015d69851d15ba543d1911932]
url: https://github.com/intel-lab-lkp/linux/commits/Marcelo-Schmitt/dt-bindings-iio-adc-Add-AD4170/20250428-222010
base: 1c2409fe38d5c19015d69851d15ba543d1911932
patch link: https://lore.kernel.org/r/3687a9e0a479aef9736ad557b341ed2e7d4f5756.1745841276.git.marcelo.schmitt%40analog.com
patch subject: [PATCH v2 7/7] iio: adc: ad4170: Add support for weigh scale and RTD sensors
config: powerpc-allmodconfig (https://download.01.org/0day-ci/archive/20250502/202505020345.iJUIBTwt-lkp@intel.com/config)
compiler: powerpc64-linux-gcc (GCC) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250502/202505020345.iJUIBTwt-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202505020345.iJUIBTwt-lkp@intel.com/
All warnings (new ones prefixed by >>):
drivers/iio/adc/ad4170.c: In function 'ad4170_setup_current_src.isra':
>> drivers/iio/adc/ad4170.c:1881:29: warning: 'current_src' is used uninitialized [-Wuninitialized]
1881 | current_src |= FIELD_PREP(AD4170_CURRENT_SRC_I_OUT_PIN_MSK, pin);
| ^~
drivers/iio/adc/ad4170.c:1875:22: note: 'current_src' was declared here
1875 | unsigned int current_src, i, j;
| ^~~~~~~~~~~
vim +/current_src +1881 drivers/iio/adc/ad4170.c
1869
1870 static int ad4170_setup_current_src(struct ad4170_state *st,
1871 struct fwnode_handle *child,
1872 struct ad4170_setup *setup, u32 *exc_pins,
1873 int num_exc_pins, int exc_cur, bool ac_excited)
1874 {
1875 unsigned int current_src, i, j;
1876 int ret;
1877
1878 for (i = 0; i < num_exc_pins; i++) {
1879 unsigned int pin = exc_pins[i];
1880
> 1881 current_src |= FIELD_PREP(AD4170_CURRENT_SRC_I_OUT_PIN_MSK, pin);
1882 current_src |= FIELD_PREP(AD4170_CURRENT_SRC_I_OUT_VAL_MSK, exc_cur);
1883
1884 for (j = 0; j < AD4170_NUM_CURRENT_SRC; j++) {
1885 /*
1886 * Excitation current chopping is configured in pairs.
1887 * If current chopping configured and the first end of
1888 * the current source pair has already been assigned,
1889 * skip to the next pair of output currents.
1890 */
1891 if (ac_excited && j % 2 != 0)
1892 continue;
1893
1894 if (st->cur_src_pins[j] == AD4170_CURRENT_SRC_DISABLED) {
1895 st->cur_src_pins[j] = pin;
1896 break;
1897 }
1898 }
1899 if (j == AD4170_NUM_CURRENT_SRC)
1900 return dev_err_probe(&st->spi->dev, -EINVAL,
1901 "Failed to setup IOUT at pin %u\n",
1902 pin);
1903
1904 ret = regmap_write(st->regmap, AD4170_CURRENT_SRC_REG(j),
1905 current_src);
1906 if (ret)
1907 return ret;
1908 }
1909
1910 if (ac_excited && num_exc_pins > 1) {
1911 unsigned int exc_cur_pair;
1912
1913 if (st->cur_src_pins[0] == exc_pins[0])
1914 exc_cur_pair = 1;
1915 else
1916 exc_cur_pair = 2;
1917
1918 /*
1919 * Configure excitation currents chopping.
1920 * Chop two pairs if using four excitation currents.
1921 */
1922 setup->misc |= FIELD_PREP(AD4170_MISC_CHOP_IEXC_MSK,
1923 num_exc_pins == 2 ? exc_cur_pair : 3);
1924 }
1925
1926 return 0;
1927 }
1928
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH v2 7/7] iio: adc: ad4170: Add support for weigh scale and RTD sensors
2025-04-28 12:29 ` [PATCH v2 7/7] iio: adc: ad4170: Add support for weigh scale and RTD sensors Marcelo Schmitt
2025-04-29 22:26 ` Andy Shevchenko
2025-05-01 19:50 ` kernel test robot
@ 2025-05-04 17:42 ` Jonathan Cameron
2 siblings, 0 replies; 27+ messages in thread
From: Jonathan Cameron @ 2025-05-04 17:42 UTC (permalink / raw)
To: Marcelo Schmitt
Cc: linux-iio, devicetree, linux-kernel, lars, Michael.Hennerich,
dlechner, nuno.sa, andy, robh, krzk+dt, conor+dt,
marcelo.schmitt1
On Mon, 28 Apr 2025 09:29:40 -0300
Marcelo Schmitt <marcelo.schmitt@analog.com> wrote:
> The AD4170 design has features to aid interfacing with weigh scale and RTD
> sensors that are expected to be setup with external circuitry for proper
> sensor operation. A key characteristic of those sensors is that the circuit
> they are in must be excited with a pair of signals. The external circuit
> can be excited either by voltage supply or by AD4170 excitation signals.
> The sensor can then be read through a different pair of lines that are
> connected to AD4170 ADC.
>
> Configure AD4170 to handle external circuit sensors.
>
> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Hi Marcelo
A few comments inline.
Jonathan
> ---
> changes since v1:
> - Improved to support more than one external sensor connected.
>
> drivers/iio/adc/ad4170.c | 375 ++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 372 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/iio/adc/ad4170.c b/drivers/iio/adc/ad4170.c
> index 335b4194c7eb..9e4a9b524dd4 100644
> --- a/drivers/iio/adc/ad4170.c
> +++ b/drivers/iio/adc/ad4170.c
> @@ -62,6 +62,8 @@
> #define AD4170_FILTER_FS_REG(x) (0xC7 + 14 * (x))
> #define AD4170_OFFSET_REG(x) (0xCA + 14 * (x))
> #define AD4170_GAIN_REG(x) (0xCD + 14 * (x))
> +#define AD4170_V_BIAS_REG 0x135
> +#define AD4170_CURRENT_SRC_REG(x) (0x139 + 2 * (x))
> #define AD4170_GPIO_MODE_REG 0x191
> #define AD4170_GPIO_OUTPUT_REG 0x193
> #define AD4170_GPIO_INPUT_REG 0x195
> @@ -110,6 +112,10 @@
> /* AD4170_FILTER_REG */
> #define AD4170_FILTER_FILTER_TYPE_MSK GENMASK(3, 0)
>
> +/* AD4170_CURRENT_SRC_REG */
> +#define AD4170_CURRENT_SRC_I_OUT_PIN_MSK GENMASK(12, 8)
> +#define AD4170_CURRENT_SRC_I_OUT_VAL_MSK GENMASK(2, 0)
> +
> /* AD4170 register constants */
>
> /* AD4170_CLOCK_CTRL_REG constants */
> @@ -171,6 +177,21 @@
> #define AD4170_FILTER_FILTER_TYPE_SINC5 0x4
> #define AD4170_FILTER_FILTER_TYPE_SINC3 0x6
>
> +/* AD4170_CURRENT_SRC_REG constants */
These seem a bit repetitive. Can we use some macros?
#define AD4170_CURRENT_SRC_I_OUT_PIN_AIN(x) (x)
#define AD4170_CURRENT_SRC_I_OUT_PIN_GPIO(x) (x + 17)
> +#define AD4170_CURRENT_SRC_I_OUT_PIN_AIN0 0
> +#define AD4170_CURRENT_SRC_I_OUT_PIN_AIN1 1
> +#define AD4170_CURRENT_SRC_I_OUT_PIN_AIN2 2
> +#define AD4170_CURRENT_SRC_I_OUT_PIN_AIN3 3
> +#define AD4170_CURRENT_SRC_I_OUT_PIN_AIN4 4
> +#define AD4170_CURRENT_SRC_I_OUT_PIN_AIN5 5
> +#define AD4170_CURRENT_SRC_I_OUT_PIN_AIN6 6
> +#define AD4170_CURRENT_SRC_I_OUT_PIN_AIN7 7
> +#define AD4170_CURRENT_SRC_I_OUT_PIN_AIN8 8
> +#define AD4170_CURRENT_SRC_I_OUT_PIN_GPIO0 17
> +#define AD4170_CURRENT_SRC_I_OUT_PIN_GPIO1 18
> +#define AD4170_CURRENT_SRC_I_OUT_PIN_GPIO2 19
> +#define AD4170_CURRENT_SRC_I_OUT_PIN_GPIO3 20
> +
> /* Device properties and auxiliary constants */
>
> #define AD4170_NUM_ANALOG_PINS 9
> @@ -204,6 +225,15 @@
> #define AD4170_PIN_UNASIGNED 0x00
> #define AD4170_PIN_ANALOG_IN 0x01
> #define AD4170_PIN_CURRENT_OUT 0x02
> +#define AD4170_PIN_VBIAS 0x04
> +
> +/* GPIO pin functions */
> +#define AD4170_GPIO_UNASIGNED 0x00
> +#define AD4170_GPIO_AC_EXCITATION 0x02
> +#define AD4170_GPIO_OUTPUT 0x04
> +
> +/* Current source */
> +#define AD4170_CURRENT_SRC_DISABLED 0xFF
>
> static const unsigned int ad4170_reg_size[] = {
> [AD4170_CONFIG_A_REG] = 1,
> @@ -244,6 +274,8 @@ static const unsigned int ad4170_reg_size[] = {
> [AD4170_OFFSET_REG(5) ... AD4170_GAIN_REG(5)] = 3,
> [AD4170_OFFSET_REG(6) ... AD4170_GAIN_REG(6)] = 3,
> [AD4170_OFFSET_REG(7) ... AD4170_GAIN_REG(7)] = 3,
> + [AD4170_V_BIAS_REG] = 2,
> + [AD4170_CURRENT_SRC_REG(0) ... AD4170_CURRENT_SRC_REG(3)] = 2,
> [AD4170_GPIO_MODE_REG] = 2,
> [AD4170_GPIO_OUTPUT_REG] = 2,
> [AD4170_GPIO_INPUT_REG] = 2,
> @@ -305,6 +337,33 @@ static const unsigned int ad4170_sinc5_filt_fs_tbl[] = {
> 1, 2, 4, 8, 12, 16, 20, 40, 48, 80, 100, 256,
> };
>
> +static const unsigned int ad4170_iout_pin_tbl[] = {
> + AD4170_CURRENT_SRC_I_OUT_PIN_AIN0,
> + AD4170_CURRENT_SRC_I_OUT_PIN_AIN1,
> + AD4170_CURRENT_SRC_I_OUT_PIN_AIN2,
> + AD4170_CURRENT_SRC_I_OUT_PIN_AIN3,
> + AD4170_CURRENT_SRC_I_OUT_PIN_AIN4,
> + AD4170_CURRENT_SRC_I_OUT_PIN_AIN5,
> + AD4170_CURRENT_SRC_I_OUT_PIN_AIN6,
> + AD4170_CURRENT_SRC_I_OUT_PIN_AIN7,
> + AD4170_CURRENT_SRC_I_OUT_PIN_AIN8,
> + AD4170_CURRENT_SRC_I_OUT_PIN_GPIO0,
> + AD4170_CURRENT_SRC_I_OUT_PIN_GPIO1,
> + AD4170_CURRENT_SRC_I_OUT_PIN_GPIO2,
> + AD4170_CURRENT_SRC_I_OUT_PIN_GPIO3,
> +};
> +
> +static const unsigned int ad4170_iout_current_ua_tbl[] = {
> + 0, 10, 50, 100, 250, 500, 1000, 1500
I think Andy got this, but trailing comma.
> +};
> +
> +enum ad4170_sensor_type {
> + AD4170_WEIGH_SCALE_SENSOR = 0,
> + AD4170_RTD_SENSOR = 1,
> + AD4170_THERMOCOUPLE_SENSOR = 2,
> + AD4170_ADC_SENSOR = 3,
> +};
> +
> struct ad4170_chip_info {
> const char *name;
> };
> @@ -378,6 +437,8 @@ struct ad4170_state {
> struct clk *ext_clk;
> struct clk_hw int_clk_hw;
> int pins_fn[AD4170_NUM_ANALOG_PINS];
> + int gpio_fn[AD4170_NUM_GPIO_PINS];
> + unsigned int cur_src_pins[AD4170_NUM_CURRENT_SRC];
> struct gpio_chip gpiochip;
> u32 int_pin_sel;
> int sps_tbl[ARRAY_SIZE(ad4170_filt_names)][AD4170_MAX_FS_TBL_SIZE][2];
> @@ -925,6 +986,19 @@ static int ad4170_get_ain_voltage_uv(struct ad4170_state *st, int ain_n,
> struct device *dev = &st->spi->dev;
>
> *ain_voltage = 0;
> + /*
> + * The voltage bias (vbias) sets the common-mode voltage of the channel
> + * to (AVDD + AVSS)/2. If provided, AVSS supply provides the magnitude
> + * (absolute value) of the negative voltage supplied to the AVSS pin.
> + * So, we do AVDD - AVSS to compute the DC voltage generated by the bias
> + * voltage generator.
> + */
> + if (st->pins_fn[ain_n] & AD4170_PIN_VBIAS) {
> + *ain_voltage = (st->vrefs_uv[AD4170_AVDD_SUP]
> + - st->vrefs_uv[AD4170_AVSS_SUP]) / 2;
> + return 0;
> + }
> +
> if (ain_n <= AD4170_CHAN_MAP_TEMP_SENSOR)
> return 0;
>
> @@ -1742,6 +1816,266 @@ static int ad4170_gpio_init(struct iio_dev *indio_dev)
> return devm_gpiochip_add_data(&st->spi->dev, &st->gpiochip, indio_dev);
> }
>
> +static int _ad4170_find_table_index(const unsigned int *tbl, size_t len,
> + unsigned int val)
> +{
> + unsigned int i;
> +
> + for (i = 0; i < len; i++)
> + if (tbl[i] == val)
> + return i;
I wonder if this is worth while vs the opencoded version
for (i = 0; i < ARRAY_SIZE(ad4170_iout_pin_tbl); i++)
if (ad4170_iout_pin_tbl[i] == val)
break;
if (i == ARRAY_SIZE(ad4170_iout_pin_tbl))
return -EINVAL;
There is a bit more repetition and opportunity for missmatches
between which table etc, but it is pretty compact and you
only have two usecases of the function via the macro.
> +
> + return -EINVAL;
> +}
> +
> +#define ad4170_find_table_index(table, val) \
> + _ad4170_find_table_index(table, ARRAY_SIZE(table), val)
> +
> +static int ad4170_validate_excitation_pins(struct ad4170_state *st,
> + u32 *exc_pins, int num_exc_pins)
> +{
> + struct device *dev = &st->spi->dev;
> + int ret, i;
> +
> + for (i = 0; i < num_exc_pins; i++) {
> + unsigned int pin = exc_pins[i];
> +
> + ret = ad4170_find_table_index(ad4170_iout_pin_tbl, pin);
> + if (ret < 0)
> + return dev_err_probe(dev, ret,
> + "Invalid excitation pin: %u\n",
> + pin);
> +
> + if (pin <= AD4170_MAX_ANALOG_PINS) {
> + if (st->pins_fn[pin] != AD4170_PIN_UNASIGNED)
> + return dev_err_probe(dev, -EINVAL,
> + "Pin %u already used with fn %u\n",
> + pin, st->pins_fn[pin]);
> +
> + st->pins_fn[pin] |= AD4170_PIN_CURRENT_OUT;
> + } else {
> + unsigned int gpio = pin - AD4170_CURRENT_SRC_I_OUT_PIN_GPIO0;
> +
> + if (st->gpio_fn[gpio] != AD4170_GPIO_UNASIGNED)
> + return dev_err_probe(dev, -EINVAL,
> + "GPIO %u already used with fn %u\n",
> + gpio, st->gpio_fn[gpio]);
> +
> + st->gpio_fn[gpio] |= AD4170_GPIO_AC_EXCITATION;
> + }
> + }
> + return 0;
> +}
> +
> +
> +static int ad4170_setup_bridge(struct ad4170_state *st,
> + struct fwnode_handle *child,
> + struct ad4170_setup *setup, u32 *exc_pins,
> + int num_exc_pins, int exc_cur, bool ac_excited)
> +{
> + int ret;
> +
> + /*
> + * If a specific current is provided through
> + * adi,excitation-current-microamp, set excitation pins provided through
> + * adi,excitation-pins to AC excite the bridge circuit. Else, use
> + * predefined ACX1, ACX1 negated, ACX2, ACX2 negated signals to AC
> + * excite the bridge. Those signals are output on GPIO2, GPIO0, GPIO3,
> + * and GPIO1, respectively. If only two pins are specified for AC
> + * excitation, use ACX1 and ACX2.
> + *
> + * Also, to avoid any short-circuit condition when more than one channel
> + * is enabled, set GPIO2 and GPIO0 high, and set GPIO1 and GPIO3 low to
> + * DC excite the bridge whenever a channel without AC excitation is
> + * selected. That is needed because GPIO pins are controlled by the next
> + * highest priority GPIO function when a channel doesn't enable AC
> + * excitation. See datasheet Figure 113 Weigh Scale (AC Excitation) for
> + * an example circuit diagram.
> + */
> + if (exc_cur == 0 && ac_excited) {
> + if (num_exc_pins == 2) {
> + setup->misc |= FIELD_PREP(AD4170_MISC_CHOP_ADC_MSK, 0x3);
> + ret = regmap_set_bits(st->regmap,
> + AD4170_GPIO_MODE_REG,
> + BIT(7) | BIT(5));
These are fields in a register with meaning that isn't obvious here.
Should have defines to give them a 'meaning'.
I'll guess this is setting two separate 1 bit values in 2 bit fields?
Those need defines that take the index of the gpio.
> + if (ret)
> + return ret;
> +
> + ret = regmap_set_bits(st->regmap,
> + AD4170_GPIO_OUTPUT_REG,
> + BIT(3) | BIT(2));
This is a bit more obvious as those are the two pins we are using
but maybe a comment.
> + if (ret)
> + return ret;
> +
> + st->gpio_fn[3] |= AD4170_GPIO_OUTPUT;
> + st->gpio_fn[2] |= AD4170_GPIO_OUTPUT;
> + } else {
> + setup->misc |= FIELD_PREP(AD4170_MISC_CHOP_ADC_MSK, 0x2);
> + ret = regmap_set_bits(st->regmap,
> + AD4170_GPIO_MODE_REG,
> + BIT(7) | BIT(5) | BIT(3) | BIT(1));
As above. Looks like a bunch of 2 bit fields with value 1?
> + if (ret)
> + return ret;
> +
> + ret = regmap_set_bits(st->regmap,
> + AD4170_GPIO_OUTPUT_REG,
> + BIT(3) | BIT(2) | BIT(1) | BIT(0));
> + if (ret)
> + return ret;
> +
> + st->gpio_fn[3] |= AD4170_GPIO_OUTPUT;
> + st->gpio_fn[2] |= AD4170_GPIO_OUTPUT;
> + st->gpio_fn[1] |= AD4170_GPIO_OUTPUT;
> + st->gpio_fn[0] |= AD4170_GPIO_OUTPUT;
> + }
> +
> + return 0;
> + }
> +
> + return ad4170_setup_current_src(st, child, setup, exc_pins,
> + num_exc_pins, exc_cur, ac_excited);
> +}
^ permalink raw reply [flat|nested] 27+ messages in thread