* [PATCH v5 00/11] iio: adc: Add support for AD4170 series of ADCs
@ 2025-06-10 20:30 Marcelo Schmitt
2025-06-10 20:31 ` [PATCH v5 01/11] dt-bindings: iio: adc: Add AD4170 Marcelo Schmitt
` (11 more replies)
0 siblings, 12 replies; 35+ messages in thread
From: Marcelo Schmitt @ 2025-06-10 20:30 UTC (permalink / raw)
To: linux-iio, devicetree, linux-gpio, linux-kernel
Cc: jic23, lars, Michael.Hennerich, dlechner, nuno.sa, andy, robh,
krzk+dt, conor+dt, linus.walleij, brgl, marcelo.schmitt1
Hello,
This is version 5 of AD4170 support patch set.
Not many changes from v4 to v5 and not waiting as long between the previous and
this new version so, keeping both change logs below.
Thank you to all reviewers.
This patch set adds support for Analog Devices AD4170 and similar sigma-delta ADCs.
Patch 1 adds device tree documentation for the parts.
Patch 2 adds basic device support.
Patch 3 adds support for calibration scale.
Patch 4 adds support for calibration bias.
Patch 5 adds support for sample frequency along with filter type configuration.
Patch 6 adds support for buffered ADC reading.
Patch 7 adds clock provider support
Patch 8 adds GPIO controller support.
Patch 9 adds internal temperature sensor support.
Patch 10 adds support for external RTD and bridge circuit sensors.
Patch 11 adds timestamp channel
Change log v4 -> v5
[device tree changes]
- Dropped interrupt maxItems constraint.
- Spelled out RC acronym in reference-buffer description.
- Require to specify interrupt-names when using interrupts.
- Added interrupt-names to the examples.
- Made adi,excitation-pin properties identical to adi,ad4130.
- Removed interrupt-parent props from the examples.
[Basic driver patch]
- Dropped 'ret' variable set but not used, warned by 0-day test bot.
- Rephrased comment about static_assert to clarify the reason for it's usage.
- Added missing includes.
- Did a few minor code readability improvements, complying with review suggestions.
[Calibration scale/gain patch]
- Squeezed info_mask_separate additions to reduce change diff.
[External sensor patch]
- Tweaked commits/patches to reduce diff.
- Dropped unneeded local variable.
Change log v3 -> v4
[device tree changes]
- Dropped sensor-node and most of defs.
- Updated external sensor props to have similar name and type of adi,ad4130 ones.
- Added constraints for properties for related to external bridge sensor excitation.
[General IIO driver changes]
- Locked device mutex to ensure attribute read correctness on all archs
- Fixed typo unasigned -> unassigned
[Basic driver patch]
- Added previously missing #include <linux/cleanup.h>.
- Moved struct completion declaration to reduce commit diff.
[Calibration scale/gain patch]
[Calibration bias/offset patch]
- No longer restoring calib gain or calib offset on reg write fail.
[Digital filter and sample frequency config patch]
- Use scoped_guard to ensure correct lock release order in ad4170_set_filter_type().
[Buffer support patch]
- Fixed a bug in the filling of the IIO device buffer.
[CLOCK provider patch]
- Explicitly stated that clock divider (CLKDIV) control support is not provided.
- Skipped clock provider register if "#clock-cells" is not present.
[GPIO controller patch]
- Made AD4170 depend on GPIOLIB.
[External sensor patch]
- Update to string adi,sensor-type dt property.
- Adapted external sensor dt prop parsing to work with the updated version of those props.
[New patch - Add timestamp channel]
Link to v4: https://lore.kernel.org/linux-iio/cover.1748829860.git.marcelo.schmitt@analog.com/
Link to v3: https://lore.kernel.org/linux-iio/cover.1747083143.git.marcelo.schmitt@analog.com/
Link to v2: https://lore.kernel.org/linux-iio/cover.1745841276.git.marcelo.schmitt@analog.com/
Link to v1: https://lore.kernel.org/linux-iio/cover.1744200264.git.marcelo.schmitt@analog.com/
Ana-Maria Cusco (1):
iio: adc: Add basic support for AD4170
Marcelo Schmitt (10):
dt-bindings: iio: adc: Add AD4170
iio: adc: ad4170: Add support for calibration gain
iio: adc: ad4170: Add support for calibration bias
iio: adc: ad4170: Add digital filter and sample frequency config
support
iio: adc: ad4170: Add support for buffered data capture
iio: adc: ad4170: Add clock provider support
iio: adc: ad4170: Add GPIO controller support
iio: adc: ad4170: Add support for internal temperature sensor
iio: adc: ad4170: Add support for weigh scale and RTD sensors
iio: adc: ad4170: Add timestamp channel
.../bindings/iio/adc/adi,ad4170.yaml | 564 ++++
MAINTAINERS | 8 +
drivers/iio/adc/Kconfig | 16 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/ad4170.c | 2975 +++++++++++++++++
5 files changed, 3564 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml
create mode 100644 drivers/iio/adc/ad4170.c
base-commit: 4c6073fec2fee4827fa0dd8a4ab4e6f7bbc05ee6
--
2.47.2
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v5 01/11] dt-bindings: iio: adc: Add AD4170
2025-06-10 20:30 [PATCH v5 00/11] iio: adc: Add support for AD4170 series of ADCs Marcelo Schmitt
@ 2025-06-10 20:31 ` Marcelo Schmitt
2025-06-16 15:41 ` Conor Dooley
2025-06-10 20:31 ` [PATCH v5 02/11] iio: adc: Add basic support for AD4170 Marcelo Schmitt
` (10 subsequent siblings)
11 siblings, 1 reply; 35+ messages in thread
From: Marcelo Schmitt @ 2025-06-10 20:31 UTC (permalink / raw)
To: linux-iio, devicetree, linux-gpio, linux-kernel
Cc: jic23, lars, Michael.Hennerich, dlechner, nuno.sa, andy, robh,
krzk+dt, conor+dt, linus.walleij, brgl, marcelo.schmitt1
Add device tree documentation for AD4170 and similar sigma-delta ADCs.
The AD4170 is a 24-bit, multichannel, sigma-delta ADC.
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
Change log v4 -> v5
- Dropped interrupt maxItems constraint.
- Spelled out RC acronym in reference-buffer description.
- Require to specify interrupt-names when using interrupts.
- Added interrupt-names to the examples.
- Made adi,excitation-pin properties identical to adi,ad4130.
- Removed interrupt-parent props from the examples.
Proposing new types and ways of describing hardware for weigh scale load cells
and related sensors external to ADCs can lead to potential better description of
how those components connect to the ADC. However, we must use what already
exists for properties documenting features that are the same across different
devices.
Maybe, we could use generic defs to define adi,excitation-current-n-microamp and
adi,excitation-pin and avoid repetition with those. Though, that triggers a
dt_binding_check warning. Also, having mixed notation (some prop declarations
using defines and others not) seems to not be desirable.
It looks like the only option left is making adi,excitation-pin properties
identical to adi,ad4130.
On one hand, dropping adi,excitation-pin defs and making those properties
identical to adi,ad4130 preserves their syntax and semantics accross
dt-bindings. OTOH, we end up with more text repetition in the doc.
.../bindings/iio/adc/adi,ad4170.yaml | 564 ++++++++++++++++++
MAINTAINERS | 7 +
2 files changed, 571 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml
diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml
new file mode 100644
index 000000000000..e3249ec56a14
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml
@@ -0,0 +1,564 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad4170.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD4170 and similar Analog to Digital Converters
+
+maintainers:
+ - Marcelo Schmitt <marcelo.schmitt@analog.com>
+
+description: |
+ Analog Devices AD4170 series of Sigma-delta Analog to Digital Converters.
+ Specifications can be found at:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ad4170-4.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ad4190-4.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ad4195-4.pdf
+
+$ref: /schemas/spi/spi-peripheral-props.yaml#
+
+$defs:
+ reference-buffer:
+ description: |
+ Enable precharge buffer, full buffer, or skip reference buffering of
+ the positive/negative voltage reference. Because the output impedance
+ of the source driving the voltage reference inputs may be dynamic,
+ resistive/capacitive combinations of those inputs can cause DC gain
+ errors if the reference inputs go unbuffered into the ADC. Enable
+ reference buffering if the provided reference source has dynamic high
+ impedance output. Note the absolute voltage allowed on REFINn+ and REFINn-
+ inputs is from AVSS - 50 mV to AVDD + 50 mV when the reference buffers are
+ disabled but narrows to AVSS to AVDD when reference buffering is enabled
+ or in precharge mode. The valid options for this property are:
+ 0: Reference precharge buffer.
+ 1: Full reference buffering.
+ 2: Bypass reference buffers (buffering disabled).
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+ default: 1
+
+properties:
+ compatible:
+ enum:
+ - adi,ad4170
+ - adi,ad4190
+ - adi,ad4195
+
+ avss-supply:
+ description:
+ Reference voltage supply for AVSS. If provided, describes the magnitude
+ (absolute value) of the negative voltage supplied to the AVSS pin. Since
+ AVSS must be −2.625V minimum and 0V maximum, the declared supply voltage
+ must be between 0 and 2.65V. If not provided, AVSS is assumed to be at
+ system ground (0V).
+
+ avdd-supply:
+ description:
+ A supply of 4.75V to 5.25V relative to AVSS that powers the chip (AVDD).
+
+ iovdd-supply:
+ description: 1.7V to 5.25V reference supply to the serial interface (IOVDD).
+
+ refin1p-supply:
+ description: REFIN+ supply that can be used as reference for conversion.
+
+ refin1n-supply:
+ description: REFIN- supply that can be used as reference for conversion. If
+ provided, describes the magnitude (absolute value) of the negative voltage
+ supplied to the REFIN- pin.
+
+ refin2p-supply:
+ description: REFIN2+ supply that can be used as reference for conversion.
+
+ refin2n-supply:
+ description: REFIN2- supply that can be used as reference for conversion. If
+ provided, describes the magnitude (absolute value) of the negative voltage
+ supplied to the REFIN2- pin.
+
+ spi-cpol: true
+
+ spi-cpha: true
+
+ interrupts:
+ description:
+ Interrupt for signaling the completion of conversion results. The data
+ ready signal (RDY) used as interrupt is by default provided on the SDO
+ pin. Alternatively, it can be provided on the DIG_AUX1 pin in which case
+ the chip disables the RDY function on SDO. Thus, there can be only one
+ data ready interrupt enabled at a time.
+
+ interrupt-names:
+ description:
+ Specify which pin should be configured as Data Ready interrupt.
+ enum:
+ - sdo
+ - dig_aux1
+
+ clocks:
+ maxItems: 1
+ description:
+ Optional external clock source. Can specify either an external clock or
+ external crystal.
+
+ clock-names:
+ enum:
+ - ext-clk
+ - xtal
+ default: ext-clk
+
+ '#clock-cells':
+ const: 0
+
+ clock-output-names:
+ maxItems: 1
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+ description: |
+ The first cell is for the GPIO number: 0 to 3.
+ The second cell takes standard GPIO flags.
+
+ ldac-gpios:
+ description:
+ GPIO connected to DIG_AUX2 pin to be used as LDAC toggle to control the
+ transfer of data from the DAC_INPUT_A register to the DAC.
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ adi,vbias-pins:
+ description: Analog inputs to apply a voltage bias of (AVDD − AVSS) / 2 to.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 9
+ items:
+ minimum: 0
+ maximum: 8
+
+allOf:
+ # Some devices don't have integrated DAC
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,ad4190
+ - adi,ad4195
+ then:
+ properties:
+ ldac-gpios: false
+
+ # Require to specify the interrupt pin when using interrupts
+ - if:
+ required:
+ - interrupts
+ then:
+ required:
+ - interrupt-names
+
+ # If an external clock is set, the internal clock cannot go out and vice versa
+ - oneOf:
+ - required: [clocks]
+ properties:
+ '#clock-cells': false
+ - required: ['#clock-cells']
+ properties:
+ clocks: false
+
+patternProperties:
+ "^channel@[0-9a-f]$":
+ $ref: /schemas/iio/adc/adc.yaml#
+ unevaluatedProperties: false
+ description:
+ Represents the external channels which are connected to the ADC.
+
+ properties:
+ reg:
+ description:
+ The channel number.
+ minimum: 0
+ maximum: 15
+
+ diff-channels:
+ description: |
+ This property is used for defining the inputs of a differential
+ voltage channel. The first value is the positive input and the second
+ value is the negative input of the channel.
+
+ Besides the analog input pins AIN0 to AIN8, there are special inputs
+ that can be selected with the following values:
+ 17: Internal temperature sensor
+ 18: (AVDD-AVSS)/5
+ 19: (IOVDD-DGND)/5
+ 20: DAC output
+ 21: ALDO
+ 22: DLDO
+ 23: AVSS
+ 24: DGND
+ 25: REFIN+
+ 26: REFIN-
+ 27: REFIN2+
+ 28: REFIN2-
+ 29: REFOUT
+ For the internal temperature sensor, use the input number for both
+ inputs (i.e. diff-channels = <17 17>).
+ items:
+ enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 17, 18, 19, 20, 21, 22, 23, 24, 25,
+ 26, 27, 28, 29]
+
+ adi,reference-select:
+ description: |
+ Select the reference source to use when converting on the
+ specific channel. Valid values are:
+ 0: REFIN+/REFIN-
+ 1: REFIN2+/REFIN2−
+ 2: REFOUT/AVSS (internal reference)
+ 3: AVDD/AVSS
+ If not specified, REFOUT/AVSS is used.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ default: 1
+
+ adi,positive-reference-buffer:
+ $ref: '#/$defs/reference-buffer'
+
+ adi,negative-reference-buffer:
+ $ref: '#/$defs/reference-buffer'
+
+ adi,sensor-type:
+ description:
+ The AD4170 and similar designs have features to aid interfacing with
+ load cell weigh scale, RTD, and thermocouple sensors. Each of those
+ sensor types requires either distinct wiring configuration or
+ external circuitry for proper sensor operation and can use different
+ ADC chip functionality on their setups. A key characteristic of those
+ external sensors is that they must be excited either by voltage supply
+ or by ADC chip excitation signals. The sensor can then be read through
+ a pair of analog inputs. This property specifies which particular
+ sensor type is connected to the ADC so it can be properly setup and
+ handled. Omit this property for conventional (not weigh scale, RTD, or
+ thermocouple) ADC channel setups.
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [ weighscale, rtd, thermocouple ]
+
+ adi,excitation-pin-0:
+ description:
+ Analog input to apply excitation current to while the channel
+ is active.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 20
+ default: 0
+
+ adi,excitation-pin-1:
+ description:
+ Analog input to apply excitation current to while the channel
+ is active.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 20
+ default: 0
+
+ adi,excitation-pin-2:
+ description:
+ Analog input to apply excitation current to while the channel
+ is active.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 20
+ default: 0
+
+ adi,excitation-pin-3:
+ description:
+ Analog input to apply excitation current to while the channel
+ is active.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 20
+ default: 0
+
+ adi,excitation-current-0-microamp:
+ description:
+ Excitation current in microamperes to be applied to pin specified in
+ adi,excitation-pin-0 while this channel is active.
+ enum: [0, 10, 50, 100, 250, 500, 1000, 1500]
+ default: 0
+
+ adi,excitation-current-1-microamp:
+ description:
+ Excitation current in microamperes to be applied to pin specified in
+ adi,excitation-pin-1 while this channel is active.
+ enum: [0, 10, 50, 100, 250, 500, 1000, 1500]
+ default: 0
+
+ adi,excitation-current-2-microamp:
+ description:
+ Excitation current in microamperes to be applied to pin specified in
+ adi,excitation-pin-2 while this channel is active.
+ enum: [0, 10, 50, 100, 250, 500, 1000, 1500]
+ default: 0
+
+ adi,excitation-current-3-microamp:
+ description:
+ Excitation current in microamperes to be applied to pin specified in
+ adi,excitation-pin-3 while this channel is active.
+ enum: [0, 10, 50, 100, 250, 500, 1000, 1500]
+ default: 0
+
+ adi,excitation-ac:
+ type: boolean
+ description:
+ Whether the external sensor has to be AC or DC excited. When omitted,
+ it is DC excited.
+
+ allOf:
+ - oneOf:
+ - required: [single-channel, common-mode-channel]
+ properties:
+ diff-channels: false
+ - required: [diff-channels]
+ properties:
+ single-channel: false
+ common-mode-channel: false
+ # Usual ADC channels don't need external circuitry excitation.
+ - if:
+ not:
+ required:
+ - adi,sensor-type
+ then:
+ properties:
+ adi,excitation-pin-0: false
+ adi,excitation-pin-1: false
+ adi,excitation-pin-2: false
+ adi,excitation-pin-3: false
+ adi,excitation-current-0-microamp: false
+ adi,excitation-current-1-microamp: false
+ adi,excitation-current-2-microamp: false
+ adi,excitation-current-3-microamp: false
+ adi,excitation-ac: false
+ # Weigh scale bridge AC excited with one pair of predefined signals.
+ - if:
+ allOf:
+ - properties:
+ adi,sensor-type:
+ contains:
+ const: weighscale
+ - required:
+ - adi,excitation-ac
+ - adi,excitation-pin-2
+ - adi,excitation-pin-3
+ - not:
+ required:
+ - adi,excitation-current-2-microamp
+ - adi,excitation-current-3-microamp
+ then:
+ properties:
+ adi,excitation-pin-2:
+ const: 19
+ adi,excitation-pin-3:
+ const: 20
+ # Weigh scale bridge AC excited with two pairs of predefined signals.
+ - if:
+ allOf:
+ - properties:
+ adi,sensor-type:
+ contains:
+ const: weighscale
+ - required:
+ - adi,excitation-ac
+ - adi,excitation-pin-0
+ - adi,excitation-pin-1
+ - adi,excitation-pin-2
+ - adi,excitation-pin-3
+ - not:
+ required:
+ - adi,excitation-current-0-microamp
+ - adi,excitation-current-1-microamp
+ - adi,excitation-current-2-microamp
+ - adi,excitation-current-3-microamp
+ then:
+ properties:
+ adi,excitation-pin-0:
+ const: 17
+ adi,excitation-pin-1:
+ const: 18
+ adi,excitation-pin-2:
+ const: 19
+ adi,excitation-pin-3:
+ const: 20
+
+required:
+ - compatible
+ - reg
+ - avdd-supply
+ - iovdd-supply
+ - spi-cpol
+ - spi-cpha
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad4170";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ spi-cpol;
+ spi-cpha;
+ avdd-supply = <&avdd>;
+ iovdd-supply = <&iovdd>;
+ clocks = <&clk>;
+ clock-names = "xtal";
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-names = "dig_aux1";
+ adi,vbias-pins = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ // Sample AIN0 with respect to DGND throughout AVDD/DGND input range
+ // Pseudo-differential unipolar
+ channel@0 {
+ reg = <0>;
+ single-channel = <0>;
+ common-mode-channel = <24>;
+ adi,reference-select = <3>;
+ };
+ // Weigh scale sensor
+ channel@1 {
+ reg = <1>;
+ bipolar;
+ diff-channels = <1 2>;
+ adi,reference-select = <0>;
+ adi,positive-reference-buffer = <0>;
+ adi,negative-reference-buffer = <0>;
+ adi,sensor-type = "weighscale";
+ adi,excitation-pin-2 = <19>;
+ adi,excitation-pin-3 = <20>;
+ adi,excitation-ac;
+ };
+ // RTD sensor
+ channel@2 {
+ reg = <2>;
+ bipolar;
+ diff-channels = <3 4>;
+ adi,reference-select = <0>;
+ adi,sensor-type = "rtd";
+ adi,excitation-pin-0 = <5>;
+ adi,excitation-pin-1 = <6>;
+ adi,excitation-current-0-microamp = <500>;
+ adi,excitation-current-1-microamp = <500>;
+ adi,excitation-ac;
+ };
+ // Thermocouple sensor
+ channel@3 {
+ reg = <3>;
+ bipolar;
+ diff-channels = <7 8>;
+ adi,reference-select = <0>;
+ adi,sensor-type = "thermocouple";
+ adi,excitation-pin-0 = <18>;
+ adi,excitation-current-0-microamp = <500>;
+ };
+ };
+ };
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad4170";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ spi-cpol;
+ spi-cpha;
+ avdd-supply = <&avdd>;
+ iovdd-supply = <&iovdd>;
+ #clock-cells = <0>;
+ clock-output-names = "ad4170-clk16mhz";
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-names = "dig_aux1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ // Sample AIN0 with respect to AIN1 throughout AVDD/AVSS input range
+ // Differential bipolar. If AVSS < 0V, differential true bipolar
+ channel@0 {
+ reg = <0>;
+ bipolar;
+ diff-channels = <0 1>;
+ adi,reference-select = <3>;
+ };
+ // Sample AIN2 with respect to DGND throughout AVDD/DGND input range
+ // Pseudo-differential unipolar
+ channel@1 {
+ reg = <1>;
+ single-channel = <2>;
+ common-mode-channel = <24>;
+ adi,reference-select = <3>;
+ };
+ // Sample AIN3 with respect to 2.5V throughout AVDD/AVSS input range
+ // Pseudo-differential bipolar
+ channel@2 {
+ reg = <2>;
+ bipolar;
+ single-channel = <3>;
+ common-mode-channel = <29>;
+ adi,reference-select = <3>;
+ };
+ // Sample AIN4 with respect to DGND throughout AVDD/AVSS input range
+ // Pseudo-differential bipolar
+ channel@3 {
+ reg = <3>;
+ bipolar;
+ single-channel = <4>;
+ common-mode-channel = <24>;
+ adi,reference-select = <3>;
+ };
+ // Sample AIN5 with respect to 2.5V throughout AVDD/AVSS input range
+ // Pseudo-differential unipolar (AD4170 datasheet page 46 example)
+ channel@4 {
+ reg = <4>;
+ single-channel = <5>;
+ common-mode-channel = <29>;
+ adi,reference-select = <3>;
+ };
+ // Sample AIN6 with respect to 2.5V throughout REFIN+/REFIN- input range
+ // Pseudo-differential bipolar
+ channel@5 {
+ reg = <5>;
+ bipolar;
+ single-channel = <6>;
+ common-mode-channel = <29>;
+ adi,reference-select = <0>;
+ };
+ // Weigh scale sensor
+ channel@6 {
+ reg = <6>;
+ bipolar;
+ diff-channels = <7 8>;
+ adi,reference-select = <0>;
+ adi,sensor-type = "weighscale";
+ adi,excitation-pin-0 = <17>;
+ adi,excitation-pin-1 = <18>;
+ adi,excitation-pin-2 = <19>;
+ adi,excitation-pin-3 = <20>;
+ adi,excitation-ac;
+ };
+ };
+ };
+...
+
diff --git a/MAINTAINERS b/MAINTAINERS
index abfd5ded8735..44735314a43e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1392,6 +1392,13 @@ F: Documentation/ABI/testing/sysfs-bus-iio-adc-ad4130
F: Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml
F: drivers/iio/adc/ad4130.c
+ANALOG DEVICES INC AD4170 DRIVER
+M: Marcelo Schmitt <marcelo.schmitt@analog.com>
+L: linux-iio@vger.kernel.org
+S: Supported
+W: https://ez.analog.com/linux-software-drivers
+F: Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml
+
ANALOG DEVICES INC AD4695 DRIVER
M: Michael Hennerich <michael.hennerich@analog.com>
M: Nuno Sá <nuno.sa@analog.com>
--
2.47.2
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v5 02/11] iio: adc: Add basic support for AD4170
2025-06-10 20:30 [PATCH v5 00/11] iio: adc: Add support for AD4170 series of ADCs Marcelo Schmitt
2025-06-10 20:31 ` [PATCH v5 01/11] dt-bindings: iio: adc: Add AD4170 Marcelo Schmitt
@ 2025-06-10 20:31 ` Marcelo Schmitt
2025-06-10 21:10 ` Andy Shevchenko
` (2 more replies)
2025-06-10 20:31 ` [PATCH v5 03/11] iio: adc: ad4170: Add support for calibration gain Marcelo Schmitt
` (9 subsequent siblings)
11 siblings, 3 replies; 35+ messages in thread
From: Marcelo Schmitt @ 2025-06-10 20:31 UTC (permalink / raw)
To: linux-iio, devicetree, linux-gpio, linux-kernel
Cc: Ana-Maria Cusco, jic23, lars, Michael.Hennerich, dlechner,
nuno.sa, andy, robh, krzk+dt, conor+dt, linus.walleij, brgl,
marcelo.schmitt1
From: Ana-Maria Cusco <ana-maria.cusco@analog.com>
The AD4170 is a multichannel, low noise, 24-bit precision sigma-delta
analog to digital converter. The AD4170 design offers a flexible data
acquisition solution with crosspoint multiplexed analog inputs,
configurable ADC voltage reference inputs, ultra-low noise integrated PGA,
digital filtering, wide range of configurable output data rates, internal
oscillator and temperature sensor, four GPIOs, and integrated features for
interfacing with load cell weigh scales, RTD, and thermocouple sensors.
Add basic support for the AD4170 ADC with the following features:
- Single-shot read.
- Analog front end PGA configuration.
- Differential and pseudo-differential input configuration.
Signed-off-by: Ana-Maria Cusco <ana-maria.cusco@analog.com>
Co-developed-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
Change log v4 -> v5
- Dropped 'ret' variable set but not used, warned by 0-day test bot.
- Rephrased comment about static_assert to clarify the reason for it's usage.
- Added missing includes.
- Did a few minor code readability improvements, complying with review suggestions.
MAINTAINERS | 1 +
drivers/iio/adc/Kconfig | 12 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/ad4170.c | 1535 ++++++++++++++++++++++++++++++++++++++
4 files changed, 1549 insertions(+)
create mode 100644 drivers/iio/adc/ad4170.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 44735314a43e..66d261ebbaf8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1398,6 +1398,7 @@ L: linux-iio@vger.kernel.org
S: Supported
W: https://ez.analog.com/linux-software-drivers
F: Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml
+F: drivers/iio/adc/ad4170.c
ANALOG DEVICES INC AD4695 DRIVER
M: Michael Hennerich <michael.hennerich@analog.com>
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 3bd03df9a976..03966d07a721 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -84,6 +84,18 @@ config AD4130
To compile this driver as a module, choose M here: the module will be
called ad4130.
+
+config AD4170
+ tristate "Analog Device AD4170 ADC Driver"
+ depends on SPI
+ select REGMAP_SPI
+ help
+ Say yes here to build support for Analog Devices AD4170 SPI analog
+ to digital converters (ADC).
+
+ To compile this driver as a module, choose M here: the module will be
+ called ad4170.
+
config AD4695
tristate "Analog Device AD4695 ADC Driver"
depends on SPI
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index 6516ccb4d63b..d99c35ff9a1c 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_AD4000) += ad4000.o
obj-$(CONFIG_AD4030) += ad4030.o
obj-$(CONFIG_AD4080) += ad4080.o
obj-$(CONFIG_AD4130) += ad4130.o
+obj-$(CONFIG_AD4170) += ad4170.o
obj-$(CONFIG_AD4695) += ad4695.o
obj-$(CONFIG_AD4851) += ad4851.o
obj-$(CONFIG_AD7091R) += ad7091r-base.o
diff --git a/drivers/iio/adc/ad4170.c b/drivers/iio/adc/ad4170.c
new file mode 100644
index 000000000000..d0628430ed14
--- /dev/null
+++ b/drivers/iio/adc/ad4170.c
@@ -0,0 +1,1535 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2025 Analog Devices, Inc.
+ * Author: Ana-Maria Cusco <ana-maria.cusco@analog.com>
+ * Author: Marcelo Schmitt <marcelo.schmitt@analog.com>
+ */
+
+#include <linux/array_size.h>
+#include <linux/bitfield.h>
+#include <linux/bitmap.h>
+#include <linux/bitops.h>
+#include <linux/bits.h>
+#include <linux/cleanup.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/iio/iio.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/math64.h>
+#include <linux/module.h>
+#include <linux/property.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+#include <linux/spi/spi.h>
+#include <linux/time.h>
+#include <linux/types.h>
+#include <linux/unaligned.h>
+#include <linux/units.h>
+#include <linux/util_macros.h>
+
+/*
+ * AD4170 registers
+ * Multibyte register addresses point to the most significant byte which is the
+ * address to use to get the most significant byte first (address accessed is
+ * decremented by one for each data byte)
+ *
+ * Each register address define follows the AD4170_<REG_NAME>_REG form.
+ * Each mask follows the AD4170_<REG_NAME>_<FIELD_NAME> form.
+ * E.g. AD4170_PIN_MUXING_DIG_AUX1_CTRL_MSK is for accessing DIG_AUX1_CTRL field
+ * of PIN_MUXING_REG.
+ * Each constant follows the AD4170_<REG_NAME>_<FIELD_NAME>_<FUNCTION> form.
+ * E.g. AD4170_PIN_MUXING_DIG_AUX1_DISABLED is the value written to
+ * DIG_AUX1_CTRL field of PIN_MUXING register to disable DIG_AUX1 pin.
+ * Some register names and register field names are shortened versions of
+ * their datasheet counterpart names to provide better code readability.
+ */
+#define AD4170_CONFIG_A_REG 0x00
+#define AD4170_DATA_24B_REG 0x1E
+#define AD4170_PIN_MUXING_REG 0x69
+#define AD4170_ADC_CTRL_REG 0x71
+#define AD4170_CHAN_EN_REG 0x79
+#define AD4170_CHAN_SETUP_REG(x) (0x81 + 4 * (x))
+#define AD4170_CHAN_MAP_REG(x) (0x83 + 4 * (x))
+#define AD4170_MISC_REG(x) (0xC1 + 14 * (x))
+#define AD4170_AFE_REG(x) (0xC3 + 14 * (x))
+#define AD4170_FILTER_REG(x) (0xC5 + 14 * (x))
+#define AD4170_FILTER_FS_REG(x) (0xC7 + 14 * (x))
+#define AD4170_OFFSET_REG(x) (0xCA + 14 * (x))
+#define AD4170_GAIN_REG(x) (0xCD + 14 * (x))
+
+#define AD4170_REG_READ_MASK BIT(14)
+
+/* AD4170_CONFIG_A_REG - INTERFACE_CONFIG_A REGISTER */
+#define AD4170_SW_RESET_MSK (BIT(7) | BIT(0))
+
+/* AD4170_PIN_MUXING_REG */
+#define AD4170_PIN_MUXING_DIG_AUX1_CTRL_MSK GENMASK(5, 4)
+
+/* AD4170_ADC_CTRL_REG */
+#define AD4170_ADC_CTRL_MULTI_DATA_REG_SEL_MSK BIT(7)
+#define AD4170_ADC_CTRL_MODE_MSK GENMASK(3, 0)
+
+/* AD4170_CHAN_EN_REG */
+#define AD4170_CHAN_EN(ch) BIT(ch)
+
+/* AD4170_CHAN_SETUP_REG */
+#define AD4170_CHAN_SETUP_SETUP_MSK GENMASK(2, 0)
+
+/* AD4170_CHAN_MAP_REG */
+#define AD4170_CHAN_MAP_AINP_MSK GENMASK(12, 8)
+#define AD4170_CHAN_MAP_AINM_MSK GENMASK(4, 0)
+
+/* AD4170_AFE_REG */
+#define AD4170_AFE_REF_BUF_M_MSK GENMASK(11, 10)
+#define AD4170_AFE_REF_BUF_P_MSK GENMASK(9, 8)
+#define AD4170_AFE_REF_SELECT_MSK GENMASK(6, 5)
+#define AD4170_AFE_BIPOLAR_MSK BIT(4)
+#define AD4170_AFE_PGA_GAIN_MSK GENMASK(3, 0)
+
+/* AD4170 register constants */
+
+/* AD4170_CHAN_MAP_REG constants */
+#define AD4170_CHAN_MAP_AIN(x) (x)
+#define AD4170_CHAN_MAP_TEMP_SENSOR 17
+#define AD4170_CHAN_MAP_AVDD_AVSS_P 18
+#define AD4170_CHAN_MAP_AVDD_AVSS_N 18
+#define AD4170_CHAN_MAP_IOVDD_DGND_P 19
+#define AD4170_CHAN_MAP_IOVDD_DGND_N 19
+#define AD4170_CHAN_MAP_AVSS 23
+#define AD4170_CHAN_MAP_DGND 24
+#define AD4170_CHAN_MAP_REFIN1_P 25
+#define AD4170_CHAN_MAP_REFIN1_N 26
+#define AD4170_CHAN_MAP_REFIN2_P 27
+#define AD4170_CHAN_MAP_REFIN2_N 28
+#define AD4170_CHAN_MAP_REFOUT 29
+
+/* AD4170_PIN_MUXING_REG constants */
+#define AD4170_PIN_MUXING_DIG_AUX1_DISABLED 0x0
+#define AD4170_PIN_MUXING_DIG_AUX1_RDY 0x1
+
+/* AD4170_ADC_CTRL_REG constants */
+#define AD4170_ADC_CTRL_MODE_SINGLE 0x4
+#define AD4170_ADC_CTRL_MODE_IDLE 0x7
+
+/* Device properties and auxiliary constants */
+
+#define AD4170_NUM_ANALOG_PINS 9
+#define AD4170_MAX_CHANNELS 16
+#define AD4170_MAX_ANALOG_PINS 8
+#define AD4170_MAX_SETUPS 8
+#define AD4170_INVALID_SETUP 9
+#define AD4170_SPI_MAX_XFER_LEN 6
+
+#define AD4170_INT_REF_2_5V 2500000
+
+/* Internal and external clock properties */
+#define AD4170_INT_CLOCK_16MHZ (16 * HZ_PER_MHZ)
+
+#define AD4170_NUM_PGA_OPTIONS 10
+
+#define AD4170_GAIN_REG_DEFAULT 0x555555
+
+static const unsigned int ad4170_reg_size[] = {
+ [AD4170_CONFIG_A_REG] = 1,
+ [AD4170_DATA_24B_REG] = 3,
+ [AD4170_PIN_MUXING_REG] = 2,
+ [AD4170_ADC_CTRL_REG] = 2,
+ [AD4170_CHAN_EN_REG] = 2,
+ /*
+ * CHANNEL_SETUP and CHANNEL_MAP register are all 2 byte size each and
+ * their addresses are interleaved such that we have CHANNEL_SETUP0
+ * address followed by CHANNEL_MAP0 address, followed by CHANNEL_SETUP1,
+ * and so on until CHANNEL_MAP15.
+ * Thus, initialize the register size for them only once.
+ */
+ [AD4170_CHAN_SETUP_REG(0) ... AD4170_CHAN_MAP_REG(AD4170_MAX_CHANNELS - 1)] = 2,
+ /*
+ * MISC, AFE, FILTER, FILTER_FS, OFFSET, and GAIN register addresses are
+ * also interleaved but MISC, AFE, FILTER, FILTER_FS, OFFSET are 16-bit
+ * while OFFSET, GAIN are 24-bit registers so we can't init them all to
+ * the same size.
+ */
+ [AD4170_MISC_REG(0) ... AD4170_FILTER_FS_REG(0)] = 2,
+ [AD4170_MISC_REG(1) ... AD4170_FILTER_FS_REG(1)] = 2,
+ [AD4170_MISC_REG(2) ... AD4170_FILTER_FS_REG(2)] = 2,
+ [AD4170_MISC_REG(3) ... AD4170_FILTER_FS_REG(3)] = 2,
+ [AD4170_MISC_REG(4) ... AD4170_FILTER_FS_REG(4)] = 2,
+ [AD4170_MISC_REG(5) ... AD4170_FILTER_FS_REG(5)] = 2,
+ [AD4170_MISC_REG(6) ... AD4170_FILTER_FS_REG(6)] = 2,
+ [AD4170_MISC_REG(7) ... AD4170_FILTER_FS_REG(7)] = 2,
+ [AD4170_OFFSET_REG(0) ... AD4170_GAIN_REG(0)] = 3,
+ [AD4170_OFFSET_REG(1) ... AD4170_GAIN_REG(1)] = 3,
+ [AD4170_OFFSET_REG(2) ... AD4170_GAIN_REG(2)] = 3,
+ [AD4170_OFFSET_REG(3) ... AD4170_GAIN_REG(3)] = 3,
+ [AD4170_OFFSET_REG(4) ... AD4170_GAIN_REG(4)] = 3,
+ [AD4170_OFFSET_REG(5) ... AD4170_GAIN_REG(5)] = 3,
+ [AD4170_OFFSET_REG(6) ... AD4170_GAIN_REG(6)] = 3,
+ [AD4170_OFFSET_REG(7) ... AD4170_GAIN_REG(7)] = 3,
+};
+
+enum ad4170_ref_buf {
+ AD4170_REF_BUF_PRE, /* Pre-charge referrence buffer */
+ AD4170_REF_BUF_FULL, /* Full referrence buffering */
+ AD4170_REF_BUF_BYPASS /* Bypass referrence buffering */
+};
+
+enum ad4170_ref_select {
+ AD4170_REF_REFIN1,
+ AD4170_REF_REFIN2,
+ AD4170_REF_REFOUT,
+ AD4170_REF_AVDD
+};
+
+enum ad4170_regulator {
+ AD4170_AVDD_SUP,
+ AD4170_AVSS_SUP,
+ AD4170_IOVDD_SUP,
+ AD4170_REFIN1P_SUP,
+ AD4170_REFIN1N_SUP,
+ AD4170_REFIN2P_SUP,
+ AD4170_REFIN2N_SUP,
+ AD4170_MAX_SUP
+};
+
+enum ad4170_int_pin_sel {
+ AD4170_INT_PIN_SDO,
+ AD4170_INT_PIN_DIG_AUX1,
+};
+
+static const char * const ad4170_int_pin_names[] = {
+ [AD4170_INT_PIN_SDO] = "sdo",
+ [AD4170_INT_PIN_DIG_AUX1] = "dig_aux1",
+};
+
+struct ad4170_chip_info {
+ const char *name;
+};
+
+static const struct ad4170_chip_info ad4170_chip_info = {
+ .name = "ad4170",
+};
+
+static const struct ad4170_chip_info ad4190_chip_info = {
+ .name = "ad4190",
+};
+
+static const struct ad4170_chip_info ad4195_chip_info = {
+ .name = "ad4195",
+};
+
+/*
+ * There are 8 of each MISC, AFE, FILTER, FILTER_FS, OFFSET, and GAIN
+ * configuration registers. That is, there are 8 miscellaneous registers, MISC0
+ * to MISC7. Each MISC register is associated with a setup; MISCN is associated
+ * with setup number N. The other 5 above mentioned types of registers have
+ * analogous structure. A setup is a set of those registers. For example,
+ * setup 1 comprises of MISC1, AFE1, FILTER1, FILTER_FS1, OFFSET1, and GAIN1
+ * registers. Also, there are 16 CHANNEL_SETUP registers (CHANNEL_SETUP0 to
+ * CHANNEL_SETUP15). Each channel setup is associated with one of the 8 possible
+ * setups. Thus, AD4170 can support up to 16 channels but, since there are only
+ * 8 available setups, channels must share settings if more than 8 channels are
+ * configured.
+ *
+ * If this struct is modified, ad4170_setup_eq() will probably need to be
+ * updated too.
+ */
+struct ad4170_setup {
+ u16 misc;
+ u16 afe;
+ u16 filter;
+ u16 filter_fs;
+ u32 offset; /* For calibration purposes */
+ u32 gain; /* For calibration purposes */
+};
+
+struct ad4170_setup_info {
+ struct ad4170_setup setup;
+ unsigned int enabled_channels;
+ unsigned int channels;
+};
+
+struct ad4170_chan_info {
+ unsigned int input_range_uv;
+ unsigned int setup_num; /* Index to access state setup_infos array */
+ struct ad4170_setup setup; /* cached setup */
+ int offset_tbl[10];
+ u32 scale_tbl[10][2];
+ bool initialized;
+ bool enabled;
+};
+
+struct ad4170_state {
+ struct mutex lock; /* Protect read-modify-write and multi write sequences */
+ int vrefs_uv[AD4170_MAX_SUP];
+ u32 mclk_hz;
+ struct ad4170_setup_info setup_infos[AD4170_MAX_SETUPS];
+ struct iio_chan_spec chans[AD4170_MAX_CHANNELS];
+ struct ad4170_chan_info chan_infos[AD4170_MAX_CHANNELS];
+ struct spi_device *spi;
+ struct regmap *regmap;
+ struct completion completion;
+ int pins_fn[AD4170_NUM_ANALOG_PINS];
+ u32 int_pin_sel;
+ /*
+ * DMA (thus cache coherency maintenance) requires the transfer buffers
+ * to live in their own cache lines.
+ */
+ u8 tx_buf[AD4170_SPI_MAX_XFER_LEN] __aligned(IIO_DMA_MINALIGN);
+ u8 rx_buf[4];
+};
+
+static int ad4170_debugfs_reg_access(struct iio_dev *indio_dev,
+ unsigned int reg, unsigned int writeval,
+ unsigned int *readval)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+
+ if (readval)
+ return regmap_read(st->regmap, reg, readval);
+
+ return regmap_write(st->regmap, reg, writeval);
+}
+
+static int ad4170_get_reg_size(struct ad4170_state *st, unsigned int reg,
+ unsigned int *size)
+{
+ if (reg >= ARRAY_SIZE(ad4170_reg_size))
+ return -EINVAL;
+
+ *size = ad4170_reg_size[reg];
+
+ return 0;
+}
+
+static int ad4170_reg_write(void *context, unsigned int reg, unsigned int val)
+{
+ struct ad4170_state *st = context;
+ unsigned int size;
+ int ret;
+
+ ret = ad4170_get_reg_size(st, reg, &size);
+ if (ret)
+ return ret;
+
+ put_unaligned_be16(reg, st->tx_buf);
+ switch (size) {
+ case 3:
+ put_unaligned_be24(val, &st->tx_buf[2]);
+ break;
+ case 2:
+ put_unaligned_be16(val, &st->tx_buf[2]);
+ break;
+ case 1:
+ st->tx_buf[2] = val;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return spi_write(st->spi, st->tx_buf, size + 2);
+}
+
+static int ad4170_reg_read(void *context, unsigned int reg, unsigned int *val)
+{
+ struct ad4170_state *st = context;
+ struct spi_transfer t[] = {
+ {
+ .tx_buf = st->tx_buf,
+ .len = 2,
+ },
+ {
+ .rx_buf = st->rx_buf,
+ },
+ };
+ unsigned int size;
+ int ret;
+
+ ret = ad4170_get_reg_size(st, reg, &size);
+ if (ret)
+ return ret;
+
+ put_unaligned_be16(AD4170_REG_READ_MASK | reg, st->tx_buf);
+ t[1].len = size;
+
+ ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
+ if (ret)
+ return ret;
+
+ switch (size) {
+ case 3:
+ *val = get_unaligned_be24(st->rx_buf);
+ return 0;
+ case 2:
+ *val = get_unaligned_be16(st->rx_buf);
+ return 0;
+ case 1:
+ *val = st->rx_buf[0];
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
+static const struct regmap_config ad4170_regmap_config = {
+ .reg_read = ad4170_reg_read,
+ .reg_write = ad4170_reg_write,
+};
+
+static bool ad4170_setup_eq(struct ad4170_setup *a, struct ad4170_setup *b)
+{
+ /*
+ * The use of static_assert() here is to make sure that, if
+ * struct ad4170_setup is ever changed (e.g. a field is added to the
+ * struct's declaration), the comparison below is adapted to keep
+ * comparing each of struct ad4170_setup fields.
+ */
+ static_assert(sizeof(*a) ==
+ sizeof(struct {
+ u16 misc;
+ u16 afe;
+ u16 filter;
+ u16 filter_fs;
+ u32 offset;
+ u32 gain;
+ }));
+
+ if (a->misc != b->misc ||
+ a->afe != b->afe ||
+ a->filter != b->filter ||
+ a->filter_fs != b->filter_fs ||
+ a->offset != b->offset ||
+ a->gain != b->gain)
+ return false;
+
+ return true;
+}
+
+static int ad4170_find_setup(struct ad4170_state *st,
+ struct ad4170_setup *target_setup,
+ unsigned int *setup_num, bool *overwrite)
+{
+ unsigned int i;
+
+ *setup_num = AD4170_INVALID_SETUP;
+ *overwrite = false;
+
+ for (i = 0; i < AD4170_MAX_SETUPS; i++) {
+ struct ad4170_setup_info *setup_info = &st->setup_infos[i];
+
+ /* Immediately accept a matching setup. */
+ if (ad4170_setup_eq(target_setup, &setup_info->setup)) {
+ *setup_num = i;
+ return 0;
+ }
+
+ /* Ignore all setups which are used by enabled channels. */
+ if (setup_info->enabled_channels)
+ continue;
+
+ /* Find the least used slot. */
+ if (*setup_num == AD4170_INVALID_SETUP ||
+ setup_info->channels < st->setup_infos[*setup_num].channels)
+ *setup_num = i;
+ }
+
+ if (*setup_num == AD4170_INVALID_SETUP)
+ return -EINVAL;
+
+ *overwrite = true;
+ return 0;
+}
+
+static void ad4170_unlink_channel(struct ad4170_state *st, unsigned int channel)
+{
+ struct ad4170_chan_info *chan_info = &st->chan_infos[channel];
+ struct ad4170_setup_info *setup_info = &st->setup_infos[chan_info->setup_num];
+
+ chan_info->setup_num = AD4170_INVALID_SETUP;
+ setup_info->channels--;
+}
+
+static int ad4170_unlink_setup(struct ad4170_state *st, unsigned int setup_num)
+{
+ unsigned int i;
+
+ for (i = 0; i < AD4170_MAX_CHANNELS; i++) {
+ struct ad4170_chan_info *chan_info = &st->chan_infos[i];
+
+ if (!chan_info->initialized || chan_info->setup_num != setup_num)
+ continue;
+
+ ad4170_unlink_channel(st, i);
+ }
+ return 0;
+}
+
+static int ad4170_link_channel_setup(struct ad4170_state *st,
+ unsigned int chan_addr,
+ unsigned int setup_num)
+{
+ struct ad4170_setup_info *setup_info = &st->setup_infos[setup_num];
+ struct ad4170_chan_info *chan_info = &st->chan_infos[chan_addr];
+ int ret;
+
+ ret = regmap_update_bits(st->regmap, AD4170_CHAN_SETUP_REG(chan_addr),
+ AD4170_CHAN_SETUP_SETUP_MSK,
+ FIELD_PREP(AD4170_CHAN_SETUP_SETUP_MSK, setup_num));
+ if (ret)
+ return ret;
+
+ chan_info->setup_num = setup_num;
+ setup_info->channels++;
+ return 0;
+}
+
+static int ad4170_write_setup(struct ad4170_state *st, unsigned int setup_num,
+ struct ad4170_setup *setup)
+{
+ int ret;
+
+ /*
+ * It is recommended to place the ADC in standby mode or idle mode to
+ * write to OFFSET and GAIN registers.
+ */
+ ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG,
+ AD4170_ADC_CTRL_MODE_MSK,
+ FIELD_PREP(AD4170_ADC_CTRL_MODE_MSK,
+ AD4170_ADC_CTRL_MODE_IDLE));
+ if (ret)
+ return ret;
+
+ ret = regmap_write(st->regmap, AD4170_MISC_REG(setup_num), setup->misc);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(st->regmap, AD4170_AFE_REG(setup_num), setup->afe);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(st->regmap, AD4170_FILTER_REG(setup_num),
+ setup->filter);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(st->regmap, AD4170_FILTER_FS_REG(setup_num),
+ setup->filter_fs);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(st->regmap, AD4170_OFFSET_REG(setup_num),
+ setup->offset);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(st->regmap, AD4170_GAIN_REG(setup_num), setup->gain);
+ if (ret)
+ return ret;
+
+ memcpy(&st->setup_infos[setup_num].setup, setup, sizeof(*setup));
+ return 0;
+}
+
+static int ad4170_write_channel_setup(struct ad4170_state *st,
+ unsigned int chan_addr, bool on_enable)
+{
+ struct ad4170_chan_info *chan_info = &st->chan_infos[chan_addr];
+ bool overwrite;
+ int setup_num;
+ int ret;
+
+ /*
+ * Similar to AD4130 driver, the following cases need to be handled.
+ *
+ * 1. Enabled and linked channel with setup changes:
+ * - Find a setup. If not possible, return error.
+ * - Unlink channel from current setup.
+ * - If the setup found has only disabled channels linked to it,
+ * unlink all channels, and write the new setup to it.
+ * - Link channel to new setup.
+ *
+ * 2. Soon to be enabled and unlinked channel:
+ * - Find a setup. If not possible, return error.
+ * - If the setup found has only disabled channels linked to it,
+ * unlink all channels, and write the new setup to it.
+ * - Link channel to the setup.
+ *
+ * 3. Disabled and linked channel with setup changes:
+ * - Unlink channel from current setup.
+ *
+ * 4. Soon to be enabled and linked channel:
+ * 5. Disabled and unlinked channel with setup changes:
+ * - Do nothing.
+ */
+
+ /* Cases 3, 4, and 5 */
+ if (chan_info->setup_num != AD4170_INVALID_SETUP) {
+ /* Case 4 */
+ if (on_enable)
+ return 0;
+
+ /* Case 3 */
+ if (!chan_info->enabled) {
+ ad4170_unlink_channel(st, chan_addr);
+ return 0;
+ }
+ } else if (!on_enable && !chan_info->enabled) {
+ /* Case 5 */
+ return 0;
+ }
+
+ /* Cases 1 & 2 */
+ ret = ad4170_find_setup(st, &chan_info->setup, &setup_num, &overwrite);
+ if (ret)
+ return ret;
+
+ if (chan_info->setup_num != AD4170_INVALID_SETUP)
+ /* Case 1 */
+ ad4170_unlink_channel(st, chan_addr);
+
+ if (overwrite) {
+ ret = ad4170_unlink_setup(st, setup_num);
+ if (ret)
+ return ret;
+
+ ret = ad4170_write_setup(st, setup_num, &chan_info->setup);
+ if (ret)
+ return ret;
+ }
+
+ return ad4170_link_channel_setup(st, chan_addr, setup_num);
+}
+
+static int ad4170_set_channel_enable(struct ad4170_state *st,
+ unsigned int chan_addr, bool status)
+{
+ struct ad4170_chan_info *chan_info = &st->chan_infos[chan_addr];
+ struct ad4170_setup_info *setup_info;
+ int ret;
+
+ if (chan_info->enabled == status)
+ return 0;
+
+ if (status) {
+ ret = ad4170_write_channel_setup(st, chan_addr, true);
+ if (ret)
+ return ret;
+ }
+
+ setup_info = &st->setup_infos[chan_info->setup_num];
+
+ ret = regmap_update_bits(st->regmap, AD4170_CHAN_EN_REG,
+ AD4170_CHAN_EN(chan_addr),
+ status ? AD4170_CHAN_EN(chan_addr) : 0);
+ if (ret)
+ return ret;
+
+ setup_info->enabled_channels += status ? 1 : -1;
+ chan_info->enabled = status;
+ return 0;
+}
+
+static const struct iio_chan_spec ad4170_channel_template = {
+ .type = IIO_VOLTAGE,
+ .indexed = 1,
+ .differential = 1,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
+ BIT(IIO_CHAN_INFO_SCALE) |
+ BIT(IIO_CHAN_INFO_OFFSET),
+ .info_mask_separate_available = BIT(IIO_CHAN_INFO_SCALE),
+ .scan_type = {
+ .realbits = 24,
+ .storagebits = 32,
+ .endianness = IIO_BE,
+ },
+};
+
+/*
+ * Receives the number of a multiplexed AD4170 input (ain_n), and stores the
+ * voltage (in µV) of the specified input into ain_voltage. If the input number
+ * is a ordinary analog input (AIN0 to AIN8), stores zero into ain_voltage.
+ * If a voltage regulator required by a special input is unavailable, return
+ * error code. Return 0 on success.
+ */
+static int ad4170_get_ain_voltage_uv(struct ad4170_state *st, int ain_n,
+ int *ain_voltage)
+{
+ struct device *dev = &st->spi->dev;
+ int v_diff;
+
+ *ain_voltage = 0;
+ if (ain_n <= AD4170_CHAN_MAP_TEMP_SENSOR)
+ return 0;
+
+ switch (ain_n) {
+ case AD4170_CHAN_MAP_AVDD_AVSS_N:
+ v_diff = st->vrefs_uv[AD4170_AVDD_SUP] - st->vrefs_uv[AD4170_AVSS_SUP];
+ *ain_voltage = v_diff / 5;
+ return 0;
+ case AD4170_CHAN_MAP_IOVDD_DGND_N:
+ *ain_voltage = st->vrefs_uv[AD4170_IOVDD_SUP] / 5;
+ return 0;
+ case AD4170_CHAN_MAP_AVSS:
+ *ain_voltage = st->vrefs_uv[AD4170_AVSS_SUP];
+ return 0;
+ case AD4170_CHAN_MAP_DGND:
+ *ain_voltage = 0;
+ return 0;
+ case AD4170_CHAN_MAP_REFIN1_P:
+ if (st->vrefs_uv[AD4170_REFIN1P_SUP] == -ENODEV)
+ return dev_err_probe(dev, -ENODEV,
+ "input set to REFIN+ but ref not provided\n");
+
+ *ain_voltage = st->vrefs_uv[AD4170_REFIN1P_SUP];
+ return 0;
+ case AD4170_CHAN_MAP_REFIN1_N:
+ if (st->vrefs_uv[AD4170_REFIN1N_SUP] == -ENODEV)
+ return dev_err_probe(dev, -ENODEV,
+ "input set to REFIN- but ref not provided\n");
+
+ *ain_voltage = st->vrefs_uv[AD4170_REFIN1N_SUP];
+ return 0;
+ case AD4170_CHAN_MAP_REFIN2_P:
+ if (st->vrefs_uv[AD4170_REFIN2P_SUP] == -ENODEV)
+ return dev_err_probe(dev, -ENODEV,
+ "input set to REFIN2+ but ref not provided\n");
+
+ *ain_voltage = st->vrefs_uv[AD4170_REFIN2P_SUP];
+ return 0;
+ case AD4170_CHAN_MAP_REFIN2_N:
+ if (st->vrefs_uv[AD4170_REFIN2N_SUP] == -ENODEV)
+ return dev_err_probe(dev, -ENODEV,
+ "input set to REFIN2- but ref not provided\n");
+
+ *ain_voltage = st->vrefs_uv[AD4170_REFIN2N_SUP];
+ return 0;
+ case AD4170_CHAN_MAP_REFOUT:
+ /* REFOUT is 2.5V relative to AVSS so take that into account */
+ *ain_voltage = st->vrefs_uv[AD4170_AVSS_SUP] + AD4170_INT_REF_2_5V;
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int ad4170_validate_channel_input(struct ad4170_state *st, int pin, bool com)
+{
+ /* Check common-mode input pin is mapped to a special input. */
+ if (com && (pin < AD4170_CHAN_MAP_AVDD_AVSS_P || pin > AD4170_CHAN_MAP_REFOUT))
+ return dev_err_probe(&st->spi->dev, -EINVAL,
+ "Invalid common-mode input pin number. %d\n",
+ pin);
+
+ /* Check differential input pin is mapped to a analog input pin. */
+ if (!com && pin > AD4170_MAX_ANALOG_PINS)
+ return dev_err_probe(&st->spi->dev, -EINVAL,
+ "Invalid analog input pin number. %d\n",
+ pin);
+
+ return 0;
+}
+
+/*
+ * Verifies whether the channel input configuration is valid by checking the
+ * input numbers.
+ * Returns 0 on valid channel input configuration. -EINVAL otherwise.
+ */
+static int ad4170_validate_channel(struct ad4170_state *st,
+ struct iio_chan_spec const *chan)
+{
+ int ret;
+
+ ret = ad4170_validate_channel_input(st, chan->channel, false);
+ if (ret)
+ return ret;
+
+ return ad4170_validate_channel_input(st, chan->channel2,
+ !chan->differential);
+}
+
+/*
+ * Verifies whether the channel configuration is valid by checking the provided
+ * input type, polarity, and voltage references result in a sane input range.
+ * Returns negative error code on failure.
+ */
+static int ad4170_get_input_range(struct ad4170_state *st,
+ struct iio_chan_spec const *chan,
+ unsigned int ch_reg, unsigned int ref_sel)
+{
+ bool bipolar = chan->scan_type.sign == 's';
+ struct device *dev = &st->spi->dev;
+ int refp, refn, ain_voltage, ret;
+
+ switch (ref_sel) {
+ case AD4170_REF_REFIN1:
+ if (st->vrefs_uv[AD4170_REFIN1P_SUP] == -ENODEV ||
+ st->vrefs_uv[AD4170_REFIN1N_SUP] == -ENODEV)
+ return dev_err_probe(dev, -ENODEV,
+ "REFIN± selected but not provided\n");
+
+ refp = st->vrefs_uv[AD4170_REFIN1P_SUP];
+ refn = st->vrefs_uv[AD4170_REFIN1N_SUP];
+ break;
+ case AD4170_REF_REFIN2:
+ if (st->vrefs_uv[AD4170_REFIN2P_SUP] == -ENODEV ||
+ st->vrefs_uv[AD4170_REFIN2N_SUP] == -ENODEV)
+ return dev_err_probe(dev, -ENODEV,
+ "REFIN2± selected but not provided\n");
+
+ refp = st->vrefs_uv[AD4170_REFIN2P_SUP];
+ refn = st->vrefs_uv[AD4170_REFIN2N_SUP];
+ break;
+ case AD4170_REF_AVDD:
+ refp = st->vrefs_uv[AD4170_AVDD_SUP];
+ refn = st->vrefs_uv[AD4170_AVSS_SUP];
+ break;
+ case AD4170_REF_REFOUT:
+ /* REFOUT is 2.5 V relative to AVSS */
+ refp = st->vrefs_uv[AD4170_AVSS_SUP] + AD4170_INT_REF_2_5V;
+ refn = st->vrefs_uv[AD4170_AVSS_SUP];
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /*
+ * Find out the analog input range from the channel type, polarity, and
+ * voltage reference selection.
+ * AD4170 channels are either differential or pseudo-differential.
+ * Diff input voltage range: −VREF/gain to +VREF/gain (datasheet page 6)
+ * Pseudo-diff input voltage range: 0 to VREF/gain (datasheet page 6)
+ */
+ if (chan->differential) {
+ if (!bipolar)
+ return dev_err_probe(dev, -EINVAL,
+ "Channel %u differential unipolar\n",
+ ch_reg);
+
+ /*
+ * Differential bipolar channel.
+ * avss-supply is never above 0V.
+ * Assuming refin1n-supply not above 0V.
+ * Assuming refin2n-supply not above 0V.
+ */
+ return refp + abs(refn);
+ }
+ /*
+ * Some configurations can lead to invalid setups.
+ * For example, if AVSS = -2.5V, REF_SELECT set to REFOUT (REFOUT/AVSS),
+ * and pseudo-diff channel configuration set, then the input range
+ * should go from 0V to +VREF (single-ended - datasheet pg 10), but
+ * REFOUT/AVSS range would be -2.5V to 0V.
+ * Check the positive reference is higher than 0V for pseudo-diff
+ * channels.
+ */
+ if (refp <= 0)
+ return dev_err_probe(dev, -EINVAL,
+ "REF+ <= GND for pseudo-diff chan %u\n",
+ ch_reg);
+
+ if (bipolar)
+ return refp;
+
+ /*
+ * Pseudo-differential unipolar channel.
+ * Input expected to swing from IN- to +VREF.
+ */
+ ret = ad4170_get_ain_voltage_uv(st, chan->channel2, &ain_voltage);
+ if (ret)
+ return ret;
+
+ if (refp - ain_voltage <= 0)
+ return dev_err_probe(dev, -EINVAL,
+ "Negative input >= REF+ for pseudo-diff chan %u\n",
+ ch_reg);
+
+ return refp - ain_voltage;
+}
+
+static int __ad4170_read_sample(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan, int *val)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ unsigned long settling_time_ms;
+ int ret;
+
+ reinit_completion(&st->completion);
+ ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG,
+ AD4170_ADC_CTRL_MODE_MSK,
+ FIELD_PREP(AD4170_ADC_CTRL_MODE_MSK,
+ AD4170_ADC_CTRL_MODE_SINGLE));
+ if (ret)
+ return ret;
+
+ /*
+ * When a channel is manually selected by the user, the ADC needs an
+ * extra time to provide the first stable conversion. The ADC settling
+ * time depends on the filter type, filter frequency, and ADC clock
+ * frequency (see datasheet page 53). The maximum settling time among
+ * all filter configurations is 6291164 / fCLK. Use that formula to wait
+ * for sufficient time whatever the filter configuration may be.
+ */
+ settling_time_ms = DIV_ROUND_UP(6291164 * MILLI, st->mclk_hz);
+ ret = wait_for_completion_timeout(&st->completion,
+ msecs_to_jiffies(settling_time_ms));
+ if (!ret)
+ dev_dbg(&st->spi->dev,
+ "No Data Ready signal. Reading after delay.\n");
+
+ ret = regmap_read(st->regmap, AD4170_DATA_24B_REG, val);
+ if (ret)
+ return ret;
+
+ if (chan->scan_type.sign == 's')
+ *val = sign_extend32(*val, chan->scan_type.realbits - 1);
+
+ return 0;
+}
+
+static int ad4170_read_sample(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan, int *val)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ struct device *dev = &st->spi->dev;
+ int ret, ret2;
+
+ /*
+ * The ADC sequences through all enabled channels. That can lead to
+ * incorrect channel being sampled if a previous read would have left a
+ * different channel enabled. Thus, always enable and disable the
+ * channel on single-shot read.
+ */
+ ret = ad4170_set_channel_enable(st, chan->address, true);
+ if (ret)
+ return ret;
+
+ ret = __ad4170_read_sample(indio_dev, chan, val);
+ if (ret) {
+ dev_err(dev, "failed to read sample: %d\n", ret);
+
+ ret2 = ad4170_set_channel_enable(st, chan->address, false);
+ if (ret2)
+ dev_err(dev, "failed to disable channel: %d\n", ret2);
+
+ return ret;
+ }
+
+ ret = ad4170_set_channel_enable(st, chan->address, false);
+ if (ret)
+ return ret;
+
+ return IIO_VAL_INT;
+}
+
+static int ad4170_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val, int *val2, long info)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
+ struct ad4170_setup *setup = &chan_info->setup;
+ unsigned int pga;
+ int ret;
+
+ guard(mutex)(&st->lock);
+ switch (info) {
+ case IIO_CHAN_INFO_RAW:
+ if (!iio_device_claim_direct(indio_dev))
+ return -EBUSY;
+
+ ret = ad4170_read_sample(indio_dev, chan, val);
+ iio_device_release_direct(indio_dev);
+ return ret;
+ case IIO_CHAN_INFO_SCALE:
+ pga = FIELD_GET(AD4170_AFE_PGA_GAIN_MSK, setup->afe);
+ *val = chan_info->scale_tbl[pga][0];
+ *val2 = chan_info->scale_tbl[pga][1];
+ return IIO_VAL_INT_PLUS_NANO;
+ case IIO_CHAN_INFO_OFFSET:
+ pga = FIELD_GET(AD4170_AFE_PGA_GAIN_MSK, setup->afe);
+ *val = chan_info->offset_tbl[pga];
+ return IIO_VAL_INT;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int ad4170_fill_scale_tbl(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
+ struct device *dev = &st->spi->dev;
+ int bipolar = chan->scan_type.sign == 's' ? 1 : 0;
+ int precision_bits = chan->scan_type.realbits;
+ int pga, ainm_voltage, ret;
+ unsigned long long offset;
+
+ ainm_voltage = 0;
+ ret = ad4170_get_ain_voltage_uv(st, chan->channel2, &ainm_voltage);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to fill scale table\n");
+
+ for (pga = 0; pga < AD4170_NUM_PGA_OPTIONS; pga++) {
+ u64 nv;
+ unsigned int lshift, rshift;
+
+ /*
+ * The PGA options are numbered from 0 to 9, with option 0 being
+ * a gain of 2^0 (no actual gain), and 7 meaning a gain of 2^7.
+ * Option 8, though, sets a gain of 0.5, so the input signal can
+ * be attenuated by 2 rather than amplified. Option 9, allows
+ * the signal to bypass the PGA circuitry (no gain).
+ *
+ * The scale factor to get ADC output codes to values in mV
+ * units is given by:
+ * _scale = (input_range / gain) / 2^precision
+ * AD4170 gain is a power of 2 so the above can be written as
+ * _scale = input_range / 2^(precision + gain)
+ * Keep the input range in µV to avoid truncating the less
+ * significan bits when right shifting it so to preserve scale
+ * precision.
+ */
+ nv = (u64)chan_info->input_range_uv * NANO;
+ lshift = !!(pga & BIT(3)); /* handle options 8 and 9 */
+ rshift = precision_bits - bipolar + (pga & GENMASK(2, 0)) - lshift;
+ chan_info->scale_tbl[pga][0] = 0;
+ chan_info->scale_tbl[pga][1] = div_u64(nv >> rshift, MILLI);
+
+ /*
+ * If the negative input is not at GND, the conversion result
+ * (which is relative to IN-) will be offset by the level at IN-.
+ * Use the scale factor the other way around to go from a known
+ * voltage to the corresponding ADC output code.
+ * With that, we are able to get to what would be the output
+ * code for the voltage at the negative input.
+ * If the negative input is not fixed, there is no offset.
+ */
+ offset = ((unsigned long long)abs(ainm_voltage)) * MICRO;
+ offset = DIV_ROUND_CLOSEST_ULL(offset, chan_info->scale_tbl[pga][1]);
+
+ /*
+ * After divided by the scale, offset will always fit into 31
+ * bits. For _raw + _offset to be relative to GND, the value
+ * provided as _offset is of opposite sign than the real offset.
+ */
+ if (ainm_voltage > 0)
+ chan_info->offset_tbl[pga] = -(int)(offset);
+ else
+ chan_info->offset_tbl[pga] = (int)(offset);
+ }
+ return 0;
+}
+
+static int ad4170_read_avail(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ const int **vals, int *type, int *length,
+ long info)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
+
+ switch (info) {
+ case IIO_CHAN_INFO_SCALE:
+ *vals = (int *)chan_info->scale_tbl;
+ *length = ARRAY_SIZE(chan_info->scale_tbl) * 2;
+ *type = IIO_VAL_INT_PLUS_NANO;
+ return IIO_AVAIL_LIST;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int ad4170_set_pga(struct ad4170_state *st,
+ struct iio_chan_spec const *chan, int val, int val2)
+{
+ struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
+ struct ad4170_setup *setup = &chan_info->setup;
+ unsigned int pga;
+
+ for (pga = 0; pga < AD4170_NUM_PGA_OPTIONS; pga++) {
+ if (val == chan_info->scale_tbl[pga][0] &&
+ val2 == chan_info->scale_tbl[pga][1])
+ break;
+ }
+
+ if (pga == AD4170_NUM_PGA_OPTIONS)
+ return -EINVAL;
+
+ guard(mutex)(&st->lock);
+ setup->afe &= ~AD4170_AFE_PGA_GAIN_MSK;
+ setup->afe |= FIELD_PREP(AD4170_AFE_PGA_GAIN_MSK, pga);
+
+ return ad4170_write_channel_setup(st, chan->address, false);
+}
+
+static int __ad4170_write_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan, int val,
+ int val2, long info)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+
+ switch (info) {
+ case IIO_CHAN_INFO_SCALE:
+ return ad4170_set_pga(st, chan, val, val2);
+ default:
+ return -EINVAL;
+ }
+}
+
+static int ad4170_write_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan, int val,
+ int val2, long info)
+{
+ int ret;
+
+ if (!iio_device_claim_direct(indio_dev))
+ return -EBUSY;
+
+ ret = __ad4170_write_raw(indio_dev, chan, val, val2, info);
+ iio_device_release_direct(indio_dev);
+ return ret;
+}
+
+static int ad4170_write_raw_get_fmt(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ long info)
+{
+ switch (info) {
+ case IIO_CHAN_INFO_SCALE:
+ return IIO_VAL_INT_PLUS_NANO;
+ default:
+ return -EINVAL;
+ }
+}
+
+static const struct iio_info ad4170_info = {
+ .read_raw = ad4170_read_raw,
+ .read_avail = ad4170_read_avail,
+ .write_raw = ad4170_write_raw,
+ .write_raw_get_fmt = ad4170_write_raw_get_fmt,
+ .debugfs_reg_access = ad4170_debugfs_reg_access,
+};
+
+static int ad4170_soft_reset(struct ad4170_state *st)
+{
+ int ret;
+
+ ret = regmap_write(st->regmap, AD4170_CONFIG_A_REG,
+ AD4170_SW_RESET_MSK);
+ if (ret)
+ return ret;
+
+ /* AD4170-4 requires 1 ms between reset and any register access. */
+ fsleep(1 * USEC_PER_MSEC);
+
+ return 0;
+}
+
+static int ad4170_parse_reference(struct ad4170_state *st,
+ struct fwnode_handle *child,
+ struct ad4170_setup *setup)
+{
+ struct device *dev = &st->spi->dev;
+ u32 aux;
+
+ /* Optional positive reference buffering */
+ aux = AD4170_REF_BUF_FULL; /* Default to full precharge buffer enabled. */
+ fwnode_property_read_u32(child, "adi,positive-reference-buffer", &aux);
+ if (aux < AD4170_REF_BUF_PRE || aux > AD4170_REF_BUF_BYPASS)
+ return dev_err_probe(dev, -EINVAL,
+ "Invalid adi,positive-reference-buffer: %u\n",
+ aux);
+
+ setup->afe |= FIELD_PREP(AD4170_AFE_REF_BUF_P_MSK, aux);
+
+ /* Optional negative reference buffering */
+ aux = AD4170_REF_BUF_FULL; /* Default to full precharge buffer enabled. */
+ fwnode_property_read_u32(child, "adi,negative-reference-buffer", &aux);
+ if (aux < AD4170_REF_BUF_PRE || aux > AD4170_REF_BUF_BYPASS)
+ return dev_err_probe(dev, -EINVAL,
+ "Invalid adi,negative-reference-buffer: %u\n",
+ aux);
+
+ setup->afe |= FIELD_PREP(AD4170_AFE_REF_BUF_M_MSK, aux);
+
+ /* Optional voltage reference selection */
+ aux = AD4170_REF_REFOUT; /* Default reference selection. */
+ fwnode_property_read_u32(child, "adi,reference-select", &aux);
+ if (aux > AD4170_REF_AVDD)
+ return dev_err_probe(dev, -EINVAL,
+ "Invalid reference selected %u\n",
+ aux);
+
+ setup->afe |= FIELD_PREP(AD4170_AFE_REF_SELECT_MSK, aux);
+
+ return 0;
+}
+
+static int ad4170_parse_adc_channel_type(struct device *dev,
+ struct fwnode_handle *child,
+ struct iio_chan_spec *chan)
+{
+ int ret, ret2;
+ u32 pins[2];
+
+ /* Parse pseudo-differential channel configuration */
+ ret = fwnode_property_read_u32(child, "single-channel", &pins[0]);
+ ret2 = fwnode_property_read_u32(child, "common-mode-channel", &pins[1]);
+ if (!ret && ret2)
+ return dev_err_probe(dev, ret,
+ "single-ended channels must define common-mode-channel\n");
+
+ if (!ret && !ret2) {
+ chan->differential = false;
+ chan->channel = pins[0];
+ chan->channel2 = pins[1];
+ return 0;
+ }
+ /* Failed to parse pseudo-diff chan props so try diff chan */
+
+ /* Parse differential channel configuration */
+ ret = fwnode_property_read_u32_array(child, "diff-channels", pins,
+ ARRAY_SIZE(pins));
+ if (!ret) {
+ chan->differential = true;
+ chan->channel = pins[0];
+ chan->channel2 = pins[1];
+ return 0;
+ }
+ return dev_err_probe(dev, ret,
+ "Channel must define one of diff-channels or single-channel.\n");
+}
+
+static int ad4170_parse_channel_node(struct iio_dev *indio_dev,
+ struct fwnode_handle *child,
+ unsigned int chan_num)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ struct device *dev = &st->spi->dev;
+ struct ad4170_chan_info *chan_info;
+ struct ad4170_setup *setup;
+ struct iio_chan_spec *chan;
+ unsigned int ref_select;
+ unsigned int ch_reg;
+ bool bipolar;
+ int ret;
+
+ ret = fwnode_property_read_u32(child, "reg", &ch_reg);
+ if (ret)
+ return dev_err_probe(dev, -EINVAL,
+ "Failed to read channel reg\n");
+
+ if (ch_reg >= AD4170_MAX_CHANNELS)
+ return dev_err_probe(dev, -EINVAL,
+ "Channel idx greater than no of channels\n");
+
+ chan = &st->chans[chan_num];
+ *chan = ad4170_channel_template;
+
+ chan->address = ch_reg;
+ chan->scan_index = ch_reg;
+ chan_info = &st->chan_infos[chan->address];
+
+ chan_info->setup_num = AD4170_INVALID_SETUP;
+ chan_info->initialized = true;
+
+ setup = &chan_info->setup;
+ ret = ad4170_parse_reference(st, child, setup);
+ if (ret)
+ return ret;
+
+ ret = ad4170_parse_adc_channel_type(dev, child, chan);
+ if (ret < 0)
+ return ret;
+
+ bipolar = fwnode_property_read_bool(child, "bipolar");
+ setup->afe |= FIELD_PREP(AD4170_AFE_BIPOLAR_MSK, bipolar);
+ if (bipolar)
+ chan->scan_type.sign = 's';
+ else
+ chan->scan_type.sign = 'u';
+
+ ret = ad4170_validate_channel(st, chan);
+ if (ret < 0)
+ return ret;
+
+ ref_select = FIELD_GET(AD4170_AFE_REF_SELECT_MSK, setup->afe);
+ ret = ad4170_get_input_range(st, chan, ch_reg, ref_select);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Invalid input config\n");
+
+ chan_info->input_range_uv = ret;
+ return 0;
+}
+
+static int ad4170_parse_channels(struct iio_dev *indio_dev)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ struct device *dev = &st->spi->dev;
+ unsigned int num_channels;
+ unsigned int chan_num = 0;
+ int ret;
+
+ num_channels = device_get_child_node_count(dev);
+
+ if (num_channels > AD4170_MAX_CHANNELS)
+ return dev_err_probe(dev, -EINVAL, "Too many channels\n");
+
+ device_for_each_child_node_scoped(dev, child) {
+ ret = ad4170_parse_channel_node(indio_dev, child, chan_num++);
+ if (ret)
+ return ret;
+ }
+
+ indio_dev->num_channels = num_channels;
+ indio_dev->channels = st->chans;
+
+ return 0;
+}
+
+static int ad4170_parse_firmware(struct iio_dev *indio_dev)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ struct device *dev = &st->spi->dev;
+ int reg_data, ret;
+
+ st->mclk_hz = AD4170_INT_CLOCK_16MHZ;
+
+ /* On power on, device defaults to using SDO pin for data ready signal */
+ st->int_pin_sel = AD4170_INT_PIN_SDO;
+ ret = device_property_match_property_string(dev, "interrupt-names",
+ ad4170_int_pin_names,
+ ARRAY_SIZE(ad4170_int_pin_names));
+ if (ret >= 0)
+ st->int_pin_sel = ret;
+
+ reg_data = FIELD_PREP(AD4170_PIN_MUXING_DIG_AUX1_CTRL_MSK,
+ st->int_pin_sel == AD4170_INT_PIN_DIG_AUX1 ?
+ AD4170_PIN_MUXING_DIG_AUX1_RDY :
+ AD4170_PIN_MUXING_DIG_AUX1_DISABLED);
+
+ ret = regmap_update_bits(st->regmap, AD4170_PIN_MUXING_REG,
+ AD4170_PIN_MUXING_DIG_AUX1_CTRL_MSK, reg_data);
+ if (ret)
+ return ret;
+
+ return ad4170_parse_channels(indio_dev);
+}
+
+static int ad4170_initial_config(struct iio_dev *indio_dev)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ struct device *dev = &st->spi->dev;
+ unsigned int i;
+ int ret;
+
+ ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG,
+ AD4170_ADC_CTRL_MODE_MSK,
+ FIELD_PREP(AD4170_ADC_CTRL_MODE_MSK,
+ AD4170_ADC_CTRL_MODE_IDLE));
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to set ADC mode to idle\n");
+
+ for (i = 0; i < indio_dev->num_channels; i++) {
+ struct ad4170_chan_info *chan_info;
+ struct iio_chan_spec const *chan;
+ struct ad4170_setup *setup;
+ unsigned int val;
+
+ chan = &indio_dev->channels[i];
+ chan_info = &st->chan_infos[chan->address];
+
+ setup = &chan_info->setup;
+ setup->gain = AD4170_GAIN_REG_DEFAULT;
+ ret = ad4170_write_channel_setup(st, chan->address, false);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to write channel setup\n");
+
+ val = FIELD_PREP(AD4170_CHAN_MAP_AINP_MSK, chan->channel) |
+ FIELD_PREP(AD4170_CHAN_MAP_AINM_MSK, chan->channel2);
+
+ ret = regmap_write(st->regmap, AD4170_CHAN_MAP_REG(i), val);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to write CHAN_MAP_REG\n");
+
+ ret = ad4170_fill_scale_tbl(indio_dev, chan);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to fill scale tbl\n");
+ }
+
+ /* Disable all channels to avoid reading from unexpected channel */
+ ret = regmap_write(st->regmap, AD4170_CHAN_EN_REG, 0);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to disable channels\n");
+
+ /*
+ * Configure channels to share the same data output register, i.e. data
+ * can be read from the same register address regardless of channel
+ * number.
+ */
+ return regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG,
+ AD4170_ADC_CTRL_MULTI_DATA_REG_SEL_MSK,
+ AD4170_ADC_CTRL_MULTI_DATA_REG_SEL_MSK);
+}
+
+static irqreturn_t ad4170_irq_handler(int irq, void *dev_id)
+{
+ struct iio_dev *indio_dev = dev_id;
+ struct ad4170_state *st = iio_priv(indio_dev);
+
+ complete(&st->completion);
+
+ return IRQ_HANDLED;
+};
+
+static int ad4170_regulator_setup(struct ad4170_state *st)
+{
+ struct device *dev = &st->spi->dev;
+ int ret;
+
+ /* Required regulators */
+ ret = devm_regulator_get_enable_read_voltage(dev, "avdd");
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to get AVDD voltage.\n");
+
+ st->vrefs_uv[AD4170_AVDD_SUP] = ret;
+
+ ret = devm_regulator_get_enable_read_voltage(dev, "iovdd");
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to get IOVDD voltage.\n");
+
+ st->vrefs_uv[AD4170_IOVDD_SUP] = ret;
+
+ /* Optional regulators */
+ ret = devm_regulator_get_enable_read_voltage(dev, "avss");
+ if (ret < 0 && ret != -ENODEV)
+ return dev_err_probe(dev, ret, "Failed to get AVSS voltage.\n");
+
+ /* Assume AVSS at GND (0V) if not provided */
+ st->vrefs_uv[AD4170_AVSS_SUP] = ret == -ENODEV ? 0 : -ret;
+
+ ret = devm_regulator_get_enable_read_voltage(dev, "refin1p");
+ if (ret < 0 && ret != -ENODEV)
+ return dev_err_probe(dev, ret, "Failed to get REFIN+ voltage.\n");
+
+ st->vrefs_uv[AD4170_REFIN1P_SUP] = ret;
+
+ ret = devm_regulator_get_enable_read_voltage(dev, "refin1n");
+ if (ret < 0 && ret != -ENODEV)
+ return dev_err_probe(dev, ret, "Failed to get REFIN- voltage.\n");
+
+ /* Negative supplies are assumed to provide negative voltage */
+ st->vrefs_uv[AD4170_REFIN1N_SUP] = ret == -ENODEV ? -ENODEV : -ret;
+
+ ret = devm_regulator_get_enable_read_voltage(dev, "refin2p");
+ if (ret < 0 && ret != -ENODEV)
+ return dev_err_probe(dev, ret, "Failed to get REFIN2+ voltage.\n");
+
+ st->vrefs_uv[AD4170_REFIN2P_SUP] = ret;
+
+ ret = devm_regulator_get_enable_read_voltage(dev, "refin2n");
+ if (ret < 0 && ret != -ENODEV)
+ return dev_err_probe(dev, ret, "Failed to get REFIN2- voltage.\n");
+
+ /* Negative supplies are assumed to provide negative voltage */
+ st->vrefs_uv[AD4170_REFIN2N_SUP] = ret == -ENODEV ? -ENODEV : -ret;
+
+ return 0;
+}
+
+static int ad4170_probe(struct spi_device *spi)
+{
+ const struct ad4170_chip_info *chip;
+ struct device *dev = &spi->dev;
+ struct iio_dev *indio_dev;
+ struct ad4170_state *st;
+ int ret;
+
+ indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
+ if (!indio_dev)
+ return -ENOMEM;
+
+ st = iio_priv(indio_dev);
+ st->spi = spi;
+
+ ret = devm_mutex_init(dev, &st->lock);
+ if (ret)
+ return ret;
+
+ chip = spi_get_device_match_data(spi);
+ if (!chip)
+ return -EINVAL;
+
+ indio_dev->name = chip->name;
+ indio_dev->info = &ad4170_info;
+
+ st->regmap = devm_regmap_init(dev, NULL, st, &ad4170_regmap_config);
+ if (IS_ERR(st->regmap))
+ return dev_err_probe(dev, PTR_ERR(st->regmap),
+ "Failed to initialize regmap\n");
+
+ ret = ad4170_regulator_setup(st);
+ if (ret)
+ return ret;
+
+ ret = ad4170_soft_reset(st);
+ if (ret)
+ return ret;
+
+ ret = ad4170_parse_firmware(indio_dev);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to parse firmware\n");
+
+ ret = ad4170_initial_config(indio_dev);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to setup device\n");
+
+ init_completion(&st->completion);
+
+ if (spi->irq) {
+ ret = devm_request_irq(dev, spi->irq, &ad4170_irq_handler,
+ IRQF_ONESHOT, indio_dev->name, indio_dev);
+ if (ret)
+ return ret;
+ }
+
+ return devm_iio_device_register(dev, indio_dev);
+}
+
+static const struct spi_device_id ad4170_id_table[] = {
+ { "ad4170", (kernel_ulong_t)&ad4170_chip_info },
+ { "ad4190", (kernel_ulong_t)&ad4190_chip_info },
+ { "ad4195", (kernel_ulong_t)&ad4195_chip_info },
+ { }
+};
+MODULE_DEVICE_TABLE(spi, ad4170_id_table);
+
+static const struct of_device_id ad4170_of_match[] = {
+ { .compatible = "adi,ad4170", .data = &ad4170_chip_info },
+ { .compatible = "adi,ad4190", .data = &ad4190_chip_info },
+ { .compatible = "adi,ad4195", .data = &ad4195_chip_info },
+ { }
+};
+MODULE_DEVICE_TABLE(of, ad4170_of_match);
+
+static struct spi_driver ad4170_driver = {
+ .driver = {
+ .name = "ad4170",
+ .of_match_table = ad4170_of_match,
+ },
+ .probe = ad4170_probe,
+ .id_table = ad4170_id_table,
+};
+module_spi_driver(ad4170_driver);
+
+MODULE_AUTHOR("Ana-Maria Cusco <ana-maria.cusco@analog.com>");
+MODULE_AUTHOR("Marcelo Schmitt <marcelo.schmitt@analog.com>");
+MODULE_DESCRIPTION("Analog Devices AD4170 SPI driver");
+MODULE_LICENSE("GPL");
--
2.47.2
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v5 03/11] iio: adc: ad4170: Add support for calibration gain
2025-06-10 20:30 [PATCH v5 00/11] iio: adc: Add support for AD4170 series of ADCs Marcelo Schmitt
2025-06-10 20:31 ` [PATCH v5 01/11] dt-bindings: iio: adc: Add AD4170 Marcelo Schmitt
2025-06-10 20:31 ` [PATCH v5 02/11] iio: adc: Add basic support for AD4170 Marcelo Schmitt
@ 2025-06-10 20:31 ` Marcelo Schmitt
2025-06-10 20:32 ` [PATCH v5 04/11] iio: adc: ad4170: Add support for calibration bias Marcelo Schmitt
` (8 subsequent siblings)
11 siblings, 0 replies; 35+ messages in thread
From: Marcelo Schmitt @ 2025-06-10 20:31 UTC (permalink / raw)
To: linux-iio, devicetree, linux-gpio, linux-kernel
Cc: jic23, lars, Michael.Hennerich, dlechner, nuno.sa, andy, robh,
krzk+dt, conor+dt, linus.walleij, brgl, marcelo.schmitt1
Add support for ADC calibration gain configuration.
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
Change log v4 -> v5
- Squeezed info_mask_separate additions to reduce change diff.
drivers/iio/adc/ad4170.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/iio/adc/ad4170.c b/drivers/iio/adc/ad4170.c
index d0628430ed14..8e422c76f03a 100644
--- a/drivers/iio/adc/ad4170.c
+++ b/drivers/iio/adc/ad4170.c
@@ -636,6 +636,7 @@ static const struct iio_chan_spec ad4170_channel_template = {
.differential = 1,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE) |
+ BIT(IIO_CHAN_INFO_CALIBSCALE) |
BIT(IIO_CHAN_INFO_OFFSET),
.info_mask_separate_available = BIT(IIO_CHAN_INFO_SCALE),
.scan_type = {
@@ -950,6 +951,9 @@ static int ad4170_read_raw(struct iio_dev *indio_dev,
pga = FIELD_GET(AD4170_AFE_PGA_GAIN_MSK, setup->afe);
*val = chan_info->offset_tbl[pga];
return IIO_VAL_INT;
+ case IIO_CHAN_INFO_CALIBSCALE:
+ *val = setup->gain;
+ return IIO_VAL_INT;
default:
return -EINVAL;
}
@@ -1064,6 +1068,18 @@ static int ad4170_set_pga(struct ad4170_state *st,
return ad4170_write_channel_setup(st, chan->address, false);
}
+static int ad4170_set_calib_gain(struct ad4170_state *st,
+ struct iio_chan_spec const *chan, int val)
+{
+ struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
+ struct ad4170_setup *setup = &chan_info->setup;
+
+ guard(mutex)(&st->lock);
+ setup->gain = val;
+
+ return ad4170_write_channel_setup(st, chan->address, false);
+}
+
static int __ad4170_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val,
int val2, long info)
@@ -1073,6 +1089,8 @@ static int __ad4170_write_raw(struct iio_dev *indio_dev,
switch (info) {
case IIO_CHAN_INFO_SCALE:
return ad4170_set_pga(st, chan, val, val2);
+ case IIO_CHAN_INFO_CALIBSCALE:
+ return ad4170_set_calib_gain(st, chan, val);
default:
return -EINVAL;
}
@@ -1099,6 +1117,8 @@ static int ad4170_write_raw_get_fmt(struct iio_dev *indio_dev,
switch (info) {
case IIO_CHAN_INFO_SCALE:
return IIO_VAL_INT_PLUS_NANO;
+ case IIO_CHAN_INFO_CALIBSCALE:
+ return IIO_VAL_INT;
default:
return -EINVAL;
}
--
2.47.2
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v5 04/11] iio: adc: ad4170: Add support for calibration bias
2025-06-10 20:30 [PATCH v5 00/11] iio: adc: Add support for AD4170 series of ADCs Marcelo Schmitt
` (2 preceding siblings ...)
2025-06-10 20:31 ` [PATCH v5 03/11] iio: adc: ad4170: Add support for calibration gain Marcelo Schmitt
@ 2025-06-10 20:32 ` Marcelo Schmitt
2025-06-10 20:32 ` [PATCH v5 05/11] iio: adc: ad4170: Add digital filter and sample frequency config support Marcelo Schmitt
` (7 subsequent siblings)
11 siblings, 0 replies; 35+ messages in thread
From: Marcelo Schmitt @ 2025-06-10 20:32 UTC (permalink / raw)
To: linux-iio, devicetree, linux-gpio, linux-kernel
Cc: jic23, lars, Michael.Hennerich, dlechner, nuno.sa, andy, robh,
krzk+dt, conor+dt, linus.walleij, brgl, marcelo.schmitt1
Add support for ADC calibration bias/offset configuration.
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
Change log v4 -> v5
- Squeezed info_mask_separate additions to reduce change diff.
drivers/iio/adc/ad4170.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/iio/adc/ad4170.c b/drivers/iio/adc/ad4170.c
index 8e422c76f03a..d0482f3b6f01 100644
--- a/drivers/iio/adc/ad4170.c
+++ b/drivers/iio/adc/ad4170.c
@@ -636,6 +636,7 @@ static const struct iio_chan_spec ad4170_channel_template = {
.differential = 1,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE) |
+ BIT(IIO_CHAN_INFO_CALIBBIAS) |
BIT(IIO_CHAN_INFO_CALIBSCALE) |
BIT(IIO_CHAN_INFO_OFFSET),
.info_mask_separate_available = BIT(IIO_CHAN_INFO_SCALE),
@@ -951,6 +952,9 @@ static int ad4170_read_raw(struct iio_dev *indio_dev,
pga = FIELD_GET(AD4170_AFE_PGA_GAIN_MSK, setup->afe);
*val = chan_info->offset_tbl[pga];
return IIO_VAL_INT;
+ case IIO_CHAN_INFO_CALIBBIAS:
+ *val = setup->offset;
+ return IIO_VAL_INT;
case IIO_CHAN_INFO_CALIBSCALE:
*val = setup->gain;
return IIO_VAL_INT;
@@ -1068,6 +1072,18 @@ static int ad4170_set_pga(struct ad4170_state *st,
return ad4170_write_channel_setup(st, chan->address, false);
}
+static int ad4170_set_calib_offset(struct ad4170_state *st,
+ struct iio_chan_spec const *chan, int val)
+{
+ struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
+ struct ad4170_setup *setup = &chan_info->setup;
+
+ guard(mutex)(&st->lock);
+ setup->offset = val;
+
+ return ad4170_write_channel_setup(st, chan->address, false);
+}
+
static int ad4170_set_calib_gain(struct ad4170_state *st,
struct iio_chan_spec const *chan, int val)
{
@@ -1089,6 +1105,8 @@ static int __ad4170_write_raw(struct iio_dev *indio_dev,
switch (info) {
case IIO_CHAN_INFO_SCALE:
return ad4170_set_pga(st, chan, val, val2);
+ case IIO_CHAN_INFO_CALIBBIAS:
+ return ad4170_set_calib_offset(st, chan, val);
case IIO_CHAN_INFO_CALIBSCALE:
return ad4170_set_calib_gain(st, chan, val);
default:
@@ -1117,6 +1135,7 @@ static int ad4170_write_raw_get_fmt(struct iio_dev *indio_dev,
switch (info) {
case IIO_CHAN_INFO_SCALE:
return IIO_VAL_INT_PLUS_NANO;
+ case IIO_CHAN_INFO_CALIBBIAS:
case IIO_CHAN_INFO_CALIBSCALE:
return IIO_VAL_INT;
default:
--
2.47.2
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v5 05/11] iio: adc: ad4170: Add digital filter and sample frequency config support
2025-06-10 20:30 [PATCH v5 00/11] iio: adc: Add support for AD4170 series of ADCs Marcelo Schmitt
` (3 preceding siblings ...)
2025-06-10 20:32 ` [PATCH v5 04/11] iio: adc: ad4170: Add support for calibration bias Marcelo Schmitt
@ 2025-06-10 20:32 ` Marcelo Schmitt
2025-06-16 20:53 ` David Lechner
2025-06-10 20:32 ` [PATCH v5 06/11] iio: adc: ad4170: Add support for buffered data capture Marcelo Schmitt
` (6 subsequent siblings)
11 siblings, 1 reply; 35+ messages in thread
From: Marcelo Schmitt @ 2025-06-10 20:32 UTC (permalink / raw)
To: linux-iio, devicetree, linux-gpio, linux-kernel
Cc: jic23, lars, Michael.Hennerich, dlechner, nuno.sa, andy, robh,
krzk+dt, conor+dt, linus.walleij, brgl, marcelo.schmitt1
Add support for sinc3, sinc5, and averaged sinc5 digital filters along with
sample frequency configuration.
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
No changes from v4.
drivers/iio/adc/ad4170.c | 262 ++++++++++++++++++++++++++++++++++++++-
1 file changed, 259 insertions(+), 3 deletions(-)
diff --git a/drivers/iio/adc/ad4170.c b/drivers/iio/adc/ad4170.c
index d0482f3b6f01..eecd223cda44 100644
--- a/drivers/iio/adc/ad4170.c
+++ b/drivers/iio/adc/ad4170.c
@@ -18,6 +18,7 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/math64.h>
+#include <linux/minmax.h>
#include <linux/module.h>
#include <linux/property.h>
#include <linux/regmap.h>
@@ -88,6 +89,9 @@
#define AD4170_AFE_BIPOLAR_MSK BIT(4)
#define AD4170_AFE_PGA_GAIN_MSK GENMASK(3, 0)
+/* AD4170_FILTER_REG */
+#define AD4170_FILTER_FILTER_TYPE_MSK GENMASK(3, 0)
+
/* AD4170 register constants */
/* AD4170_CHAN_MAP_REG constants */
@@ -113,6 +117,11 @@
#define AD4170_ADC_CTRL_MODE_SINGLE 0x4
#define AD4170_ADC_CTRL_MODE_IDLE 0x7
+/* AD4170_FILTER_REG constants */
+#define AD4170_FILTER_FILTER_TYPE_SINC5_AVG 0x0
+#define AD4170_FILTER_FILTER_TYPE_SINC5 0x4
+#define AD4170_FILTER_FILTER_TYPE_SINC3 0x6
+
/* Device properties and auxiliary constants */
#define AD4170_NUM_ANALOG_PINS 9
@@ -121,6 +130,7 @@
#define AD4170_MAX_SETUPS 8
#define AD4170_INVALID_SETUP 9
#define AD4170_SPI_MAX_XFER_LEN 6
+#define AD4170_DEFAULT_SAMP_RATE (125 * HZ_PER_KHZ)
#define AD4170_INT_REF_2_5V 2500000
@@ -129,6 +139,12 @@
#define AD4170_NUM_PGA_OPTIONS 10
+/* Digital filter properties */
+#define AD4170_SINC3_MIN_FS 4
+#define AD4170_SINC3_MAX_FS 65532
+#define AD4170_SINC5_MIN_FS 1
+#define AD4170_SINC5_MAX_FS 256
+
#define AD4170_GAIN_REG_DEFAULT 0x555555
static const unsigned int ad4170_reg_size[] = {
@@ -182,6 +198,12 @@ enum ad4170_ref_select {
AD4170_REF_AVDD
};
+enum ad4170_filter_type {
+ AD4170_SINC5_AVG,
+ AD4170_SINC5,
+ AD4170_SINC3,
+};
+
enum ad4170_regulator {
AD4170_AVDD_SUP,
AD4170_AVSS_SUP,
@@ -203,6 +225,18 @@ static const char * const ad4170_int_pin_names[] = {
[AD4170_INT_PIN_DIG_AUX1] = "dig_aux1",
};
+static const unsigned int ad4170_sinc3_filt_fs_tbl[] = {
+ 4, 8, 12, 16, 20, 40, 48, 80, /* 0 - 7 */
+ 100, 256, 500, 1000, 5000, 8332, 10000, 25000, /* 8 - 15 */
+ 50000, 65532, /* 16 - 17 */
+};
+
+#define AD4170_MAX_FS_TBL_SIZE ARRAY_SIZE(ad4170_sinc3_filt_fs_tbl)
+
+static const unsigned int ad4170_sinc5_filt_fs_tbl[] = {
+ 1, 2, 4, 8, 12, 16, 20, 40, 48, 80, 100, 256,
+};
+
struct ad4170_chip_info {
const char *name;
};
@@ -260,6 +294,12 @@ struct ad4170_chan_info {
bool enabled;
};
+static const char * const ad4170_filt_names[] = {
+ [AD4170_SINC5_AVG] = "sinc5+avg",
+ [AD4170_SINC5] = "sinc5",
+ [AD4170_SINC3] = "sinc3",
+};
+
struct ad4170_state {
struct mutex lock; /* Protect read-modify-write and multi write sequences */
int vrefs_uv[AD4170_MAX_SUP];
@@ -269,6 +309,7 @@ struct ad4170_state {
struct ad4170_chan_info chan_infos[AD4170_MAX_CHANNELS];
struct spi_device *spi;
struct regmap *regmap;
+ int sps_tbl[ARRAY_SIZE(ad4170_filt_names)][AD4170_MAX_FS_TBL_SIZE][2];
struct completion completion;
int pins_fn[AD4170_NUM_ANALOG_PINS];
u32 int_pin_sel;
@@ -280,6 +321,38 @@ struct ad4170_state {
u8 rx_buf[4];
};
+static void ad4170_fill_sps_tbl(struct ad4170_state *st)
+{
+ unsigned int tmp0, tmp1, i;
+
+ /*
+ * The ODR can be calculated the same way for sinc5+avg, sinc5, and
+ * sinc3 filter types with the exception that sinc5 filter has a
+ * narrowed range of allowed FILTER_FS values.
+ */
+ for (i = 0; i < ARRAY_SIZE(ad4170_sinc3_filt_fs_tbl); i++) {
+ tmp0 = div_u64_rem(st->mclk_hz, 32 * ad4170_sinc3_filt_fs_tbl[i],
+ &tmp1);
+ tmp1 = mult_frac(tmp1, MICRO, 32 * ad4170_sinc3_filt_fs_tbl[i]);
+ /* Fill sinc5+avg filter SPS table */
+ st->sps_tbl[AD4170_SINC5_AVG][i][0] = tmp0; /* Integer part */
+ st->sps_tbl[AD4170_SINC5_AVG][i][1] = tmp1; /* Fractional part */
+
+ /* Fill sinc3 filter SPS table */
+ st->sps_tbl[AD4170_SINC3][i][0] = tmp0; /* Integer part */
+ st->sps_tbl[AD4170_SINC3][i][1] = tmp1; /* Fractional part */
+ }
+ /* Sinc5 filter ODR doesn't use all FILTER_FS bits */
+ for (i = 0; i < ARRAY_SIZE(ad4170_sinc5_filt_fs_tbl); i++) {
+ tmp0 = div_u64_rem(st->mclk_hz, 32 * ad4170_sinc5_filt_fs_tbl[i],
+ &tmp1);
+ tmp1 = mult_frac(tmp1, MICRO, 32 * ad4170_sinc5_filt_fs_tbl[i]);
+ /* Fill sinc5 filter SPS table */
+ st->sps_tbl[AD4170_SINC5][i][0] = tmp0; /* Integer part */
+ st->sps_tbl[AD4170_SINC5][i][1] = tmp1; /* Fractional part */
+ }
+}
+
static int ad4170_debugfs_reg_access(struct iio_dev *indio_dev,
unsigned int reg, unsigned int writeval,
unsigned int *readval)
@@ -630,6 +703,100 @@ static int ad4170_set_channel_enable(struct ad4170_state *st,
return 0;
}
+static int __ad4170_get_filter_type(unsigned int filter)
+{
+ u16 f_conf = FIELD_GET(AD4170_FILTER_FILTER_TYPE_MSK, filter);
+
+ switch (f_conf) {
+ case AD4170_FILTER_FILTER_TYPE_SINC5_AVG:
+ return AD4170_SINC5_AVG;
+ case AD4170_FILTER_FILTER_TYPE_SINC5:
+ return AD4170_SINC5;
+ case AD4170_FILTER_FILTER_TYPE_SINC3:
+ return AD4170_SINC3;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int ad4170_set_filter_type(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ unsigned int val)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
+ struct ad4170_setup *setup = &chan_info->setup;
+ unsigned int filter_type_conf;
+ int ret;
+
+ switch (val) {
+ case AD4170_SINC5_AVG:
+ filter_type_conf = AD4170_FILTER_FILTER_TYPE_SINC5_AVG;
+ break;
+ case AD4170_SINC5:
+ filter_type_conf = AD4170_FILTER_FILTER_TYPE_SINC5;
+ break;
+ case AD4170_SINC3:
+ filter_type_conf = AD4170_FILTER_FILTER_TYPE_SINC3;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /*
+ * The filters provide the same ODR for a given filter_fs value but
+ * there are different minimum and maximum filter_fs limits for each
+ * filter. The filter_fs value will be adjusted if the current filter_fs
+ * is out of the limits of the just requested filter. Since the
+ * filter_fs value affects the ODR (sampling_frequency), changing the
+ * filter may lead to a change in the sampling frequency.
+ */
+ scoped_guard(mutex, &st->lock) {
+ if (!iio_device_claim_direct(indio_dev))
+ return -EBUSY;
+
+ if (val == AD4170_SINC5_AVG || val == AD4170_SINC3)
+ setup->filter_fs = clamp(val, AD4170_SINC3_MIN_FS,
+ AD4170_SINC3_MAX_FS);
+ else
+ setup->filter_fs = clamp(val, AD4170_SINC5_MIN_FS,
+ AD4170_SINC5_MAX_FS);
+
+ setup->filter &= ~AD4170_FILTER_FILTER_TYPE_MSK;
+ setup->filter |= FIELD_PREP(AD4170_FILTER_FILTER_TYPE_MSK,
+ filter_type_conf);
+
+ ret = ad4170_write_channel_setup(st, chan->address, false);
+ iio_device_release_direct(indio_dev);
+ }
+
+ return ret;
+}
+
+static int ad4170_get_filter_type(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
+ struct ad4170_setup *setup = &chan_info->setup;
+
+ return __ad4170_get_filter_type(setup->filter);
+}
+
+static const struct iio_enum ad4170_filter_type_enum = {
+ .items = ad4170_filt_names,
+ .num_items = ARRAY_SIZE(ad4170_filt_names),
+ .get = ad4170_get_filter_type,
+ .set = ad4170_set_filter_type,
+};
+
+static const struct iio_chan_spec_ext_info ad4170_filter_type_ext_info[] = {
+ IIO_ENUM("filter_type", IIO_SEPARATE, &ad4170_filter_type_enum),
+ IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_TYPE,
+ &ad4170_filter_type_enum),
+ { }
+};
+
static const struct iio_chan_spec ad4170_channel_template = {
.type = IIO_VOLTAGE,
.indexed = 1,
@@ -638,8 +805,11 @@ static const struct iio_chan_spec ad4170_channel_template = {
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_CALIBBIAS) |
BIT(IIO_CHAN_INFO_CALIBSCALE) |
- BIT(IIO_CHAN_INFO_OFFSET),
- .info_mask_separate_available = BIT(IIO_CHAN_INFO_SCALE),
+ BIT(IIO_CHAN_INFO_OFFSET) |
+ BIT(IIO_CHAN_INFO_SAMP_FREQ),
+ .info_mask_separate_available = BIT(IIO_CHAN_INFO_SCALE) |
+ BIT(IIO_CHAN_INFO_SAMP_FREQ),
+ .ext_info = ad4170_filter_type_ext_info,
.scan_type = {
.realbits = 24,
.storagebits = 32,
@@ -931,7 +1101,8 @@ static int ad4170_read_raw(struct iio_dev *indio_dev,
struct ad4170_state *st = iio_priv(indio_dev);
struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
struct ad4170_setup *setup = &chan_info->setup;
- unsigned int pga;
+ enum ad4170_filter_type f_type;
+ unsigned int pga, fs_idx;
int ret;
guard(mutex)(&st->lock);
@@ -952,6 +1123,27 @@ static int ad4170_read_raw(struct iio_dev *indio_dev,
pga = FIELD_GET(AD4170_AFE_PGA_GAIN_MSK, setup->afe);
*val = chan_info->offset_tbl[pga];
return IIO_VAL_INT;
+ case IIO_CHAN_INFO_SAMP_FREQ:
+ f_type = __ad4170_get_filter_type(setup->filter);
+ switch (f_type) {
+ case AD4170_SINC5_AVG:
+ case AD4170_SINC3:
+ fs_idx = find_closest(setup->filter_fs,
+ ad4170_sinc3_filt_fs_tbl,
+ ARRAY_SIZE(ad4170_sinc3_filt_fs_tbl));
+ *val = st->sps_tbl[f_type][fs_idx][0];
+ *val2 = st->sps_tbl[f_type][fs_idx][1];
+ return IIO_VAL_INT_PLUS_MICRO;
+ case AD4170_SINC5:
+ fs_idx = find_closest(setup->filter_fs,
+ ad4170_sinc5_filt_fs_tbl,
+ ARRAY_SIZE(ad4170_sinc5_filt_fs_tbl));
+ *val = st->sps_tbl[f_type][fs_idx][0];
+ *val2 = st->sps_tbl[f_type][fs_idx][1];
+ return IIO_VAL_INT_PLUS_MICRO;
+ default:
+ return -EINVAL;
+ }
case IIO_CHAN_INFO_CALIBBIAS:
*val = setup->offset;
return IIO_VAL_INT;
@@ -1037,6 +1229,7 @@ static int ad4170_read_avail(struct iio_dev *indio_dev,
{
struct ad4170_state *st = iio_priv(indio_dev);
struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
+ enum ad4170_filter_type f_type;
switch (info) {
case IIO_CHAN_INFO_SCALE:
@@ -1044,6 +1237,21 @@ static int ad4170_read_avail(struct iio_dev *indio_dev,
*length = ARRAY_SIZE(chan_info->scale_tbl) * 2;
*type = IIO_VAL_INT_PLUS_NANO;
return IIO_AVAIL_LIST;
+ case IIO_CHAN_INFO_SAMP_FREQ:
+ f_type = ad4170_get_filter_type(indio_dev, chan);
+ *vals = (int *)st->sps_tbl[f_type];
+ *type = IIO_VAL_INT_PLUS_MICRO;
+ switch (f_type) {
+ case AD4170_SINC5_AVG:
+ case AD4170_SINC3:
+ *length = ARRAY_SIZE(ad4170_sinc3_filt_fs_tbl) * 2;
+ return IIO_AVAIL_LIST;
+ case AD4170_SINC5:
+ *length = ARRAY_SIZE(ad4170_sinc5_filt_fs_tbl) * 2;
+ return IIO_AVAIL_LIST;
+ default:
+ return -EINVAL;
+ }
default:
return -EINVAL;
}
@@ -1072,6 +1280,42 @@ static int ad4170_set_pga(struct ad4170_state *st,
return ad4170_write_channel_setup(st, chan->address, false);
}
+static int ad4170_set_channel_freq(struct ad4170_state *st,
+ struct iio_chan_spec const *chan, int val,
+ int val2)
+{
+ struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
+ struct ad4170_setup *setup = &chan_info->setup;
+ enum ad4170_filter_type f_type = __ad4170_get_filter_type(setup->filter);
+ unsigned int filt_fs_tbl_size, i;
+
+ switch (f_type) {
+ case AD4170_SINC5_AVG:
+ case AD4170_SINC3:
+ filt_fs_tbl_size = ARRAY_SIZE(ad4170_sinc3_filt_fs_tbl);
+ break;
+ case AD4170_SINC5:
+ filt_fs_tbl_size = ARRAY_SIZE(ad4170_sinc5_filt_fs_tbl);
+ break;
+ }
+
+ for (i = 0; i < filt_fs_tbl_size; i++) {
+ if (st->sps_tbl[f_type][i][0] == val &&
+ st->sps_tbl[f_type][i][1] == val2)
+ break;
+ }
+ if (i == filt_fs_tbl_size)
+ return -EINVAL;
+
+ guard(mutex)(&st->lock);
+ if (f_type == AD4170_SINC5)
+ setup->filter_fs = ad4170_sinc5_filt_fs_tbl[i];
+ else
+ setup->filter_fs = ad4170_sinc3_filt_fs_tbl[i];
+
+ return ad4170_write_channel_setup(st, chan->address, false);
+}
+
static int ad4170_set_calib_offset(struct ad4170_state *st,
struct iio_chan_spec const *chan, int val)
{
@@ -1105,6 +1349,8 @@ static int __ad4170_write_raw(struct iio_dev *indio_dev,
switch (info) {
case IIO_CHAN_INFO_SCALE:
return ad4170_set_pga(st, chan, val, val2);
+ case IIO_CHAN_INFO_SAMP_FREQ:
+ return ad4170_set_channel_freq(st, chan, val, val2);
case IIO_CHAN_INFO_CALIBBIAS:
return ad4170_set_calib_offset(st, chan, val);
case IIO_CHAN_INFO_CALIBSCALE:
@@ -1135,6 +1381,8 @@ static int ad4170_write_raw_get_fmt(struct iio_dev *indio_dev,
switch (info) {
case IIO_CHAN_INFO_SCALE:
return IIO_VAL_INT_PLUS_NANO;
+ case IIO_CHAN_INFO_SAMP_FREQ:
+ return IIO_VAL_INT_PLUS_MICRO;
case IIO_CHAN_INFO_CALIBBIAS:
case IIO_CHAN_INFO_CALIBSCALE:
return IIO_VAL_INT;
@@ -1364,6 +1612,8 @@ static int ad4170_initial_config(struct iio_dev *indio_dev)
unsigned int i;
int ret;
+ ad4170_fill_sps_tbl(st);
+
ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG,
AD4170_ADC_CTRL_MODE_MSK,
FIELD_PREP(AD4170_ADC_CTRL_MODE_MSK,
@@ -1396,6 +1646,12 @@ static int ad4170_initial_config(struct iio_dev *indio_dev)
return dev_err_probe(dev, ret,
"Failed to write CHAN_MAP_REG\n");
+ ret = ad4170_set_channel_freq(st, chan,
+ AD4170_DEFAULT_SAMP_RATE, 0);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to set channel freq\n");
+
ret = ad4170_fill_scale_tbl(indio_dev, chan);
if (ret)
return dev_err_probe(dev, ret,
--
2.47.2
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v5 06/11] iio: adc: ad4170: Add support for buffered data capture
2025-06-10 20:30 [PATCH v5 00/11] iio: adc: Add support for AD4170 series of ADCs Marcelo Schmitt
` (4 preceding siblings ...)
2025-06-10 20:32 ` [PATCH v5 05/11] iio: adc: ad4170: Add digital filter and sample frequency config support Marcelo Schmitt
@ 2025-06-10 20:32 ` Marcelo Schmitt
2025-06-10 21:17 ` Andy Shevchenko
2025-06-10 20:33 ` [PATCH v5 07/11] iio: adc: ad4170: Add clock provider support Marcelo Schmitt
` (5 subsequent siblings)
11 siblings, 1 reply; 35+ messages in thread
From: Marcelo Schmitt @ 2025-06-10 20:32 UTC (permalink / raw)
To: linux-iio, devicetree, linux-gpio, linux-kernel
Cc: jic23, lars, Michael.Hennerich, dlechner, nuno.sa, andy, robh,
krzk+dt, conor+dt, linus.walleij, brgl, marcelo.schmitt1
Extend the AD4170 driver to allow buffered data capture in continuous read
mode. In continuous read mode, the chip skips the instruction phase and
outputs just ADC sample data, enabling faster sample rates to be reached.
The internal channel sequencer always starts sampling from channel 0 and
channel 0 must be enabled if more than one channel is selected for data
capture. The scan mask validation callback checks if the aforementioned
condition is met.
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
No changes from v4.
drivers/iio/adc/Kconfig | 2 +
drivers/iio/adc/ad4170.c | 215 ++++++++++++++++++++++++++++++++++++++-
2 files changed, 216 insertions(+), 1 deletion(-)
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 03966d07a721..b12dcc04c894 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -89,6 +89,8 @@ config AD4170
tristate "Analog Device AD4170 ADC Driver"
depends on SPI
select REGMAP_SPI
+ select IIO_BUFFER
+ select IIO_TRIGGERED_BUFFER
help
Say yes here to build support for Analog Devices AD4170 SPI analog
to digital converters (ADC).
diff --git a/drivers/iio/adc/ad4170.c b/drivers/iio/adc/ad4170.c
index eecd223cda44..5501fc6e8d3c 100644
--- a/drivers/iio/adc/ad4170.c
+++ b/drivers/iio/adc/ad4170.c
@@ -14,7 +14,11 @@
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
+#include <linux/iio/buffer.h>
#include <linux/iio/iio.h>
+#include <linux/iio/trigger.h>
+#include <linux/iio/trigger_consumer.h>
+#include <linux/iio/triggered_buffer.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/math64.h>
@@ -59,6 +63,7 @@
#define AD4170_FILTER_FS_REG(x) (0xC7 + 14 * (x))
#define AD4170_OFFSET_REG(x) (0xCA + 14 * (x))
#define AD4170_GAIN_REG(x) (0xCD + 14 * (x))
+#define AD4170_ADC_CTRL_CONT_READ_EXIT_REG 0x200 /* virtual reg */
#define AD4170_REG_READ_MASK BIT(14)
@@ -70,6 +75,7 @@
/* AD4170_ADC_CTRL_REG */
#define AD4170_ADC_CTRL_MULTI_DATA_REG_SEL_MSK BIT(7)
+#define AD4170_ADC_CTRL_CONT_READ_MSK GENMASK(5, 4)
#define AD4170_ADC_CTRL_MODE_MSK GENMASK(3, 0)
/* AD4170_CHAN_EN_REG */
@@ -114,9 +120,13 @@
#define AD4170_PIN_MUXING_DIG_AUX1_RDY 0x1
/* AD4170_ADC_CTRL_REG constants */
+#define AD4170_ADC_CTRL_MODE_CONT 0x0
#define AD4170_ADC_CTRL_MODE_SINGLE 0x4
#define AD4170_ADC_CTRL_MODE_IDLE 0x7
+#define AD4170_ADC_CTRL_CONT_READ_DISABLE 0x0
+#define AD4170_ADC_CTRL_CONT_READ_ENABLE 0x1
+
/* AD4170_FILTER_REG constants */
#define AD4170_FILTER_FILTER_TYPE_SINC5_AVG 0x0
#define AD4170_FILTER_FILTER_TYPE_SINC5 0x4
@@ -147,6 +157,8 @@
#define AD4170_GAIN_REG_DEFAULT 0x555555
+#define AD4170_ADC_CTRL_CONT_READ_EXIT 0xA5
+
static const unsigned int ad4170_reg_size[] = {
[AD4170_CONFIG_A_REG] = 1,
[AD4170_DATA_24B_REG] = 3,
@@ -183,6 +195,7 @@ static const unsigned int ad4170_reg_size[] = {
[AD4170_OFFSET_REG(5) ... AD4170_GAIN_REG(5)] = 3,
[AD4170_OFFSET_REG(6) ... AD4170_GAIN_REG(6)] = 3,
[AD4170_OFFSET_REG(7) ... AD4170_GAIN_REG(7)] = 3,
+ [AD4170_ADC_CTRL_CONT_READ_EXIT_REG] = 0,
};
enum ad4170_ref_buf {
@@ -310,6 +323,10 @@ struct ad4170_state {
struct spi_device *spi;
struct regmap *regmap;
int sps_tbl[ARRAY_SIZE(ad4170_filt_names)][AD4170_MAX_FS_TBL_SIZE][2];
+ __be32 bounce_buffer[AD4170_MAX_CHANNELS];
+ struct spi_message msg;
+ struct spi_transfer xfer;
+ struct iio_trigger *trig;
struct completion completion;
int pins_fn[AD4170_NUM_ANALOG_PINS];
u32 int_pin_sel;
@@ -397,6 +414,10 @@ static int ad4170_reg_write(void *context, unsigned int reg, unsigned int val)
case 1:
st->tx_buf[2] = val;
break;
+ case 0:
+ /* Write continuous read exit code */
+ st->tx_buf[0] = AD4170_ADC_CTRL_CONT_READ_EXIT;
+ return spi_write(st->spi, st->tx_buf, 1);
default:
return -EINVAL;
}
@@ -813,6 +834,7 @@ static const struct iio_chan_spec ad4170_channel_template = {
.scan_type = {
.realbits = 24,
.storagebits = 32,
+ .shift = 8,
.endianness = IIO_BE,
},
};
@@ -1391,11 +1413,27 @@ static int ad4170_write_raw_get_fmt(struct iio_dev *indio_dev,
}
}
+static int ad4170_update_scan_mode(struct iio_dev *indio_dev,
+ const unsigned long *active_scan_mask)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ unsigned int chan_index;
+ int ret;
+
+ iio_for_each_active_channel(indio_dev, chan_index) {
+ ret = ad4170_set_channel_enable(st, chan_index, true);
+ if (ret)
+ return ret;
+ }
+ return 0;
+}
+
static const struct iio_info ad4170_info = {
.read_raw = ad4170_read_raw,
.read_avail = ad4170_read_avail,
.write_raw = ad4170_write_raw,
.write_raw_get_fmt = ad4170_write_raw_get_fmt,
+ .update_scan_mode = ad4170_update_scan_mode,
.debugfs_reg_access = ad4170_debugfs_reg_access,
};
@@ -1674,16 +1712,177 @@ static int ad4170_initial_config(struct iio_dev *indio_dev)
AD4170_ADC_CTRL_MULTI_DATA_REG_SEL_MSK);
}
+static int ad4170_prepare_spi_message(struct ad4170_state *st)
+{
+ /*
+ * Continuous data register read is enabled on buffer postenable so
+ * no instruction phase is needed meaning we don't need to send the
+ * register address to read data. Transfer only needs the read buffer.
+ */
+ st->xfer.rx_buf = &st->rx_buf;
+ st->xfer.len = BITS_TO_BYTES(ad4170_channel_template.scan_type.realbits);
+
+ spi_message_init_with_transfers(&st->msg, &st->xfer, 1);
+
+ return devm_spi_optimize_message(&st->spi->dev, st->spi, &st->msg);
+}
+
+static int ad4170_buffer_postenable(struct iio_dev *indio_dev)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ int ret;
+
+ ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG,
+ AD4170_ADC_CTRL_MODE_MSK,
+ FIELD_PREP(AD4170_ADC_CTRL_MODE_MSK,
+ AD4170_ADC_CTRL_MODE_CONT));
+ if (ret)
+ return ret;
+
+ /*
+ * This enables continuous read of the ADC data register. The ADC must
+ * be in continuous conversion mode.
+ */
+ return regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG,
+ AD4170_ADC_CTRL_CONT_READ_MSK,
+ FIELD_PREP(AD4170_ADC_CTRL_CONT_READ_MSK,
+ AD4170_ADC_CTRL_CONT_READ_ENABLE));
+}
+
+static int ad4170_buffer_predisable(struct iio_dev *indio_dev)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ unsigned int i;
+ int ret;
+
+ /*
+ * Use a high register address (virtual register) to request a write of
+ * 0xA5 to the ADC during the first 8 SCLKs of the ADC data read cycle,
+ * thus exiting continuous read.
+ */
+ ret = regmap_write(st->regmap, AD4170_ADC_CTRL_CONT_READ_EXIT_REG, 0);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG,
+ AD4170_ADC_CTRL_CONT_READ_MSK,
+ FIELD_PREP(AD4170_ADC_CTRL_CONT_READ_MSK,
+ AD4170_ADC_CTRL_CONT_READ_DISABLE));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG,
+ AD4170_ADC_CTRL_MODE_MSK,
+ FIELD_PREP(AD4170_ADC_CTRL_MODE_MSK,
+ AD4170_ADC_CTRL_MODE_IDLE));
+ if (ret)
+ return ret;
+
+ /*
+ * The ADC sequences through all the enabled channels (see datasheet
+ * page 95). That can lead to incorrect channel being read if a
+ * single-shot read (or buffered read with different active_scan_mask)
+ * is done after buffer disable. Disable all channels so only requested
+ * channels will be read.
+ */
+ for (i = 0; i < indio_dev->num_channels; i++) {
+ ret = ad4170_set_channel_enable(st, i, false);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static bool ad4170_validate_scan_mask(struct iio_dev *indio_dev,
+ const unsigned long *scan_mask)
+{
+ unsigned int masklength = iio_get_masklength(indio_dev);
+
+ /*
+ * The channel sequencer cycles through the enabled channels in
+ * sequential order, from channel 0 to channel 15, bypassing disabled
+ * channels. When more than one channel is enabled, channel 0 must
+ * always be enabled. See datasheet channel_en register description at
+ * page 95.
+ */
+ if (bitmap_weight(scan_mask, masklength) > 1)
+ return test_bit(0, scan_mask);
+
+ return bitmap_weight(scan_mask, masklength) == 1;
+}
+
+static const struct iio_buffer_setup_ops ad4170_buffer_ops = {
+ .postenable = ad4170_buffer_postenable,
+ .predisable = ad4170_buffer_predisable,
+ .validate_scan_mask = ad4170_validate_scan_mask,
+};
+
+static irqreturn_t ad4170_trigger_handler(int irq, void *p)
+{
+ struct iio_poll_func *pf = p;
+ struct iio_dev *indio_dev = pf->indio_dev;
+ struct ad4170_state *st = iio_priv(indio_dev);
+ unsigned int chan_index;
+ unsigned int i = 0;
+ int ret;
+
+ iio_for_each_active_channel(indio_dev, chan_index) {
+ ret = spi_sync(st->spi, &st->msg);
+ if (ret)
+ goto err_out;
+
+ memcpy(&st->bounce_buffer[i++], st->rx_buf, ARRAY_SIZE(st->rx_buf));
+ }
+
+ iio_push_to_buffers(indio_dev, st->bounce_buffer);
+err_out:
+ iio_trigger_notify_done(indio_dev->trig);
+ return IRQ_HANDLED;
+}
+
+static const struct iio_trigger_ops ad4170_trigger_ops = {
+ .validate_device = iio_trigger_validate_own_device,
+};
+
static irqreturn_t ad4170_irq_handler(int irq, void *dev_id)
{
struct iio_dev *indio_dev = dev_id;
struct ad4170_state *st = iio_priv(indio_dev);
- complete(&st->completion);
+ if (iio_buffer_enabled(indio_dev))
+ iio_trigger_poll(st->trig);
+ else
+ complete(&st->completion);
return IRQ_HANDLED;
};
+static int ad4170_trigger_setup(struct iio_dev *indio_dev)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ struct device *dev = &st->spi->dev;
+ int ret;
+
+ st->trig = devm_iio_trigger_alloc(dev, "%s-trig%d",
+ indio_dev->name,
+ iio_device_id(indio_dev));
+ if (!st->trig)
+ return -ENOMEM;
+
+ st->trig->ops = &ad4170_trigger_ops;
+ st->trig->dev.parent = dev;
+
+ iio_trigger_set_drvdata(st->trig, indio_dev);
+ ret = devm_iio_trigger_register(dev, st->trig);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to register trigger\n");
+
+ indio_dev->trig = iio_trigger_get(st->trig);
+
+ return 0;
+}
+
static int ad4170_regulator_setup(struct ad4170_state *st)
{
struct device *dev = &st->spi->dev;
@@ -1793,8 +1992,22 @@ static int ad4170_probe(struct spi_device *spi)
IRQF_ONESHOT, indio_dev->name, indio_dev);
if (ret)
return ret;
+
+ ret = ad4170_trigger_setup(indio_dev);
+ if (ret)
+ return ret;
}
+ ret = ad4170_prepare_spi_message(st);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to prepare SPI message\n");
+
+ ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
+ &ad4170_trigger_handler,
+ &ad4170_buffer_ops);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to setup read buffer\n");
+
return devm_iio_device_register(dev, indio_dev);
}
--
2.47.2
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v5 07/11] iio: adc: ad4170: Add clock provider support
2025-06-10 20:30 [PATCH v5 00/11] iio: adc: Add support for AD4170 series of ADCs Marcelo Schmitt
` (5 preceding siblings ...)
2025-06-10 20:32 ` [PATCH v5 06/11] iio: adc: ad4170: Add support for buffered data capture Marcelo Schmitt
@ 2025-06-10 20:33 ` Marcelo Schmitt
2025-06-16 21:11 ` David Lechner
2025-06-10 20:33 ` [PATCH v5 08/11] iio: adc: ad4170: Add GPIO controller support Marcelo Schmitt
` (4 subsequent siblings)
11 siblings, 1 reply; 35+ messages in thread
From: Marcelo Schmitt @ 2025-06-10 20:33 UTC (permalink / raw)
To: linux-iio, devicetree, linux-gpio, linux-kernel
Cc: jic23, lars, Michael.Hennerich, dlechner, nuno.sa, andy, robh,
krzk+dt, conor+dt, linus.walleij, brgl, marcelo.schmitt1
The AD4170 chip can use an externally supplied clock at the XTAL2 pin, or
an external crystal connected to the XTAL1 and XTAL2 pins. Alternatively,
the AD4170 can provide its 16 MHz internal clock at the XTAL2 pin. In
addition, the chip has a programmable clock divider that allows dividing
the external or internal clock frequency, however, control for that is not
provided in this patch. Extend the AD4170 driver so it effectively uses the
provided external clock, if any, or supplies its own clock as a clock
provider.
Reviewed-by: Nuno Sá <nuno.sa@analog.com>
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
No changes from v4.
drivers/iio/adc/Kconfig | 1 +
drivers/iio/adc/ad4170.c | 147 ++++++++++++++++++++++++++++++++++++++-
2 files changed, 147 insertions(+), 1 deletion(-)
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index b12dcc04c894..32e5177ceebe 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -91,6 +91,7 @@ config AD4170
select REGMAP_SPI
select IIO_BUFFER
select IIO_TRIGGERED_BUFFER
+ depends on COMMON_CLK
help
Say yes here to build support for Analog Devices AD4170 SPI analog
to digital converters (ADC).
diff --git a/drivers/iio/adc/ad4170.c b/drivers/iio/adc/ad4170.c
index 5501fc6e8d3c..310eb32d0d1c 100644
--- a/drivers/iio/adc/ad4170.c
+++ b/drivers/iio/adc/ad4170.c
@@ -11,6 +11,8 @@
#include <linux/bitops.h>
#include <linux/bits.h>
#include <linux/cleanup.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
@@ -53,6 +55,7 @@
#define AD4170_CONFIG_A_REG 0x00
#define AD4170_DATA_24B_REG 0x1E
#define AD4170_PIN_MUXING_REG 0x69
+#define AD4170_CLOCK_CTRL_REG 0x6B
#define AD4170_ADC_CTRL_REG 0x71
#define AD4170_CHAN_EN_REG 0x79
#define AD4170_CHAN_SETUP_REG(x) (0x81 + 4 * (x))
@@ -73,6 +76,9 @@
/* AD4170_PIN_MUXING_REG */
#define AD4170_PIN_MUXING_DIG_AUX1_CTRL_MSK GENMASK(5, 4)
+/* AD4170_CLOCK_CTRL_REG */
+#define AD4170_CLOCK_CTRL_CLOCKSEL_MSK GENMASK(1, 0)
+
/* AD4170_ADC_CTRL_REG */
#define AD4170_ADC_CTRL_MULTI_DATA_REG_SEL_MSK BIT(7)
#define AD4170_ADC_CTRL_CONT_READ_MSK GENMASK(5, 4)
@@ -100,6 +106,12 @@
/* AD4170 register constants */
+/* AD4170_CLOCK_CTRL_REG constants */
+#define AD4170_CLOCK_CTRL_CLOCKSEL_INT 0x0
+#define AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT 0x1
+#define AD4170_CLOCK_CTRL_CLOCKSEL_EXT 0x2
+#define AD4170_CLOCK_CTRL_CLOCKSEL_EXT_XTAL 0x3
+
/* AD4170_CHAN_MAP_REG constants */
#define AD4170_CHAN_MAP_AIN(x) (x)
#define AD4170_CHAN_MAP_TEMP_SENSOR 17
@@ -146,6 +158,8 @@
/* Internal and external clock properties */
#define AD4170_INT_CLOCK_16MHZ (16 * HZ_PER_MHZ)
+#define AD4170_EXT_CLOCK_MHZ_MIN (1 * HZ_PER_MHZ)
+#define AD4170_EXT_CLOCK_MHZ_MAX (17 * HZ_PER_MHZ)
#define AD4170_NUM_PGA_OPTIONS 10
@@ -163,6 +177,7 @@ static const unsigned int ad4170_reg_size[] = {
[AD4170_CONFIG_A_REG] = 1,
[AD4170_DATA_24B_REG] = 3,
[AD4170_PIN_MUXING_REG] = 2,
+ [AD4170_CLOCK_CTRL_REG] = 2,
[AD4170_ADC_CTRL_REG] = 2,
[AD4170_CHAN_EN_REG] = 2,
/*
@@ -228,6 +243,10 @@ enum ad4170_regulator {
AD4170_MAX_SUP
};
+static const char *const ad4170_clk_sel[] = {
+ "ext-clk", "xtal",
+};
+
enum ad4170_int_pin_sel {
AD4170_INT_PIN_SDO,
AD4170_INT_PIN_DIG_AUX1,
@@ -330,6 +349,8 @@ struct ad4170_state {
struct completion completion;
int pins_fn[AD4170_NUM_ANALOG_PINS];
u32 int_pin_sel;
+ struct clk_hw int_clk_hw;
+ unsigned int clock_ctrl;
/*
* DMA (thus cache coherency maintenance) requires the transfer buffers
* to live in their own cache lines.
@@ -1614,13 +1635,137 @@ static int ad4170_parse_channels(struct iio_dev *indio_dev)
return 0;
}
+static struct ad4170_state *clk_hw_to_ad4170(struct clk_hw *hw)
+{
+ return container_of(hw, struct ad4170_state, int_clk_hw);
+}
+
+static unsigned long ad4170_sel_clk(struct ad4170_state *st,
+ unsigned int clk_sel)
+{
+ st->clock_ctrl &= ~AD4170_CLOCK_CTRL_CLOCKSEL_MSK;
+ st->clock_ctrl |= FIELD_PREP(AD4170_CLOCK_CTRL_CLOCKSEL_MSK, clk_sel);
+ return regmap_write(st->regmap, AD4170_CLOCK_CTRL_REG, st->clock_ctrl);
+}
+
+static unsigned long ad4170_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return AD4170_INT_CLOCK_16MHZ;
+}
+
+static int ad4170_clk_output_is_enabled(struct clk_hw *hw)
+{
+ struct ad4170_state *st = clk_hw_to_ad4170(hw);
+ u32 clk_sel;
+
+ clk_sel = FIELD_GET(AD4170_CLOCK_CTRL_CLOCKSEL_MSK, st->clock_ctrl);
+ return clk_sel == AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT;
+}
+
+static int ad4170_clk_output_prepare(struct clk_hw *hw)
+{
+ struct ad4170_state *st = clk_hw_to_ad4170(hw);
+
+ return ad4170_sel_clk(st, AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT);
+}
+
+static void ad4170_clk_output_unprepare(struct clk_hw *hw)
+{
+ struct ad4170_state *st = clk_hw_to_ad4170(hw);
+
+ ad4170_sel_clk(st, AD4170_CLOCK_CTRL_CLOCKSEL_INT);
+}
+
+static const struct clk_ops ad4170_int_clk_ops = {
+ .recalc_rate = ad4170_clk_recalc_rate,
+ .is_enabled = ad4170_clk_output_is_enabled,
+ .prepare = ad4170_clk_output_prepare,
+ .unprepare = ad4170_clk_output_unprepare,
+};
+
+static int ad4170_register_clk_provider(struct iio_dev *indio_dev)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ struct device *dev = indio_dev->dev.parent;
+ struct clk_init_data init = {};
+ int ret;
+
+ if (device_property_read_string(dev, "clock-output-names", &init.name)) {
+ init.name = devm_kasprintf(dev, GFP_KERNEL, "%pfw",
+ dev_fwnode(dev));
+ if (!init.name)
+ return -ENOMEM;
+ }
+
+ init.ops = &ad4170_int_clk_ops;
+
+ st->int_clk_hw.init = &init;
+ ret = devm_clk_hw_register(dev, &st->int_clk_hw);
+ if (ret)
+ return ret;
+
+ return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
+ &st->int_clk_hw);
+}
+
+static int ad4170_clock_select(struct iio_dev *indio_dev)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+ struct device *dev = &st->spi->dev;
+ struct clk *ext_clk;
+ int ret;
+
+ ext_clk = devm_clk_get_optional_enabled(dev, NULL);
+ if (IS_ERR(ext_clk))
+ return dev_err_probe(dev, PTR_ERR(ext_clk),
+ "Failed to get external clock\n");
+
+ if (!ext_clk) {
+ /* Use internal clock reference */
+ st->mclk_hz = AD4170_INT_CLOCK_16MHZ;
+ st->clock_ctrl |= FIELD_PREP(AD4170_CLOCK_CTRL_CLOCKSEL_MSK,
+ AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT);
+
+ if (!device_property_read_bool(&st->spi->dev, "#clock-cells"))
+ return 0;
+
+ return ad4170_register_clk_provider(indio_dev);
+ }
+
+ /* Read optional clock-names prop to specify the external clock type */
+ ret = device_property_match_property_string(dev, "clock-names",
+ ad4170_clk_sel,
+ ARRAY_SIZE(ad4170_clk_sel));
+
+ ret = ret < 0 ? 0 : ret; /* Default to external clock if no clock-names */
+ st->clock_ctrl |= FIELD_PREP(AD4170_CLOCK_CTRL_CLOCKSEL_MSK,
+ AD4170_CLOCK_CTRL_CLOCKSEL_EXT + ret);
+
+ st->mclk_hz = clk_get_rate(ext_clk);
+ if (st->mclk_hz < AD4170_EXT_CLOCK_MHZ_MIN ||
+ st->mclk_hz > AD4170_EXT_CLOCK_MHZ_MAX) {
+ return dev_err_probe(dev, -EINVAL,
+ "Invalid external clock frequency %u\n",
+ st->mclk_hz);
+ }
+
+ return 0;
+}
+
static int ad4170_parse_firmware(struct iio_dev *indio_dev)
{
struct ad4170_state *st = iio_priv(indio_dev);
struct device *dev = &st->spi->dev;
int reg_data, ret;
- st->mclk_hz = AD4170_INT_CLOCK_16MHZ;
+ ret = ad4170_clock_select(indio_dev);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to setup device clock\n");
+
+ ret = regmap_write(st->regmap, AD4170_CLOCK_CTRL_REG, st->clock_ctrl);
+ if (ret)
+ return ret;
/* On power on, device defaults to using SDO pin for data ready signal */
st->int_pin_sel = AD4170_INT_PIN_SDO;
--
2.47.2
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v5 08/11] iio: adc: ad4170: Add GPIO controller support
2025-06-10 20:30 [PATCH v5 00/11] iio: adc: Add support for AD4170 series of ADCs Marcelo Schmitt
` (6 preceding siblings ...)
2025-06-10 20:33 ` [PATCH v5 07/11] iio: adc: ad4170: Add clock provider support Marcelo Schmitt
@ 2025-06-10 20:33 ` Marcelo Schmitt
2025-06-18 10:15 ` Linus Walleij
2025-06-10 20:33 ` [PATCH v5 09/11] iio: adc: ad4170: Add support for internal temperature sensor Marcelo Schmitt
` (3 subsequent siblings)
11 siblings, 1 reply; 35+ messages in thread
From: Marcelo Schmitt @ 2025-06-10 20:33 UTC (permalink / raw)
To: linux-iio, devicetree, linux-gpio, linux-kernel
Cc: jic23, lars, Michael.Hennerich, dlechner, nuno.sa, andy, robh,
krzk+dt, conor+dt, linus.walleij, brgl, marcelo.schmitt1,
Bartosz Golaszewski
The AD4170 has four multifunctional pins that can be used as GPIOs. The
GPIO functionality can be accessed when the AD4170 chip is not busy
performing continuous data capture or handling any other register
read/write request. Also, the AD4170 does not provide any interrupt based
on GPIO pin states so AD4170 GPIOs can't be used as interrupt sources.
Implement gpio_chip callbacks to make AD4170 GPIO pins controllable through
the gpiochip interface.
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
No changes from v4.
drivers/iio/adc/Kconfig | 1 +
drivers/iio/adc/ad4170.c | 224 ++++++++++++++++++++++++++++++++++++++-
2 files changed, 224 insertions(+), 1 deletion(-)
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 32e5177ceebe..0c16b2d5947d 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -92,6 +92,7 @@ config AD4170
select IIO_BUFFER
select IIO_TRIGGERED_BUFFER
depends on COMMON_CLK
+ depends on GPIOLIB
help
Say yes here to build support for Analog Devices AD4170 SPI analog
to digital converters (ADC).
diff --git a/drivers/iio/adc/ad4170.c b/drivers/iio/adc/ad4170.c
index 310eb32d0d1c..b3189c5f8078 100644
--- a/drivers/iio/adc/ad4170.c
+++ b/drivers/iio/adc/ad4170.c
@@ -16,6 +16,7 @@
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
+#include <linux/gpio/driver.h>
#include <linux/iio/buffer.h>
#include <linux/iio/iio.h>
#include <linux/iio/trigger.h>
@@ -66,6 +67,9 @@
#define AD4170_FILTER_FS_REG(x) (0xC7 + 14 * (x))
#define AD4170_OFFSET_REG(x) (0xCA + 14 * (x))
#define AD4170_GAIN_REG(x) (0xCD + 14 * (x))
+#define AD4170_GPIO_MODE_REG 0x191
+#define AD4170_GPIO_OUTPUT_REG 0x193
+#define AD4170_GPIO_INPUT_REG 0x195
#define AD4170_ADC_CTRL_CONT_READ_EXIT_REG 0x200 /* virtual reg */
#define AD4170_REG_READ_MASK BIT(14)
@@ -104,6 +108,12 @@
/* AD4170_FILTER_REG */
#define AD4170_FILTER_FILTER_TYPE_MSK GENMASK(3, 0)
+/* AD4170_GPIO_MODE_REG */
+#define AD4170_GPIO_MODE_GPIO0_MSK GENMASK(1, 0)
+#define AD4170_GPIO_MODE_GPIO1_MSK GENMASK(3, 2)
+#define AD4170_GPIO_MODE_GPIO2_MSK GENMASK(5, 4)
+#define AD4170_GPIO_MODE_GPIO3_MSK GENMASK(7, 6)
+
/* AD4170 register constants */
/* AD4170_CLOCK_CTRL_REG constants */
@@ -144,9 +154,14 @@
#define AD4170_FILTER_FILTER_TYPE_SINC5 0x4
#define AD4170_FILTER_FILTER_TYPE_SINC3 0x6
+/* AD4170_GPIO_MODE_REG constants */
+#define AD4170_GPIO_MODE_GPIO_INPUT 1
+#define AD4170_GPIO_MODE_GPIO_OUTPUT 2
+
/* Device properties and auxiliary constants */
#define AD4170_NUM_ANALOG_PINS 9
+#define AD4170_NUM_GPIO_PINS 4
#define AD4170_MAX_CHANNELS 16
#define AD4170_MAX_ANALOG_PINS 8
#define AD4170_MAX_SETUPS 8
@@ -173,6 +188,9 @@
#define AD4170_ADC_CTRL_CONT_READ_EXIT 0xA5
+/* GPIO pin functions */
+#define AD4170_GPIO_UNASSIGNED 0x00
+
static const unsigned int ad4170_reg_size[] = {
[AD4170_CONFIG_A_REG] = 1,
[AD4170_DATA_24B_REG] = 3,
@@ -210,6 +228,9 @@ static const unsigned int ad4170_reg_size[] = {
[AD4170_OFFSET_REG(5) ... AD4170_GAIN_REG(5)] = 3,
[AD4170_OFFSET_REG(6) ... AD4170_GAIN_REG(6)] = 3,
[AD4170_OFFSET_REG(7) ... AD4170_GAIN_REG(7)] = 3,
+ [AD4170_GPIO_MODE_REG] = 2,
+ [AD4170_GPIO_OUTPUT_REG] = 2,
+ [AD4170_GPIO_INPUT_REG] = 2,
[AD4170_ADC_CTRL_CONT_READ_EXIT_REG] = 0,
};
@@ -350,7 +371,9 @@ struct ad4170_state {
int pins_fn[AD4170_NUM_ANALOG_PINS];
u32 int_pin_sel;
struct clk_hw int_clk_hw;
+ struct gpio_chip gpiochip;
unsigned int clock_ctrl;
+ int gpio_fn[AD4170_NUM_GPIO_PINS];
/*
* DMA (thus cache coherency maintenance) requires the transfer buffers
* to live in their own cache lines.
@@ -1473,6 +1496,194 @@ static int ad4170_soft_reset(struct ad4170_state *st)
return 0;
}
+static int ad4170_gpio_get(struct gpio_chip *gc, unsigned int offset)
+{
+ struct iio_dev *indio_dev = gpiochip_get_data(gc);
+ struct ad4170_state *st = iio_priv(indio_dev);
+ unsigned int val;
+ int ret;
+
+ if (!iio_device_claim_direct(indio_dev))
+ return -EBUSY;
+
+ ret = regmap_read(st->regmap, AD4170_GPIO_MODE_REG, &val);
+ if (ret)
+ goto err_release;
+
+ /*
+ * If the GPIO is configured as an input, read the current value from
+ * AD4170_GPIO_INPUT_REG. Otherwise, read the input value from
+ * AD4170_GPIO_OUTPUT_REG.
+ */
+ if (val & BIT(offset * 2))
+ ret = regmap_read(st->regmap, AD4170_GPIO_INPUT_REG, &val);
+ else
+ ret = regmap_read(st->regmap, AD4170_GPIO_OUTPUT_REG, &val);
+ if (ret)
+ goto err_release;
+
+ ret = !!(val & BIT(offset));
+err_release:
+ iio_device_release_direct(indio_dev);
+
+ return ret;
+}
+
+static int ad4170_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
+{
+ struct iio_dev *indio_dev = gpiochip_get_data(gc);
+ struct ad4170_state *st = iio_priv(indio_dev);
+ int ret;
+
+ if (!iio_device_claim_direct(indio_dev))
+ return -EBUSY;
+
+ ret = regmap_assign_bits(st->regmap, AD4170_GPIO_OUTPUT_REG,
+ BIT(offset), !!value);
+
+ iio_device_release_direct(indio_dev);
+ return ret;
+}
+
+static int ad4170_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
+{
+ struct iio_dev *indio_dev = gpiochip_get_data(gc);
+ struct ad4170_state *st = iio_priv(indio_dev);
+ unsigned int val;
+ int ret;
+
+ if (!iio_device_claim_direct(indio_dev))
+ return -EBUSY;
+
+ ret = regmap_read(st->regmap, AD4170_GPIO_MODE_REG, &val);
+ if (ret)
+ goto err_release;
+
+ if (val & BIT(offset * 2 + 1))
+ ret = GPIO_LINE_DIRECTION_OUT;
+ else
+ ret = GPIO_LINE_DIRECTION_IN;
+
+err_release:
+ iio_device_release_direct(indio_dev);
+
+ return ret;
+}
+
+static int ad4170_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
+{
+ struct iio_dev *indio_dev = gpiochip_get_data(gc);
+ struct ad4170_state *st = iio_priv(indio_dev);
+ unsigned long gpio_mask;
+ int ret;
+
+ if (!iio_device_claim_direct(indio_dev))
+ return -EBUSY;
+
+ switch (offset) {
+ case 0:
+ gpio_mask = AD4170_GPIO_MODE_GPIO0_MSK;
+ break;
+ case 1:
+ gpio_mask = AD4170_GPIO_MODE_GPIO1_MSK;
+ break;
+ case 2:
+ gpio_mask = AD4170_GPIO_MODE_GPIO2_MSK;
+ break;
+ case 3:
+ gpio_mask = AD4170_GPIO_MODE_GPIO3_MSK;
+ break;
+ default:
+ ret = -EINVAL;
+ goto err_release;
+ }
+ ret = regmap_update_bits(st->regmap, AD4170_GPIO_MODE_REG, gpio_mask,
+ AD4170_GPIO_MODE_GPIO_INPUT << (2 * offset));
+
+err_release:
+ iio_device_release_direct(indio_dev);
+
+ return ret;
+}
+
+static int ad4170_gpio_direction_output(struct gpio_chip *gc,
+ unsigned int offset, int value)
+{
+ struct iio_dev *indio_dev = gpiochip_get_data(gc);
+ struct ad4170_state *st = iio_priv(indio_dev);
+ unsigned long gpio_mask;
+ int ret;
+
+ ret = ad4170_gpio_set(gc, offset, value);
+ if (ret)
+ return ret;
+
+ if (!iio_device_claim_direct(indio_dev))
+ return -EBUSY;
+
+ switch (offset) {
+ case 0:
+ gpio_mask = AD4170_GPIO_MODE_GPIO0_MSK;
+ break;
+ case 1:
+ gpio_mask = AD4170_GPIO_MODE_GPIO1_MSK;
+ break;
+ case 2:
+ gpio_mask = AD4170_GPIO_MODE_GPIO2_MSK;
+ break;
+ case 3:
+ gpio_mask = AD4170_GPIO_MODE_GPIO3_MSK;
+ break;
+ default:
+ ret = -EINVAL;
+ goto err_release;
+ }
+ ret = regmap_update_bits(st->regmap, AD4170_GPIO_MODE_REG, gpio_mask,
+ AD4170_GPIO_MODE_GPIO_OUTPUT << (2 * offset));
+
+err_release:
+ iio_device_release_direct(indio_dev);
+
+ return ret;
+}
+
+static int ad4170_gpio_init_valid_mask(struct gpio_chip *gc,
+ unsigned long *valid_mask,
+ unsigned int ngpios)
+{
+ struct ad4170_state *st = gpiochip_get_data(gc);
+ unsigned int i;
+
+ /* Only expose GPIOs that were not assigned any other function. */
+ for (i = 0; i < ngpios; i++) {
+ bool valid = st->gpio_fn[i] == AD4170_GPIO_UNASSIGNED;
+
+ __assign_bit(i, valid_mask, valid);
+ }
+
+ return 0;
+}
+
+static int ad4170_gpio_init(struct iio_dev *indio_dev)
+{
+ struct ad4170_state *st = iio_priv(indio_dev);
+
+ st->gpiochip.label = "ad4170_gpios";
+ st->gpiochip.base = -1;
+ st->gpiochip.ngpio = AD4170_NUM_GPIO_PINS;
+ st->gpiochip.parent = &st->spi->dev;
+ st->gpiochip.can_sleep = true;
+ st->gpiochip.init_valid_mask = ad4170_gpio_init_valid_mask;
+ st->gpiochip.get_direction = ad4170_gpio_get_direction;
+ st->gpiochip.direction_input = ad4170_gpio_direction_input;
+ st->gpiochip.direction_output = ad4170_gpio_direction_output;
+ st->gpiochip.get = ad4170_gpio_get;
+ st->gpiochip.set_rv = ad4170_gpio_set;
+ st->gpiochip.owner = THIS_MODULE;
+
+ return devm_gpiochip_add_data(&st->spi->dev, &st->gpiochip, indio_dev);
+}
+
static int ad4170_parse_reference(struct ad4170_state *st,
struct fwnode_handle *child,
struct ad4170_setup *setup)
@@ -1785,7 +1996,18 @@ static int ad4170_parse_firmware(struct iio_dev *indio_dev)
if (ret)
return ret;
- return ad4170_parse_channels(indio_dev);
+ ret = ad4170_parse_channels(indio_dev);
+ if (ret)
+ return ret;
+
+ /* Only create a GPIO chip if flagged for it */
+ if (device_property_read_bool(&st->spi->dev, "gpio-controller")) {
+ ret = ad4170_gpio_init(indio_dev);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
}
static int ad4170_initial_config(struct iio_dev *indio_dev)
--
2.47.2
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v5 09/11] iio: adc: ad4170: Add support for internal temperature sensor
2025-06-10 20:30 [PATCH v5 00/11] iio: adc: Add support for AD4170 series of ADCs Marcelo Schmitt
` (7 preceding siblings ...)
2025-06-10 20:33 ` [PATCH v5 08/11] iio: adc: ad4170: Add GPIO controller support Marcelo Schmitt
@ 2025-06-10 20:33 ` Marcelo Schmitt
2025-06-10 20:33 ` [PATCH v5 10/11] iio: adc: ad4170: Add support for weigh scale and RTD sensors Marcelo Schmitt
` (2 subsequent siblings)
11 siblings, 0 replies; 35+ messages in thread
From: Marcelo Schmitt @ 2025-06-10 20:33 UTC (permalink / raw)
To: linux-iio, devicetree, linux-gpio, linux-kernel
Cc: jic23, lars, Michael.Hennerich, dlechner, nuno.sa, andy, robh,
krzk+dt, conor+dt, linus.walleij, brgl, marcelo.schmitt1
The AD4170 has an internal temperature sensor that can be read using the
ADC. Whenever possible, configure an IIO channel to provide the chip's
temperature.
Reviewed-by: Nuno Sá <nuno.sa@analog.com>
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
No changes since v3.
drivers/iio/adc/ad4170.c | 72 ++++++++++++++++++++++++++++++++++++++--
1 file changed, 69 insertions(+), 3 deletions(-)
diff --git a/drivers/iio/adc/ad4170.c b/drivers/iio/adc/ad4170.c
index b3189c5f8078..253c9ca9b3e6 100644
--- a/drivers/iio/adc/ad4170.c
+++ b/drivers/iio/adc/ad4170.c
@@ -883,6 +883,27 @@ static const struct iio_chan_spec ad4170_channel_template = {
},
};
+static const struct iio_chan_spec ad4170_temp_channel_template = {
+ .type = IIO_TEMP,
+ .indexed = 0,
+ .channel = 17,
+ .channel2 = 17,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
+ BIT(IIO_CHAN_INFO_SCALE) |
+ BIT(IIO_CHAN_INFO_OFFSET) |
+ BIT(IIO_CHAN_INFO_CALIBSCALE) |
+ BIT(IIO_CHAN_INFO_CALIBBIAS) |
+ BIT(IIO_CHAN_INFO_SAMP_FREQ),
+ .info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
+ .scan_type = {
+ .sign = 's',
+ .realbits = 24,
+ .storagebits = 32,
+ .shift = 8,
+ .endianness = IIO_BE,
+ },
+};
+
/*
* Receives the number of a multiplexed AD4170 input (ain_n), and stores the
* voltage (in µV) of the specified input into ain_voltage. If the input number
@@ -1182,9 +1203,27 @@ static int ad4170_read_raw(struct iio_dev *indio_dev,
return ret;
case IIO_CHAN_INFO_SCALE:
pga = FIELD_GET(AD4170_AFE_PGA_GAIN_MSK, setup->afe);
- *val = chan_info->scale_tbl[pga][0];
- *val2 = chan_info->scale_tbl[pga][1];
- return IIO_VAL_INT_PLUS_NANO;
+ switch (chan->type) {
+ case IIO_VOLTAGE:
+ *val = chan_info->scale_tbl[pga][0];
+ *val2 = chan_info->scale_tbl[pga][1];
+ return IIO_VAL_INT_PLUS_NANO;
+
+ case IIO_TEMP:
+ /*
+ * The scale_tbl converts output codes to mV units so
+ * multiply by MILLI to make the factor convert to µV.
+ * Then, apply the temperature sensor change sensitivity
+ * of 477 μV/K. Finally, multiply the result by MILLI
+ * again to comply with milli degrees Celsius IIO ABI.
+ */
+ *val = 0;
+ *val2 = DIV_ROUND_CLOSEST(chan_info->scale_tbl[pga][1] * MILLI, 477) *
+ MILLI;
+ return IIO_VAL_INT_PLUS_NANO;
+ default:
+ return -EINVAL;
+ }
case IIO_CHAN_INFO_OFFSET:
pga = FIELD_GET(AD4170_AFE_PGA_GAIN_MSK, setup->afe);
*val = chan_info->offset_tbl[pga];
@@ -1834,12 +1873,39 @@ static int ad4170_parse_channels(struct iio_dev *indio_dev)
if (num_channels > AD4170_MAX_CHANNELS)
return dev_err_probe(dev, -EINVAL, "Too many channels\n");
+ /* Add one for temperature */
+ num_channels = min(num_channels + 1, AD4170_MAX_CHANNELS);
+
device_for_each_child_node_scoped(dev, child) {
ret = ad4170_parse_channel_node(indio_dev, child, chan_num++);
if (ret)
return ret;
}
+ /*
+ * Add internal temperature sensor channel if the maximum number of
+ * channels has not been reached.
+ */
+ if (num_channels < AD4170_MAX_CHANNELS) {
+ struct ad4170_setup *setup = &st->chan_infos[chan_num].setup;
+
+ st->chans[chan_num] = ad4170_temp_channel_template;
+ st->chans[chan_num].address = chan_num;
+ st->chans[chan_num].scan_index = chan_num;
+
+ st->chan_infos[chan_num].setup_num = AD4170_INVALID_SETUP;
+ st->chan_infos[chan_num].initialized = true;
+
+ setup->afe |= FIELD_PREP(AD4170_AFE_REF_SELECT_MSK,
+ AD4170_REF_AVDD);
+
+ ret = ad4170_get_input_range(st, &st->chans[chan_num], chan_num,
+ AD4170_REF_AVDD);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Invalid input config\n");
+
+ st->chan_infos[chan_num].input_range_uv = ret;
+ }
indio_dev->num_channels = num_channels;
indio_dev->channels = st->chans;
--
2.47.2
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v5 10/11] iio: adc: ad4170: Add support for weigh scale and RTD sensors
2025-06-10 20:30 [PATCH v5 00/11] iio: adc: Add support for AD4170 series of ADCs Marcelo Schmitt
` (8 preceding siblings ...)
2025-06-10 20:33 ` [PATCH v5 09/11] iio: adc: ad4170: Add support for internal temperature sensor Marcelo Schmitt
@ 2025-06-10 20:33 ` Marcelo Schmitt
2025-06-10 20:34 ` [PATCH v5 11/11] iio: adc: ad4170: Add timestamp channel Marcelo Schmitt
2025-06-14 11:04 ` [PATCH v5 00/11] iio: adc: Add support for AD4170 series of ADCs Jonathan Cameron
11 siblings, 0 replies; 35+ messages in thread
From: Marcelo Schmitt @ 2025-06-10 20:33 UTC (permalink / raw)
To: linux-iio, devicetree, linux-gpio, linux-kernel
Cc: jic23, lars, Michael.Hennerich, dlechner, nuno.sa, andy, robh,
krzk+dt, conor+dt, linus.walleij, brgl, marcelo.schmitt1
The AD4170 design has features to aid interfacing with weigh scale and RTD
sensors that are expected to be setup with external circuitry for proper
sensor operation. A key characteristic of those sensors is that the circuit
they are in must be excited with a pair of signals. The external circuit
can be excited either by voltage supply or by AD4170 excitation signals.
The sensor can then be read through a different pair of lines that are
connected to AD4170 ADC.
Configure AD4170 to handle external circuit sensors.
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
Change log v4 -> v5
- Tweaked commits/patches to reduce diff.
- Dropped unneeded local variable.
drivers/iio/adc/ad4170.c | 494 ++++++++++++++++++++++++++++++++++++++-
1 file changed, 490 insertions(+), 4 deletions(-)
diff --git a/drivers/iio/adc/ad4170.c b/drivers/iio/adc/ad4170.c
index 253c9ca9b3e6..96274b20e9d2 100644
--- a/drivers/iio/adc/ad4170.c
+++ b/drivers/iio/adc/ad4170.c
@@ -67,6 +67,8 @@
#define AD4170_FILTER_FS_REG(x) (0xC7 + 14 * (x))
#define AD4170_OFFSET_REG(x) (0xCA + 14 * (x))
#define AD4170_GAIN_REG(x) (0xCD + 14 * (x))
+#define AD4170_V_BIAS_REG 0x135
+#define AD4170_CURRENT_SRC_REG(x) (0x139 + 2 * (x))
#define AD4170_GPIO_MODE_REG 0x191
#define AD4170_GPIO_OUTPUT_REG 0x193
#define AD4170_GPIO_INPUT_REG 0x195
@@ -98,6 +100,10 @@
#define AD4170_CHAN_MAP_AINP_MSK GENMASK(12, 8)
#define AD4170_CHAN_MAP_AINM_MSK GENMASK(4, 0)
+/* AD4170_MISC_REG */
+#define AD4170_MISC_CHOP_IEXC_MSK GENMASK(15, 14)
+#define AD4170_MISC_CHOP_ADC_MSK GENMASK(9, 8)
+
/* AD4170_AFE_REG */
#define AD4170_AFE_REF_BUF_M_MSK GENMASK(11, 10)
#define AD4170_AFE_REF_BUF_P_MSK GENMASK(9, 8)
@@ -108,12 +114,19 @@
/* AD4170_FILTER_REG */
#define AD4170_FILTER_FILTER_TYPE_MSK GENMASK(3, 0)
+/* AD4170_CURRENT_SRC_REG */
+#define AD4170_CURRENT_SRC_I_OUT_PIN_MSK GENMASK(12, 8)
+#define AD4170_CURRENT_SRC_I_OUT_VAL_MSK GENMASK(2, 0)
+
/* AD4170_GPIO_MODE_REG */
#define AD4170_GPIO_MODE_GPIO0_MSK GENMASK(1, 0)
#define AD4170_GPIO_MODE_GPIO1_MSK GENMASK(3, 2)
#define AD4170_GPIO_MODE_GPIO2_MSK GENMASK(5, 4)
#define AD4170_GPIO_MODE_GPIO3_MSK GENMASK(7, 6)
+/* AD4170_GPIO_OUTPUT_REG */
+#define AD4170_GPIO_OUTPUT_GPIO_MSK(x) BIT(x)
+
/* AD4170 register constants */
/* AD4170_CLOCK_CTRL_REG constants */
@@ -137,6 +150,11 @@
#define AD4170_CHAN_MAP_REFIN2_N 28
#define AD4170_CHAN_MAP_REFOUT 29
+/* AD4170_MISC_REG constants */
+#define AD4170_MISC_CHOP_IEXC_PAIR1 0x1
+#define AD4170_MISC_CHOP_IEXC_PAIR2 0x2
+#define AD4170_MISC_CHOP_IEXC_BOTH 0x3
+
/* AD4170_PIN_MUXING_REG constants */
#define AD4170_PIN_MUXING_DIG_AUX1_DISABLED 0x0
#define AD4170_PIN_MUXING_DIG_AUX1_RDY 0x1
@@ -154,6 +172,10 @@
#define AD4170_FILTER_FILTER_TYPE_SINC5 0x4
#define AD4170_FILTER_FILTER_TYPE_SINC3 0x6
+/* AD4170_CURRENT_SRC_REG constants */
+#define AD4170_CURRENT_SRC_I_OUT_PIN_AIN(x) (x)
+#define AD4170_CURRENT_SRC_I_OUT_PIN_GPIO(x) ((x) + 17)
+
/* AD4170_GPIO_MODE_REG constants */
#define AD4170_GPIO_MODE_GPIO_INPUT 1
#define AD4170_GPIO_MODE_GPIO_OUTPUT 2
@@ -167,6 +189,7 @@
#define AD4170_MAX_SETUPS 8
#define AD4170_INVALID_SETUP 9
#define AD4170_SPI_MAX_XFER_LEN 6
+#define AD4170_NUM_CURRENT_SRC 4
#define AD4170_DEFAULT_SAMP_RATE (125 * HZ_PER_KHZ)
#define AD4170_INT_REF_2_5V 2500000
@@ -188,8 +211,19 @@
#define AD4170_ADC_CTRL_CONT_READ_EXIT 0xA5
+/* Analog pin functions */
+#define AD4170_PIN_UNASSIGNED 0x00
+#define AD4170_PIN_ANALOG_IN 0x01
+#define AD4170_PIN_CURRENT_OUT 0x02
+#define AD4170_PIN_VBIAS 0x04
+
/* GPIO pin functions */
#define AD4170_GPIO_UNASSIGNED 0x00
+#define AD4170_GPIO_AC_EXCITATION 0x02
+#define AD4170_GPIO_OUTPUT 0x04
+
+/* Current source */
+#define AD4170_CURRENT_SRC_DISABLED 0xFF
static const unsigned int ad4170_reg_size[] = {
[AD4170_CONFIG_A_REG] = 1,
@@ -228,6 +262,8 @@ static const unsigned int ad4170_reg_size[] = {
[AD4170_OFFSET_REG(5) ... AD4170_GAIN_REG(5)] = 3,
[AD4170_OFFSET_REG(6) ... AD4170_GAIN_REG(6)] = 3,
[AD4170_OFFSET_REG(7) ... AD4170_GAIN_REG(7)] = 3,
+ [AD4170_V_BIAS_REG] = 2,
+ [AD4170_CURRENT_SRC_REG(0) ... AD4170_CURRENT_SRC_REG(3)] = 2,
[AD4170_GPIO_MODE_REG] = 2,
[AD4170_GPIO_OUTPUT_REG] = 2,
[AD4170_GPIO_INPUT_REG] = 2,
@@ -290,6 +326,41 @@ static const unsigned int ad4170_sinc5_filt_fs_tbl[] = {
1, 2, 4, 8, 12, 16, 20, 40, 48, 80, 100, 256,
};
+static const unsigned int ad4170_iout_pin_tbl[] = {
+ AD4170_CURRENT_SRC_I_OUT_PIN_AIN(0),
+ AD4170_CURRENT_SRC_I_OUT_PIN_AIN(1),
+ AD4170_CURRENT_SRC_I_OUT_PIN_AIN(2),
+ AD4170_CURRENT_SRC_I_OUT_PIN_AIN(3),
+ AD4170_CURRENT_SRC_I_OUT_PIN_AIN(4),
+ AD4170_CURRENT_SRC_I_OUT_PIN_AIN(5),
+ AD4170_CURRENT_SRC_I_OUT_PIN_AIN(6),
+ AD4170_CURRENT_SRC_I_OUT_PIN_AIN(7),
+ AD4170_CURRENT_SRC_I_OUT_PIN_AIN(8),
+ AD4170_CURRENT_SRC_I_OUT_PIN_GPIO(0),
+ AD4170_CURRENT_SRC_I_OUT_PIN_GPIO(1),
+ AD4170_CURRENT_SRC_I_OUT_PIN_GPIO(2),
+ AD4170_CURRENT_SRC_I_OUT_PIN_GPIO(3),
+};
+
+static const unsigned int ad4170_iout_current_ua_tbl[] = {
+ 0, 10, 50, 100, 250, 500, 1000, 1500,
+};
+
+enum ad4170_sensor_enum {
+ AD4170_ADC_SENSOR = 0,
+ AD4170_WEIGH_SCALE_SENSOR = 1,
+ AD4170_RTD_SENSOR = 2,
+ AD4170_THERMOCOUPLE_SENSOR = 3,
+};
+
+/* maps adi,sensor-type property value to enum */
+static const char * const ad4170_sensor_type[] = {
+ [AD4170_ADC_SENSOR] = "adc",
+ [AD4170_WEIGH_SCALE_SENSOR] = "weighscale",
+ [AD4170_RTD_SENSOR] = "rtd",
+ [AD4170_THERMOCOUPLE_SENSOR] = "thermocouple",
+};
+
struct ad4170_chip_info {
const char *name;
};
@@ -374,6 +445,7 @@ struct ad4170_state {
struct gpio_chip gpiochip;
unsigned int clock_ctrl;
int gpio_fn[AD4170_NUM_GPIO_PINS];
+ unsigned int cur_src_pins[AD4170_NUM_CURRENT_SRC];
/*
* DMA (thus cache coherency maintenance) requires the transfer buffers
* to live in their own cache lines.
@@ -918,6 +990,19 @@ static int ad4170_get_ain_voltage_uv(struct ad4170_state *st, int ain_n,
int v_diff;
*ain_voltage = 0;
+ /*
+ * The voltage bias (vbias) sets the common-mode voltage of the channel
+ * to (AVDD + AVSS)/2. If provided, AVSS supply provides the magnitude
+ * (absolute value) of the negative voltage supplied to the AVSS pin.
+ * So, we do AVDD - AVSS to compute the DC voltage generated by the bias
+ * voltage generator.
+ */
+ if (st->pins_fn[ain_n] & AD4170_PIN_VBIAS) {
+ int v_diff = st->vrefs_uv[AD4170_AVDD_SUP] - st->vrefs_uv[AD4170_AVSS_SUP];
+ *ain_voltage = v_diff / 2;
+ return 0;
+ }
+
if (ain_n <= AD4170_CHAN_MAP_TEMP_SENSOR)
return 0;
@@ -972,6 +1057,19 @@ static int ad4170_get_ain_voltage_uv(struct ad4170_state *st, int ain_n,
}
}
+static int ad4170_validate_analog_input(struct ad4170_state *st, int pin)
+{
+ if (pin <= AD4170_MAX_ANALOG_PINS) {
+ if (st->pins_fn[pin] & AD4170_PIN_CURRENT_OUT)
+ return dev_err_probe(&st->spi->dev, -EINVAL,
+ "Pin %d already used with fn %u.\n",
+ pin, st->pins_fn[pin]);
+
+ st->pins_fn[pin] |= AD4170_PIN_ANALOG_IN;
+ }
+ return 0;
+}
+
static int ad4170_validate_channel_input(struct ad4170_state *st, int pin, bool com)
{
/* Check common-mode input pin is mapped to a special input. */
@@ -986,7 +1084,7 @@ static int ad4170_validate_channel_input(struct ad4170_state *st, int pin, bool
"Invalid analog input pin number. %d\n",
pin);
- return 0;
+ return ad4170_validate_analog_input(st, pin);
}
/*
@@ -1723,6 +1821,371 @@ static int ad4170_gpio_init(struct iio_dev *indio_dev)
return devm_gpiochip_add_data(&st->spi->dev, &st->gpiochip, indio_dev);
}
+static int ad4170_validate_excitation_pin(struct ad4170_state *st, u32 pin)
+{
+ struct device *dev = &st->spi->dev;
+ unsigned int i;
+
+ /* Check the pin number is valid */
+ for (i = 0; i < ARRAY_SIZE(ad4170_iout_pin_tbl); i++)
+ if (ad4170_iout_pin_tbl[i] == pin)
+ break;
+
+ if (i == ARRAY_SIZE(ad4170_iout_pin_tbl))
+ return dev_err_probe(dev, -EINVAL,
+ "Invalid excitation pin: %u\n",
+ pin);
+
+ /* Check the pin is available */
+ if (pin <= AD4170_MAX_ANALOG_PINS) {
+ if (st->pins_fn[pin] != AD4170_PIN_UNASSIGNED)
+ return dev_err_probe(dev, -EINVAL,
+ "Pin %u already used with fn %u\n",
+ pin, st->pins_fn[pin]);
+
+ st->pins_fn[pin] |= AD4170_PIN_CURRENT_OUT;
+ } else {
+ unsigned int gpio = pin - AD4170_CURRENT_SRC_I_OUT_PIN_GPIO(0);
+
+ if (st->gpio_fn[gpio] != AD4170_GPIO_UNASSIGNED)
+ return dev_err_probe(dev, -EINVAL,
+ "GPIO %u already used with fn %u\n",
+ gpio, st->gpio_fn[gpio]);
+
+ st->gpio_fn[gpio] |= AD4170_GPIO_AC_EXCITATION;
+ }
+
+ return 0;
+}
+
+static int ad4170_validate_excitation_pins(struct ad4170_state *st,
+ u32 *exc_pins, int num_exc_pins)
+{
+ unsigned int i;
+ int ret;
+
+ for (i = 0; i < num_exc_pins; i++) {
+ ret = ad4170_validate_excitation_pin(st, exc_pins[i]);
+ if (ret)
+ return ret;
+ }
+ return 0;
+}
+
+static const char *const ad4170_i_out_pin_dt_props[] = {
+ "adi,excitation-pin-0",
+ "adi,excitation-pin-1",
+ "adi,excitation-pin-2",
+ "adi,excitation-pin-3",
+};
+
+static const char *const ad4170_i_out_val_dt_props[] = {
+ "adi,excitation-current-0-microamp",
+ "adi,excitation-current-1-microamp",
+ "adi,excitation-current-2-microamp",
+ "adi,excitation-current-3-microamp",
+};
+
+/*
+ * Parses firmware data describing output current source setup. There are 4
+ * excitation currents (IOUT0 to IOUT3) that can be configured independently.
+ * Excitation currents are added if they are output on the same pin.
+ */
+static int ad4170_parse_exc_current(struct ad4170_state *st,
+ struct fwnode_handle *child,
+ unsigned int *exc_pins,
+ unsigned int *exc_curs,
+ unsigned int *num_exc_pins)
+{
+ struct device *dev = &st->spi->dev;
+ unsigned int num_pins, i, j;
+ u32 pin, val;
+ int ret;
+
+ num_pins = 0;
+ for (i = 0; i < AD4170_NUM_CURRENT_SRC; i++) {
+ /* Parse excitation current output pin properties. */
+ pin = AD4170_CURRENT_SRC_I_OUT_PIN_AIN(0);
+ ret = fwnode_property_read_u32(child, ad4170_i_out_pin_dt_props[i],
+ &pin);
+ if (ret)
+ continue;
+
+ exc_pins[num_pins] = pin;
+
+ /* Parse excitation current value properties. */
+ val = ad4170_iout_current_ua_tbl[0];
+ fwnode_property_read_u32(child,
+ ad4170_i_out_val_dt_props[i], &val);
+
+ for (j = 0; j < ARRAY_SIZE(ad4170_iout_current_ua_tbl); j++)
+ if (ad4170_iout_current_ua_tbl[j] == val)
+ break;
+
+ if (j == ARRAY_SIZE(ad4170_iout_current_ua_tbl))
+ return dev_err_probe(dev, -EINVAL, "Invalid %s: %uuA\n",
+ ad4170_i_out_val_dt_props[i], val);
+
+ exc_curs[num_pins] = j;
+ num_pins++;
+ }
+ *num_exc_pins = num_pins;
+
+ return 0;
+}
+
+static int ad4170_setup_current_src(struct ad4170_state *st,
+ struct fwnode_handle *child,
+ struct ad4170_setup *setup, u32 *exc_pins,
+ unsigned int *exc_curs, int num_exc_pins,
+ bool ac_excited)
+{
+ unsigned int exc_cur_pair, i, j;
+ int ret;
+
+ for (i = 0; i < num_exc_pins; i++) {
+ unsigned int exc_cur = exc_curs[i];
+ unsigned int pin = exc_pins[i];
+ unsigned int current_src = 0;
+
+ for (j = 0; j < AD4170_NUM_CURRENT_SRC; j++)
+ if (st->cur_src_pins[j] == AD4170_CURRENT_SRC_DISABLED)
+ break;
+
+ if (j == AD4170_NUM_CURRENT_SRC)
+ return dev_err_probe(&st->spi->dev, -EINVAL,
+ "Too many excitation current sources\n");
+
+ current_src |= FIELD_PREP(AD4170_CURRENT_SRC_I_OUT_PIN_MSK, pin);
+ current_src |= FIELD_PREP(AD4170_CURRENT_SRC_I_OUT_VAL_MSK, exc_cur);
+ st->cur_src_pins[j] = pin;
+ ret = regmap_write(st->regmap, AD4170_CURRENT_SRC_REG(j),
+ current_src);
+ if (ret)
+ return ret;
+ }
+
+ if (!ac_excited)
+ return 0;
+
+ if (num_exc_pins < 2)
+ return dev_err_probe(&st->spi->dev, -EINVAL,
+ "Current chopping requested but only one pin provided: %u\n",
+ exc_pins[0]);
+
+ /*
+ * Two use cases to handle here:
+ * - 2 pairs of excitation currents;
+ * - 1 pair of excitation currents.
+ */
+ if (num_exc_pins == 4) {
+ for (i = 0; i < AD4170_NUM_CURRENT_SRC; i++)
+ if (st->cur_src_pins[i] != exc_pins[i])
+ return dev_err_probe(&st->spi->dev, -EINVAL,
+ "Unable to use 4 exc pins\n");
+ } else {
+ /*
+ * Excitation current chopping is configured in pairs. Current
+ * sources IOUT0 and IOUT1 form pair 1, IOUT2 and IOUT3 make up
+ * pair 2. So, if current chopping was requested, check if the
+ * first end of the first pair of excitation currents is
+ * available. Try the next pair if IOUT0 has already been
+ * configured for another channel.
+ */
+ i = st->cur_src_pins[0] == exc_pins[0] ? 0 : 2;
+
+ if (st->cur_src_pins[i] != exc_pins[0] ||
+ st->cur_src_pins[i + 1] != exc_pins[1])
+ return dev_err_probe(&st->spi->dev, -EINVAL,
+ "Failed to setup current chopping\n");
+
+ st->cur_src_pins[i] = exc_pins[0];
+ st->cur_src_pins[i + 1] = exc_pins[1];
+
+ if (i == 0)
+ exc_cur_pair = AD4170_MISC_CHOP_IEXC_PAIR1;
+ else
+ exc_cur_pair = AD4170_MISC_CHOP_IEXC_PAIR2;
+ }
+
+ /*
+ * Configure excitation current chopping.
+ * Chop both pairs if using four excitation pins.
+ */
+ setup->misc |= FIELD_PREP(AD4170_MISC_CHOP_IEXC_MSK,
+ num_exc_pins == 2 ?
+ exc_cur_pair :
+ AD4170_MISC_CHOP_IEXC_BOTH);
+
+ return 0;
+}
+
+static int ad4170_setup_bridge(struct ad4170_state *st,
+ struct fwnode_handle *child,
+ struct ad4170_setup *setup, u32 *exc_pins,
+ unsigned int *exc_curs, int num_exc_pins,
+ bool ac_excited)
+{
+ unsigned long gpio_mask;
+ unsigned int i;
+ int ret;
+
+ /*
+ * If a specific current is provided through
+ * adi,excitation-current-n-microamp, set excitation pins provided
+ * through adi,excitation-pin-n to excite the bridge circuit.
+ */
+ for (i = 0; i < num_exc_pins; i++)
+ if (exc_curs[i] > 0)
+ return ad4170_setup_current_src(st, child, setup, exc_pins,
+ exc_curs, num_exc_pins,
+ ac_excited);
+
+ /*
+ * Else, use predefined ACX1, ACX1 negated, ACX2, ACX2 negated signals
+ * to AC excite the bridge. Those signals are output on GPIO2, GPIO0,
+ * GPIO3, and GPIO1, respectively. If only two pins are specified for AC
+ * excitation, use ACX1 and ACX2 (GPIO2 and GPIO3).
+ *
+ * Also, to avoid any short-circuit condition when more than one channel
+ * is enabled, set GPIO2 and GPIO0 high, and set GPIO1 and GPIO3 low to
+ * DC excite the bridge whenever a channel without AC excitation is
+ * selected. That is needed because GPIO pins are controlled by the next
+ * highest priority GPIO function when a channel doesn't enable AC
+ * excitation. See datasheet Figure 113 Weigh Scale (AC Excitation) for
+ * the reference circuit diagram.
+ */
+ if (num_exc_pins == 2) {
+ setup->misc |= FIELD_PREP(AD4170_MISC_CHOP_ADC_MSK, 0x3);
+
+ gpio_mask = AD4170_GPIO_MODE_GPIO3_MSK | AD4170_GPIO_MODE_GPIO2_MSK;
+ ret = regmap_update_bits(st->regmap, AD4170_GPIO_MODE_REG, gpio_mask,
+ FIELD_PREP(AD4170_GPIO_MODE_GPIO3_MSK,
+ AD4170_GPIO_MODE_GPIO_OUTPUT) |
+ FIELD_PREP(AD4170_GPIO_MODE_GPIO2_MSK,
+ AD4170_GPIO_MODE_GPIO_OUTPUT));
+ if (ret)
+ return ret;
+
+ /*
+ * Set GPIO2 high and GPIO3 low to DC excite the bridge when
+ * a different channel is selected.
+ */
+ gpio_mask = AD4170_GPIO_OUTPUT_GPIO_MSK(3) |
+ AD4170_GPIO_OUTPUT_GPIO_MSK(2);
+ ret = regmap_update_bits(st->regmap, AD4170_GPIO_OUTPUT_REG, gpio_mask,
+ FIELD_PREP(AD4170_GPIO_OUTPUT_GPIO_MSK(3), 0) |
+ FIELD_PREP(AD4170_GPIO_OUTPUT_GPIO_MSK(2), 1));
+ if (ret)
+ return ret;
+
+ st->gpio_fn[3] |= AD4170_GPIO_OUTPUT;
+ st->gpio_fn[2] |= AD4170_GPIO_OUTPUT;
+ } else {
+ setup->misc |= FIELD_PREP(AD4170_MISC_CHOP_ADC_MSK, 0x2);
+
+ gpio_mask = AD4170_GPIO_MODE_GPIO3_MSK | AD4170_GPIO_MODE_GPIO2_MSK |
+ AD4170_GPIO_MODE_GPIO1_MSK | AD4170_GPIO_MODE_GPIO0_MSK;
+ ret = regmap_update_bits(st->regmap, AD4170_GPIO_MODE_REG, gpio_mask,
+ FIELD_PREP(AD4170_GPIO_MODE_GPIO3_MSK,
+ AD4170_GPIO_MODE_GPIO_OUTPUT) |
+ FIELD_PREP(AD4170_GPIO_MODE_GPIO2_MSK,
+ AD4170_GPIO_MODE_GPIO_OUTPUT) |
+ FIELD_PREP(AD4170_GPIO_MODE_GPIO1_MSK,
+ AD4170_GPIO_MODE_GPIO_OUTPUT) |
+ FIELD_PREP(AD4170_GPIO_MODE_GPIO0_MSK,
+ AD4170_GPIO_MODE_GPIO_OUTPUT));
+ if (ret)
+ return ret;
+
+ /*
+ * Set GPIO2 and GPIO0 high, and set GPIO1 and GPIO3 low to DC
+ * excite the bridge when a different channel is selected.
+ */
+ gpio_mask = AD4170_GPIO_OUTPUT_GPIO_MSK(3) |
+ AD4170_GPIO_OUTPUT_GPIO_MSK(2) |
+ AD4170_GPIO_OUTPUT_GPIO_MSK(1) |
+ AD4170_GPIO_OUTPUT_GPIO_MSK(0);
+ ret = regmap_update_bits(st->regmap, AD4170_GPIO_OUTPUT_REG, gpio_mask,
+ FIELD_PREP(AD4170_GPIO_OUTPUT_GPIO_MSK(3), 0) |
+ FIELD_PREP(AD4170_GPIO_OUTPUT_GPIO_MSK(2), 1) |
+ FIELD_PREP(AD4170_GPIO_OUTPUT_GPIO_MSK(1), 0) |
+ FIELD_PREP(AD4170_GPIO_OUTPUT_GPIO_MSK(0), 1));
+ if (ret)
+ return ret;
+
+ st->gpio_fn[3] |= AD4170_GPIO_OUTPUT;
+ st->gpio_fn[2] |= AD4170_GPIO_OUTPUT;
+ st->gpio_fn[1] |= AD4170_GPIO_OUTPUT;
+ st->gpio_fn[0] |= AD4170_GPIO_OUTPUT;
+ }
+
+ return 0;
+}
+
+static int ad4170_setup_rtd(struct ad4170_state *st,
+ struct fwnode_handle *child,
+ struct ad4170_setup *setup, u32 *exc_pins,
+ unsigned int *exc_curs, int num_exc_pins, bool ac_excited)
+{
+ return ad4170_setup_current_src(st, child, setup, exc_pins,
+ exc_curs, num_exc_pins, ac_excited);
+}
+
+static int ad4170_parse_external_sensor(struct ad4170_state *st,
+ struct fwnode_handle *child,
+ struct ad4170_setup *setup,
+ struct iio_chan_spec *chan, u8 s_type)
+{
+ unsigned int num_exc_pins, reg_val;
+ struct device *dev = &st->spi->dev;
+ u32 pins[2], exc_pins[4], exc_curs[4];
+ bool ac_excited, vbias;
+ int ret;
+
+ ret = fwnode_property_read_u32_array(child, "diff-channels", pins,
+ ARRAY_SIZE(pins));
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to read sensor diff-channels\n");
+
+ chan->differential = true;
+ chan->channel = pins[0];
+ chan->channel2 = pins[1];
+
+ ret = ad4170_parse_exc_current(st, child, exc_pins, exc_curs, &num_exc_pins);
+ if (ret)
+ return ret;
+
+ /* The external sensor may not need excitation from the ADC chip. */
+ if (num_exc_pins == 0)
+ return 0;
+
+ ret = ad4170_validate_excitation_pins(st, exc_pins, num_exc_pins);
+ if (ret)
+ return ret;
+
+ ac_excited = fwnode_property_read_bool(child, "adi,excitation-ac");
+
+ if (s_type == AD4170_THERMOCOUPLE_SENSOR) {
+ vbias = fwnode_property_read_bool(child, "adi,vbias");
+ if (vbias) {
+ st->pins_fn[chan->channel2] |= AD4170_PIN_VBIAS;
+ reg_val = BIT(chan->channel2);
+ return regmap_write(st->regmap, AD4170_V_BIAS_REG,
+ reg_val);
+ }
+ }
+ if (s_type == AD4170_WEIGH_SCALE_SENSOR)
+ ret = ad4170_setup_bridge(st, child, setup, exc_pins, exc_curs,
+ num_exc_pins, ac_excited);
+ else
+ ret = ad4170_setup_rtd(st, child, setup, exc_pins, exc_curs,
+ num_exc_pins, ac_excited);
+
+ return ret;
+}
+
static int ad4170_parse_reference(struct ad4170_state *st,
struct fwnode_handle *child,
struct ad4170_setup *setup)
@@ -1808,6 +2271,7 @@ static int ad4170_parse_channel_node(struct iio_dev *indio_dev,
struct ad4170_setup *setup;
struct iio_chan_spec *chan;
unsigned int ref_select;
+ unsigned int s_type;
unsigned int ch_reg;
bool bipolar;
int ret;
@@ -1836,10 +2300,28 @@ static int ad4170_parse_channel_node(struct iio_dev *indio_dev,
if (ret)
return ret;
- ret = ad4170_parse_adc_channel_type(dev, child, chan);
- if (ret < 0)
- return ret;
+ ret = fwnode_property_match_property_string(child, "adi,sensor-type",
+ ad4170_sensor_type,
+ ARRAY_SIZE(ad4170_sensor_type));
+ /* Default to conventional ADC channel if sensor type not present */
+ s_type = ret < 0 ? AD4170_ADC_SENSOR : ret;
+ switch (s_type) {
+ case AD4170_ADC_SENSOR:
+ ret = ad4170_parse_adc_channel_type(dev, child, chan);
+ if (ret)
+ return ret;
+
+ break;
+ case AD4170_WEIGH_SCALE_SENSOR:
+ case AD4170_THERMOCOUPLE_SENSOR:
+ case AD4170_RTD_SENSOR:
+ ret = ad4170_parse_external_sensor(st, child, setup, chan, s_type);
+ if (ret)
+ return ret;
+
+ break;
+ }
bipolar = fwnode_property_read_bool(child, "bipolar");
setup->afe |= FIELD_PREP(AD4170_AFE_BIPOLAR_MSK, bipolar);
if (bipolar)
@@ -2035,6 +2517,7 @@ static int ad4170_parse_firmware(struct iio_dev *indio_dev)
struct ad4170_state *st = iio_priv(indio_dev);
struct device *dev = &st->spi->dev;
int reg_data, ret;
+ unsigned int i;
ret = ad4170_clock_select(indio_dev);
if (ret)
@@ -2044,6 +2527,9 @@ static int ad4170_parse_firmware(struct iio_dev *indio_dev)
if (ret)
return ret;
+ for (i = 0; i < AD4170_NUM_CURRENT_SRC; i++)
+ st->cur_src_pins[i] = AD4170_CURRENT_SRC_DISABLED;
+
/* On power on, device defaults to using SDO pin for data ready signal */
st->int_pin_sel = AD4170_INT_PIN_SDO;
ret = device_property_match_property_string(dev, "interrupt-names",
--
2.47.2
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v5 11/11] iio: adc: ad4170: Add timestamp channel
2025-06-10 20:30 [PATCH v5 00/11] iio: adc: Add support for AD4170 series of ADCs Marcelo Schmitt
` (9 preceding siblings ...)
2025-06-10 20:33 ` [PATCH v5 10/11] iio: adc: ad4170: Add support for weigh scale and RTD sensors Marcelo Schmitt
@ 2025-06-10 20:34 ` Marcelo Schmitt
2025-06-14 11:04 ` [PATCH v5 00/11] iio: adc: Add support for AD4170 series of ADCs Jonathan Cameron
11 siblings, 0 replies; 35+ messages in thread
From: Marcelo Schmitt @ 2025-06-10 20:34 UTC (permalink / raw)
To: linux-iio, devicetree, linux-gpio, linux-kernel
Cc: jic23, lars, Michael.Hennerich, dlechner, nuno.sa, andy, robh,
krzk+dt, conor+dt, linus.walleij, brgl, marcelo.schmitt1
Add timestamp channel allowing to record the moment at which ADC samples
are captured in buffered read mode.
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
No changes from v4.
drivers/iio/adc/ad4170.c | 21 +++++++++++++++++----
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/iio/adc/ad4170.c b/drivers/iio/adc/ad4170.c
index 96274b20e9d2..db244c1533b4 100644
--- a/drivers/iio/adc/ad4170.c
+++ b/drivers/iio/adc/ad4170.c
@@ -185,6 +185,7 @@
#define AD4170_NUM_ANALOG_PINS 9
#define AD4170_NUM_GPIO_PINS 4
#define AD4170_MAX_CHANNELS 16
+#define AD4170_MAX_IIO_CHANNELS (AD4170_MAX_CHANNELS + 1)
#define AD4170_MAX_ANALOG_PINS 8
#define AD4170_MAX_SETUPS 8
#define AD4170_INVALID_SETUP 9
@@ -429,7 +430,7 @@ struct ad4170_state {
int vrefs_uv[AD4170_MAX_SUP];
u32 mclk_hz;
struct ad4170_setup_info setup_infos[AD4170_MAX_SETUPS];
- struct iio_chan_spec chans[AD4170_MAX_CHANNELS];
+ struct iio_chan_spec chans[AD4170_MAX_IIO_CHANNELS];
struct ad4170_chan_info chan_infos[AD4170_MAX_CHANNELS];
struct spi_device *spi;
struct regmap *regmap;
@@ -446,6 +447,7 @@ struct ad4170_state {
unsigned int clock_ctrl;
int gpio_fn[AD4170_NUM_GPIO_PINS];
unsigned int cur_src_pins[AD4170_NUM_CURRENT_SRC];
+ unsigned int num_adc_chans;
/*
* DMA (thus cache coherency maintenance) requires the transfer buffers
* to live in their own cache lines.
@@ -2387,7 +2389,16 @@ static int ad4170_parse_channels(struct iio_dev *indio_dev)
return dev_err_probe(dev, ret, "Invalid input config\n");
st->chan_infos[chan_num].input_range_uv = ret;
+ chan_num++;
}
+ st->num_adc_chans = chan_num;
+
+ /* Add timestamp channel */
+ struct iio_chan_spec ts_chan = IIO_CHAN_SOFT_TIMESTAMP(chan_num);
+
+ st->chans[chan_num] = ts_chan;
+ num_channels = num_channels + 1;
+
indio_dev->num_channels = num_channels;
indio_dev->channels = st->chans;
@@ -2579,7 +2590,7 @@ static int ad4170_initial_config(struct iio_dev *indio_dev)
return dev_err_probe(dev, ret,
"Failed to set ADC mode to idle\n");
- for (i = 0; i < indio_dev->num_channels; i++) {
+ for (i = 0; i < st->num_adc_chans; i++) {
struct ad4170_chan_info *chan_info;
struct iio_chan_spec const *chan;
struct ad4170_setup *setup;
@@ -2704,7 +2715,7 @@ static int ad4170_buffer_predisable(struct iio_dev *indio_dev)
* is done after buffer disable. Disable all channels so only requested
* channels will be read.
*/
- for (i = 0; i < indio_dev->num_channels; i++) {
+ for (i = 0; i < st->num_adc_chans; i++) {
ret = ad4170_set_channel_enable(st, i, false);
if (ret)
return ret;
@@ -2754,7 +2765,9 @@ static irqreturn_t ad4170_trigger_handler(int irq, void *p)
memcpy(&st->bounce_buffer[i++], st->rx_buf, ARRAY_SIZE(st->rx_buf));
}
- iio_push_to_buffers(indio_dev, st->bounce_buffer);
+ iio_push_to_buffers_with_ts(indio_dev, st->bounce_buffer,
+ sizeof(st->bounce_buffer),
+ iio_get_time_ns(indio_dev));
err_out:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
--
2.47.2
^ permalink raw reply related [flat|nested] 35+ messages in thread
* Re: [PATCH v5 02/11] iio: adc: Add basic support for AD4170
2025-06-10 20:31 ` [PATCH v5 02/11] iio: adc: Add basic support for AD4170 Marcelo Schmitt
@ 2025-06-10 21:10 ` Andy Shevchenko
2025-06-11 21:04 ` Marcelo Schmitt
2025-06-16 20:41 ` David Lechner
2025-06-18 17:37 ` Dan Carpenter
2 siblings, 1 reply; 35+ messages in thread
From: Andy Shevchenko @ 2025-06-10 21:10 UTC (permalink / raw)
To: Marcelo Schmitt
Cc: linux-iio, devicetree, linux-gpio, linux-kernel, Ana-Maria Cusco,
jic23, lars, Michael.Hennerich, dlechner, nuno.sa, robh, krzk+dt,
conor+dt, linus.walleij, brgl, marcelo.schmitt1
On Tue, Jun 10, 2025 at 05:31:25PM -0300, Marcelo Schmitt wrote:
> From: Ana-Maria Cusco <ana-maria.cusco@analog.com>
>
> The AD4170 is a multichannel, low noise, 24-bit precision sigma-delta
> analog to digital converter. The AD4170 design offers a flexible data
> acquisition solution with crosspoint multiplexed analog inputs,
> configurable ADC voltage reference inputs, ultra-low noise integrated PGA,
> digital filtering, wide range of configurable output data rates, internal
> oscillator and temperature sensor, four GPIOs, and integrated features for
> interfacing with load cell weigh scales, RTD, and thermocouple sensors.
>
> Add basic support for the AD4170 ADC with the following features:
> - Single-shot read.
> - Analog front end PGA configuration.
> - Differential and pseudo-differential input configuration.
...
> +enum ad4170_ref_buf {
> + AD4170_REF_BUF_PRE, /* Pre-charge referrence buffer */
> + AD4170_REF_BUF_FULL, /* Full referrence buffering */
> + AD4170_REF_BUF_BYPASS /* Bypass referrence buffering */
Doesn't seem like a terminator. Please, leave trailing comma.
> +};
> +
> +enum ad4170_ref_select {
> + AD4170_REF_REFIN1,
> + AD4170_REF_REFIN2,
> + AD4170_REF_REFOUT,
> + AD4170_REF_AVDD
Ditto.
> +};
...
> + int pins_fn[AD4170_NUM_ANALOG_PINS];
Can be negative? If so, perhaps a comment like '-1 means no assigned function'.
...
> + return spi_write(st->spi, st->tx_buf, size + 2);
... + sizeof(reg) ?
...
> +static bool ad4170_setup_eq(struct ad4170_setup *a, struct ad4170_setup *b)
> +{
> + /*
> + * The use of static_assert() here is to make sure that, if
> + * struct ad4170_setup is ever changed (e.g. a field is added to the
> + * struct's declaration), the comparison below is adapted to keep
> + * comparing each of struct ad4170_setup fields.
> + */
Okay. But this also will trigger the case when the field just changes the type.
So, it also brings false positives. I really think this is wrong place to put
static_assert(). To me it looks like a solving rare problem, if any.
But I leave this to the IIO maintainers.
In my opinion static_assert() makes only sense when memcmp() is being used.
Otherwise it has prons and cons.
> + static_assert(sizeof(*a) ==
> + sizeof(struct {
> + u16 misc;
> + u16 afe;
> + u16 filter;
> + u16 filter_fs;
> + u32 offset;
> + u32 gain;
> + }));
> +
> + if (a->misc != b->misc ||
> + a->afe != b->afe ||
> + a->filter != b->filter ||
> + a->filter_fs != b->filter_fs ||
> + a->offset != b->offset ||
> + a->gain != b->gain)
> + return false;
> +
> + return true;
> +}
...
> + /*
> + * Some configurations can lead to invalid setups.
> + * For example, if AVSS = -2.5V, REF_SELECT set to REFOUT (REFOUT/AVSS),
> + * and pseudo-diff channel configuration set, then the input range
> + * should go from 0V to +VREF (single-ended - datasheet pg 10), but
> + * REFOUT/AVSS range would be -2.5V to 0V.
> + * Check the positive reference is higher than 0V for pseudo-diff
> + * channels.
> + */
Right, the Q is, can refp contain an error code here, rather than negative
value? The code above hints that in some case it may, but are all those cases
were caught up already? (Comment can be extended to explain this)
> + if (refp <= 0)
> + return dev_err_probe(dev, -EINVAL,
> + "REF+ <= GND for pseudo-diff chan %u\n",
> + ch_reg);
...
> +{
> + struct device *dev = &st->spi->dev;
> + u32 aux;
> +
> + /* Optional positive reference buffering */
> + aux = AD4170_REF_BUF_FULL; /* Default to full precharge buffer enabled. */
> + fwnode_property_read_u32(child, "adi,positive-reference-buffer", &aux);
> + if (aux < AD4170_REF_BUF_PRE || aux > AD4170_REF_BUF_BYPASS)
> + return dev_err_probe(dev, -EINVAL,
> + "Invalid adi,positive-reference-buffer: %u\n",
> + aux);
Note, if you make it like
const char *propname;
...
propname = "...";
and use in both places. Alternatively can be done like
return dev_err_probe(dev, -EINVAL, "Invalid %s %u\n",
"adi,positive-reference-buffer: ", aux);
This will save a few dozens of bytes in the object file and at runtime.
Same for other similar cases. And I believe I have already pointed that out.
> +
> + setup->afe |= FIELD_PREP(AD4170_AFE_REF_BUF_P_MSK, aux);
> +
> + /* Optional negative reference buffering */
> + aux = AD4170_REF_BUF_FULL; /* Default to full precharge buffer enabled. */
> + fwnode_property_read_u32(child, "adi,negative-reference-buffer", &aux);
> + if (aux < AD4170_REF_BUF_PRE || aux > AD4170_REF_BUF_BYPASS)
> + return dev_err_probe(dev, -EINVAL,
> + "Invalid adi,negative-reference-buffer: %u\n",
> + aux);
> +
> + setup->afe |= FIELD_PREP(AD4170_AFE_REF_BUF_M_MSK, aux);
> +
> + /* Optional voltage reference selection */
> + aux = AD4170_REF_REFOUT; /* Default reference selection. */
> + fwnode_property_read_u32(child, "adi,reference-select", &aux);
> + if (aux > AD4170_REF_AVDD)
> + return dev_err_probe(dev, -EINVAL,
> + "Invalid reference selected %u\n",
> + aux);
> +
> + setup->afe |= FIELD_PREP(AD4170_AFE_REF_SELECT_MSK, aux);
> +
> + return 0;
> +}
...
> +static int ad4170_parse_adc_channel_type(struct device *dev,
> + struct fwnode_handle *child,
> + struct iio_chan_spec *chan)
Ditto in this function.
...
> +static int ad4170_parse_channel_node(struct iio_dev *indio_dev,
> + struct fwnode_handle *child,
> + unsigned int chan_num)
> +{
> + struct ad4170_state *st = iio_priv(indio_dev);
> + struct device *dev = &st->spi->dev;
> + struct ad4170_chan_info *chan_info;
> + struct ad4170_setup *setup;
> + struct iio_chan_spec *chan;
> + unsigned int ref_select;
> + unsigned int ch_reg;
> + bool bipolar;
> + int ret;
> +
> + ret = fwnode_property_read_u32(child, "reg", &ch_reg);
> + if (ret)
> + return dev_err_probe(dev, -EINVAL,
Why not ret?
> + "Failed to read channel reg\n");
> +
> + if (ch_reg >= AD4170_MAX_CHANNELS)
> + return dev_err_probe(dev, -EINVAL,
> + "Channel idx greater than no of channels\n");
> +
> + chan = &st->chans[chan_num];
> + *chan = ad4170_channel_template;
> +
> + chan->address = ch_reg;
> + chan->scan_index = ch_reg;
> + chan_info = &st->chan_infos[chan->address];
> +
> + chan_info->setup_num = AD4170_INVALID_SETUP;
> + chan_info->initialized = true;
> +
> + setup = &chan_info->setup;
> + ret = ad4170_parse_reference(st, child, setup);
> + if (ret)
> + return ret;
> +
> + ret = ad4170_parse_adc_channel_type(dev, child, chan);
> + if (ret < 0)
What is the meaning of the positive returned value? Why is it not used?
> + return ret;
> +
> + bipolar = fwnode_property_read_bool(child, "bipolar");
> + setup->afe |= FIELD_PREP(AD4170_AFE_BIPOLAR_MSK, bipolar);
> + if (bipolar)
> + chan->scan_type.sign = 's';
> + else
> + chan->scan_type.sign = 'u';
> +
> + ret = ad4170_validate_channel(st, chan);
> + if (ret < 0)
Ditto.
> + return ret;
> +
> + ref_select = FIELD_GET(AD4170_AFE_REF_SELECT_MSK, setup->afe);
> + ret = ad4170_get_input_range(st, chan, ch_reg, ref_select);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "Invalid input config\n");
> +
> + chan_info->input_range_uv = ret;
> + return 0;
> +}
...
> +static int ad4170_parse_channels(struct iio_dev *indio_dev)
> +{
> + struct ad4170_state *st = iio_priv(indio_dev);
> + struct device *dev = &st->spi->dev;
> + unsigned int num_channels;
> + unsigned int chan_num = 0;
It's better to split, so it will make code robust against potential reuse of
the same variable in between.
> + int ret;
> +
> + num_channels = device_get_child_node_count(dev);
> +
Unneeded blank line.
> + if (num_channels > AD4170_MAX_CHANNELS)
> + return dev_err_probe(dev, -EINVAL, "Too many channels\n");
> +
> + device_for_each_child_node_scoped(dev, child) {
> + ret = ad4170_parse_channel_node(indio_dev, child, chan_num++);
> + if (ret)
> + return ret;
> + }
> +
> + indio_dev->num_channels = num_channels;
> + indio_dev->channels = st->chans;
> +
> + return 0;
> +}
...
> + /* Assume AVSS at GND (0V) if not provided */
> + st->vrefs_uv[AD4170_AVSS_SUP] = ret == -ENODEV ? 0 : -ret;
-ret ?!?!
Even if you know that *now* it can't have any other error code, it's quite
fragile.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v5 06/11] iio: adc: ad4170: Add support for buffered data capture
2025-06-10 20:32 ` [PATCH v5 06/11] iio: adc: ad4170: Add support for buffered data capture Marcelo Schmitt
@ 2025-06-10 21:17 ` Andy Shevchenko
0 siblings, 0 replies; 35+ messages in thread
From: Andy Shevchenko @ 2025-06-10 21:17 UTC (permalink / raw)
To: Marcelo Schmitt
Cc: linux-iio, devicetree, linux-gpio, linux-kernel, jic23, lars,
Michael.Hennerich, dlechner, nuno.sa, robh, krzk+dt, conor+dt,
linus.walleij, brgl, marcelo.schmitt1
On Tue, Jun 10, 2025 at 05:32:43PM -0300, Marcelo Schmitt wrote:
> Extend the AD4170 driver to allow buffered data capture in continuous read
> mode. In continuous read mode, the chip skips the instruction phase and
> outputs just ADC sample data, enabling faster sample rates to be reached.
> The internal channel sequencer always starts sampling from channel 0 and
> channel 0 must be enabled if more than one channel is selected for data
> capture. The scan mask validation callback checks if the aforementioned
> condition is met.
...
> +static bool ad4170_validate_scan_mask(struct iio_dev *indio_dev,
> + const unsigned long *scan_mask)
> +{
> + unsigned int masklength = iio_get_masklength(indio_dev);
> +
> + /*
> + * The channel sequencer cycles through the enabled channels in
> + * sequential order, from channel 0 to channel 15, bypassing disabled
> + * channels. When more than one channel is enabled, channel 0 must
> + * always be enabled. See datasheet channel_en register description at
> + * page 95.
> + */
> + if (bitmap_weight(scan_mask, masklength) > 1)
> + return test_bit(0, scan_mask);
> +
> + return bitmap_weight(scan_mask, masklength) == 1;
Hopefully compiler is smart enough to see the two calls for the same which
can't be modified on the fly, but it definitely can't assume that the
mask is one word long, meaning the bitmap API will choose the slow path
for them. I would rather take a temporary variable approach.
It also minimizes the risk of race conditions in case something changes the
data beneath (which is quite a nasty situation to begin with).
> +}
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v5 02/11] iio: adc: Add basic support for AD4170
2025-06-10 21:10 ` Andy Shevchenko
@ 2025-06-11 21:04 ` Marcelo Schmitt
2025-06-12 12:48 ` Andy Shevchenko
0 siblings, 1 reply; 35+ messages in thread
From: Marcelo Schmitt @ 2025-06-11 21:04 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Marcelo Schmitt, linux-iio, devicetree, linux-gpio, linux-kernel,
Ana-Maria Cusco, jic23, lars, Michael.Hennerich, dlechner,
nuno.sa, robh, krzk+dt, conor+dt, linus.walleij, brgl
On 06/11, Andy Shevchenko wrote:
> On Tue, Jun 10, 2025 at 05:31:25PM -0300, Marcelo Schmitt wrote:
> > From: Ana-Maria Cusco <ana-maria.cusco@analog.com>
> >
> > The AD4170 is a multichannel, low noise, 24-bit precision sigma-delta
> > analog to digital converter. The AD4170 design offers a flexible data
> > acquisition solution with crosspoint multiplexed analog inputs,
> > configurable ADC voltage reference inputs, ultra-low noise integrated PGA,
> > digital filtering, wide range of configurable output data rates, internal
> > oscillator and temperature sensor, four GPIOs, and integrated features for
> > interfacing with load cell weigh scales, RTD, and thermocouple sensors.
> >
> > Add basic support for the AD4170 ADC with the following features:
> > - Single-shot read.
> > - Analog front end PGA configuration.
> > - Differential and pseudo-differential input configuration.
>
> ...
>
> > + return spi_write(st->spi, st->tx_buf, size + 2);
>
> ... + sizeof(reg) ?
The size of the specific ADC register is stored in the size variable.
The result of sizeof(reg) can be different on different machines and will
probably not be equal to the size of the register in the ADC chip.
> ...
>
> > +static bool ad4170_setup_eq(struct ad4170_setup *a, struct ad4170_setup *b)
> > +{
> > + /*
> > + * The use of static_assert() here is to make sure that, if
> > + * struct ad4170_setup is ever changed (e.g. a field is added to the
> > + * struct's declaration), the comparison below is adapted to keep
> > + * comparing each of struct ad4170_setup fields.
> > + */
>
> Okay. But this also will trigger the case when the field just changes the type.
> So, it also brings false positives. I really think this is wrong place to put
> static_assert(). To me it looks like a solving rare problem, if any.
I think it is unlikely that struct ad4170_setup declaration will ever change.
The fields match the registers that are associated with a channel setup and
the their types match the size of the respective registers. So, I do agree
that triggering this assert would be something rare.
>
> But I leave this to the IIO maintainers.
>
> In my opinion static_assert() makes only sense when memcmp() is being used.
> Otherwise it has prons and cons.
I think the most relevant reason to have this static_assert would be to keep
some consistency with ad4130, ad7124, and ad7173, but no strong opinion about it.
Actually, I don't get why static_assert() would only matter if memcmp() was
being used. Would it be better to not bother if the fields change type?
Anyway, I'll go with whatever be IIO maintainer's preference.
>
> > + static_assert(sizeof(*a) ==
> > + sizeof(struct {
> > + u16 misc;
> > + u16 afe;
> > + u16 filter;
> > + u16 filter_fs;
> > + u32 offset;
> > + u32 gain;
> > + }));
> > +
> > + if (a->misc != b->misc ||
> > + a->afe != b->afe ||
> > + a->filter != b->filter ||
> > + a->filter_fs != b->filter_fs ||
> > + a->offset != b->offset ||
> > + a->gain != b->gain)
> > + return false;
> > +
> > + return true;
> > +}
>
> ...
>
> > + /*
> > + * Some configurations can lead to invalid setups.
> > + * For example, if AVSS = -2.5V, REF_SELECT set to REFOUT (REFOUT/AVSS),
> > + * and pseudo-diff channel configuration set, then the input range
> > + * should go from 0V to +VREF (single-ended - datasheet pg 10), but
> > + * REFOUT/AVSS range would be -2.5V to 0V.
> > + * Check the positive reference is higher than 0V for pseudo-diff
> > + * channels.
> > + */
>
> Right, the Q is, can refp contain an error code here, rather than negative
> value? The code above hints that in some case it may, but are all those cases
> were caught up already? (Comment can be extended to explain this)
I don't think refp can contain an error code at this point. All regulators are
read at ad4170_regulator_setup(). After that setup,
st->vrefs_uv[AD4170_<SUPPLY>] will either contain the voltage read from the
regulator framework (which is >= 0) or -ENODEV. Then, we check the supply value
at the beginning of ad4170_get_input_range() (this function) and error out if
the value is -ENODEV. Will extend the comment to explain that.
>
> > + if (refp <= 0)
> > + return dev_err_probe(dev, -EINVAL,
> > + "REF+ <= GND for pseudo-diff chan %u\n",
> > + ch_reg);
>
...
>
> > + /* Assume AVSS at GND (0V) if not provided */
> > + st->vrefs_uv[AD4170_AVSS_SUP] = ret == -ENODEV ? 0 : -ret;
>
> -ret ?!?!
That's because AVSS is never above system ground level (i.e. AVSS is either GND
or a negative voltage). But we currently don't have support for reading negative
voltages with the regulator framework. So, the current AD4170 support reads
a positive value from the regulator, then inverts signal to make it negative :)
>
> Even if you know that *now* it can't have any other error code, it's quite
> fragile.
Yeah, I guess ADCs that can take bipolar power supplies are not that common.
I couldn't think of any better way to have that, though.
Thanks,
Marcelo
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v5 02/11] iio: adc: Add basic support for AD4170
2025-06-11 21:04 ` Marcelo Schmitt
@ 2025-06-12 12:48 ` Andy Shevchenko
2025-06-12 14:03 ` Marcelo Schmitt
2025-06-14 10:52 ` Jonathan Cameron
0 siblings, 2 replies; 35+ messages in thread
From: Andy Shevchenko @ 2025-06-12 12:48 UTC (permalink / raw)
To: Marcelo Schmitt
Cc: Marcelo Schmitt, linux-iio, devicetree, linux-gpio, linux-kernel,
Ana-Maria Cusco, jic23, lars, Michael.Hennerich, dlechner,
nuno.sa, robh, krzk+dt, conor+dt, linus.walleij, brgl
On Wed, Jun 11, 2025 at 06:04:49PM -0300, Marcelo Schmitt wrote:
> On 06/11, Andy Shevchenko wrote:
> > On Tue, Jun 10, 2025 at 05:31:25PM -0300, Marcelo Schmitt wrote:
...
> > > + return spi_write(st->spi, st->tx_buf, size + 2);
> >
> > ... + sizeof(reg) ?
>
> The size of the specific ADC register is stored in the size variable.
> The result of sizeof(reg) can be different on different machines and will
> probably not be equal to the size of the register in the ADC chip.
Hmm... But shouldn't we have a variable type that respects the sizeof() of the
register in HW to keep it there? 2 is magic.
...
> > > +static bool ad4170_setup_eq(struct ad4170_setup *a, struct ad4170_setup *b)
> > > +{
> > > + /*
> > > + * The use of static_assert() here is to make sure that, if
> > > + * struct ad4170_setup is ever changed (e.g. a field is added to the
> > > + * struct's declaration), the comparison below is adapted to keep
> > > + * comparing each of struct ad4170_setup fields.
> > > + */
> >
> > Okay. But this also will trigger the case when the field just changes the type.
> > So, it also brings false positives. I really think this is wrong place to put
> > static_assert(). To me it looks like a solving rare problem, if any.
>
> I think it is unlikely that struct ad4170_setup declaration will ever change.
> The fields match the registers that are associated with a channel setup and
> the their types match the size of the respective registers. So, I do agree
> that triggering this assert would be something rare.
Yep, which thinks to me as an unneeded noise in the code, making it harder to
read and maintain (in _this_ case).
> > But I leave this to the IIO maintainers.
> >
> > In my opinion static_assert() makes only sense when memcmp() is being used.
> > Otherwise it has prons and cons.
>
> I think the most relevant reason to have this static_assert would be to keep
> some consistency with ad4130, ad7124, and ad7173, but no strong opinion about it.
I would argue that those needs to be revisited for the same reasons as above.
> Actually, I don't get why static_assert() would only matter if memcmp() was
> being used. Would it be better to not bother if the fields change type?
>
> Anyway, I'll go with whatever be IIO maintainer's preference.
> > > + static_assert(sizeof(*a) ==
> > > + sizeof(struct {
> > > + u16 misc;
> > > + u16 afe;
> > > + u16 filter;
> > > + u16 filter_fs;
> > > + u32 offset;
> > > + u32 gain;
> > > + }));
> > > +
> > > + if (a->misc != b->misc ||
> > > + a->afe != b->afe ||
> > > + a->filter != b->filter ||
> > > + a->filter_fs != b->filter_fs ||
> > > + a->offset != b->offset ||
> > > + a->gain != b->gain)
> > > + return false;
> > > +
> > > + return true;
> > > +}
...
> > > + /* Assume AVSS at GND (0V) if not provided */
> > > + st->vrefs_uv[AD4170_AVSS_SUP] = ret == -ENODEV ? 0 : -ret;
> >
> > -ret ?!?!
>
> That's because AVSS is never above system ground level (i.e. AVSS is either GND
> or a negative voltage). But we currently don't have support for reading negative
> voltages with the regulator framework. So, the current AD4170 support reads
> a positive value from the regulator, then inverts signal to make it negative :)
This needs a good comment and ideally a TODO item in the regulator framework.
(It might be easy to implement by adding a flag without changing the type of
the field, if it's unsigned.)
> > Even if you know that *now* it can't have any other error code, it's quite
> > fragile.
>
> Yeah, I guess ADCs that can take bipolar power supplies are not that common.
> I couldn't think of any better way to have that, though.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v5 02/11] iio: adc: Add basic support for AD4170
2025-06-12 12:48 ` Andy Shevchenko
@ 2025-06-12 14:03 ` Marcelo Schmitt
2025-06-12 18:48 ` Andy Shevchenko
2025-06-14 10:52 ` Jonathan Cameron
1 sibling, 1 reply; 35+ messages in thread
From: Marcelo Schmitt @ 2025-06-12 14:03 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Marcelo Schmitt, linux-iio, devicetree, linux-gpio, linux-kernel,
Ana-Maria Cusco, jic23, lars, Michael.Hennerich, dlechner,
nuno.sa, robh, krzk+dt, conor+dt, linus.walleij, brgl
On 06/12, Andy Shevchenko wrote:
> On Wed, Jun 11, 2025 at 06:04:49PM -0300, Marcelo Schmitt wrote:
> > On 06/11, Andy Shevchenko wrote:
> > > On Tue, Jun 10, 2025 at 05:31:25PM -0300, Marcelo Schmitt wrote:
>
> ...
>
> > > > + return spi_write(st->spi, st->tx_buf, size + 2);
> > >
> > > ... + sizeof(reg) ?
> >
> > The size of the specific ADC register is stored in the size variable.
> > The result of sizeof(reg) can be different on different machines and will
> > probably not be equal to the size of the register in the ADC chip.
>
> Hmm... But shouldn't we have a variable type that respects the sizeof() of the
> register in HW to keep it there? 2 is magic.
>
I'll add a define for that constant.
For clarification, there is a 2 byte instruction phase during which the driver
sends the R/W flag and register address. After that, it sends the data to be
written to the register. There are 1 byte, 2 byte, and 3 byte long registers.
So, the total transfer length is 2 + reg size.
...
>
> > > > + /* Assume AVSS at GND (0V) if not provided */
> > > > + st->vrefs_uv[AD4170_AVSS_SUP] = ret == -ENODEV ? 0 : -ret;
> > >
> > > -ret ?!?!
> >
> > That's because AVSS is never above system ground level (i.e. AVSS is either GND
> > or a negative voltage). But we currently don't have support for reading negative
> > voltages with the regulator framework. So, the current AD4170 support reads
> > a positive value from the regulator, then inverts signal to make it negative :)
>
> This needs a good comment and ideally a TODO item in the regulator framework.
> (It might be easy to implement by adding a flag without changing the type of
> the field, if it's unsigned.)
I'll add a TODO mark and expand the comment in the driver.
Not sure about sending a patch only adding a TODO to the regulator framework.
Aren't developers expected to propose things?
I'm anticipating 'talk is cheap, show me the code' coming.
Thanks,
Marcelo
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v5 02/11] iio: adc: Add basic support for AD4170
2025-06-12 14:03 ` Marcelo Schmitt
@ 2025-06-12 18:48 ` Andy Shevchenko
2025-06-14 10:51 ` Jonathan Cameron
0 siblings, 1 reply; 35+ messages in thread
From: Andy Shevchenko @ 2025-06-12 18:48 UTC (permalink / raw)
To: Marcelo Schmitt
Cc: Marcelo Schmitt, linux-iio, devicetree, linux-gpio, linux-kernel,
Ana-Maria Cusco, jic23, lars, Michael.Hennerich, dlechner,
nuno.sa, robh, krzk+dt, conor+dt, linus.walleij, brgl
On Thu, Jun 12, 2025 at 11:03:01AM -0300, Marcelo Schmitt wrote:
> On 06/12, Andy Shevchenko wrote:
> > On Wed, Jun 11, 2025 at 06:04:49PM -0300, Marcelo Schmitt wrote:
> > > On 06/11, Andy Shevchenko wrote:
> > > > On Tue, Jun 10, 2025 at 05:31:25PM -0300, Marcelo Schmitt wrote:
...
> Not sure about sending a patch only adding a TODO to the regulator framework.
> Aren't developers expected to propose things?
> I'm anticipating 'talk is cheap, show me the code' coming.
This maybe done in a form of the discussion started with the maintainers and
stakeholders of regulator framework. It doesn't mean we must have something
in the form of the patch right now.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v5 02/11] iio: adc: Add basic support for AD4170
2025-06-12 18:48 ` Andy Shevchenko
@ 2025-06-14 10:51 ` Jonathan Cameron
0 siblings, 0 replies; 35+ messages in thread
From: Jonathan Cameron @ 2025-06-14 10:51 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Marcelo Schmitt, Marcelo Schmitt, linux-iio, devicetree,
linux-gpio, linux-kernel, Ana-Maria Cusco, lars,
Michael.Hennerich, dlechner, nuno.sa, robh, krzk+dt, conor+dt,
linus.walleij, brgl
On Thu, 12 Jun 2025 21:48:27 +0300
Andy Shevchenko <andriy.shevchenko@linux.intel.com> wrote:
> On Thu, Jun 12, 2025 at 11:03:01AM -0300, Marcelo Schmitt wrote:
> > On 06/12, Andy Shevchenko wrote:
> > > On Wed, Jun 11, 2025 at 06:04:49PM -0300, Marcelo Schmitt wrote:
> > > > On 06/11, Andy Shevchenko wrote:
> > > > > On Tue, Jun 10, 2025 at 05:31:25PM -0300, Marcelo Schmitt wrote:
>
> ...
>
> > Not sure about sending a patch only adding a TODO to the regulator framework.
> > Aren't developers expected to propose things?
> > I'm anticipating 'talk is cheap, show me the code' coming.
>
> This maybe done in a form of the discussion started with the maintainers and
> stakeholders of regulator framework. It doesn't mean we must have something
> in the form of the patch right now.
>
Been quite a few years since we last looked at negative regulator voltages.
Might be worth a revisit.
J
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v5 02/11] iio: adc: Add basic support for AD4170
2025-06-12 12:48 ` Andy Shevchenko
2025-06-12 14:03 ` Marcelo Schmitt
@ 2025-06-14 10:52 ` Jonathan Cameron
1 sibling, 0 replies; 35+ messages in thread
From: Jonathan Cameron @ 2025-06-14 10:52 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Marcelo Schmitt, Marcelo Schmitt, linux-iio, devicetree,
linux-gpio, linux-kernel, Ana-Maria Cusco, lars,
Michael.Hennerich, dlechner, nuno.sa, robh, krzk+dt, conor+dt,
linus.walleij, brgl
On Thu, 12 Jun 2025 15:48:02 +0300
Andy Shevchenko <andriy.shevchenko@linux.intel.com> wrote:
> On Wed, Jun 11, 2025 at 06:04:49PM -0300, Marcelo Schmitt wrote:
> > On 06/11, Andy Shevchenko wrote:
> > > On Tue, Jun 10, 2025 at 05:31:25PM -0300, Marcelo Schmitt wrote:
>
> ...
>
> > > > + return spi_write(st->spi, st->tx_buf, size + 2);
> > >
> > > ... + sizeof(reg) ?
> >
> > The size of the specific ADC register is stored in the size variable.
> > The result of sizeof(reg) can be different on different machines and will
> > probably not be equal to the size of the register in the ADC chip.
>
> Hmm... But shouldn't we have a variable type that respects the sizeof() of the
> register in HW to keep it there? 2 is magic.
>
> ...
>
> > > > +static bool ad4170_setup_eq(struct ad4170_setup *a, struct ad4170_setup *b)
> > > > +{
> > > > + /*
> > > > + * The use of static_assert() here is to make sure that, if
> > > > + * struct ad4170_setup is ever changed (e.g. a field is added to the
> > > > + * struct's declaration), the comparison below is adapted to keep
> > > > + * comparing each of struct ad4170_setup fields.
> > > > + */
> > >
> > > Okay. But this also will trigger the case when the field just changes the type.
> > > So, it also brings false positives. I really think this is wrong place to put
> > > static_assert(). To me it looks like a solving rare problem, if any.
> >
> > I think it is unlikely that struct ad4170_setup declaration will ever change.
> > The fields match the registers that are associated with a channel setup and
> > the their types match the size of the respective registers. So, I do agree
> > that triggering this assert would be something rare.
>
> Yep, which thinks to me as an unneeded noise in the code, making it harder to
> read and maintain (in _this_ case).
This whole thing with static asserts was a compromise in the original drivers.
I'm fine with just dropping it (here at least) and relying on review to pick up
changes to these structures.
Jonathan
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v5 00/11] iio: adc: Add support for AD4170 series of ADCs
2025-06-10 20:30 [PATCH v5 00/11] iio: adc: Add support for AD4170 series of ADCs Marcelo Schmitt
` (10 preceding siblings ...)
2025-06-10 20:34 ` [PATCH v5 11/11] iio: adc: ad4170: Add timestamp channel Marcelo Schmitt
@ 2025-06-14 11:04 ` Jonathan Cameron
11 siblings, 0 replies; 35+ messages in thread
From: Jonathan Cameron @ 2025-06-14 11:04 UTC (permalink / raw)
To: Marcelo Schmitt
Cc: linux-iio, devicetree, linux-gpio, linux-kernel, lars,
Michael.Hennerich, dlechner, nuno.sa, andy, robh, krzk+dt,
conor+dt, linus.walleij, brgl, marcelo.schmitt1
On Tue, 10 Jun 2025 17:30:40 -0300
Marcelo Schmitt <marcelo.schmitt@analog.com> wrote:
> Hello,
>
> This is version 5 of AD4170 support patch set.
> Not many changes from v4 to v5 and not waiting as long between the previous and
> this new version so, keeping both change logs below.
>
> Thank you to all reviewers.
>
> This patch set adds support for Analog Devices AD4170 and similar sigma-delta ADCs.
>
> Patch 1 adds device tree documentation for the parts.
> Patch 2 adds basic device support.
> Patch 3 adds support for calibration scale.
> Patch 4 adds support for calibration bias.
> Patch 5 adds support for sample frequency along with filter type configuration.
> Patch 6 adds support for buffered ADC reading.
> Patch 7 adds clock provider support
> Patch 8 adds GPIO controller support.
> Patch 9 adds internal temperature sensor support.
> Patch 10 adds support for external RTD and bridge circuit sensors.
> Patch 11 adds timestamp channel
>
I took a look at this version and FWIW I don't have any comments to add
to Andy's review. So we should be good to go on v6.
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v5 01/11] dt-bindings: iio: adc: Add AD4170
2025-06-10 20:31 ` [PATCH v5 01/11] dt-bindings: iio: adc: Add AD4170 Marcelo Schmitt
@ 2025-06-16 15:41 ` Conor Dooley
2025-06-16 17:58 ` Marcelo Schmitt
` (2 more replies)
0 siblings, 3 replies; 35+ messages in thread
From: Conor Dooley @ 2025-06-16 15:41 UTC (permalink / raw)
To: Marcelo Schmitt
Cc: linux-iio, devicetree, linux-gpio, linux-kernel, jic23, lars,
Michael.Hennerich, dlechner, nuno.sa, andy, robh, krzk+dt,
conor+dt, linus.walleij, brgl, marcelo.schmitt1
[-- Attachment #1: Type: text/plain, Size: 24158 bytes --]
On Tue, Jun 10, 2025 at 05:31:04PM -0300, Marcelo Schmitt wrote:
> Add device tree documentation for AD4170 and similar sigma-delta ADCs.
> The AD4170 is a 24-bit, multichannel, sigma-delta ADC.
>
> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
> ---
> Change log v4 -> v5
> - Dropped interrupt maxItems constraint.
> - Spelled out RC acronym in reference-buffer description.
> - Require to specify interrupt-names when using interrupts.
> - Added interrupt-names to the examples.
> - Made adi,excitation-pin properties identical to adi,ad4130.
> - Removed interrupt-parent props from the examples.
>
> Proposing new types and ways of describing hardware for weigh scale load cells
> and related sensors external to ADCs can lead to potential better description of
> how those components connect to the ADC. However, we must use what already
> exists for properties documenting features that are the same across different
> devices.
>
> Maybe, we could use generic defs to define adi,excitation-current-n-microamp and
> adi,excitation-pin and avoid repetition with those. Though, that triggers a
> dt_binding_check warning. Also, having mixed notation (some prop declarations
> using defines and others not) seems to not be desirable.
>
> It looks like the only option left is making adi,excitation-pin properties
> identical to adi,ad4130.
>
> On one hand, dropping adi,excitation-pin defs and making those properties
> identical to adi,ad4130 preserves their syntax and semantics accross
> dt-bindings. OTOH, we end up with more text repetition in the doc.
>
>
> .../bindings/iio/adc/adi,ad4170.yaml | 564 ++++++++++++++++++
> MAINTAINERS | 7 +
> 2 files changed, 571 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml
> new file mode 100644
> index 000000000000..e3249ec56a14
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml
> @@ -0,0 +1,564 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iio/adc/adi,ad4170.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Analog Devices AD4170 and similar Analog to Digital Converters
> +
> +maintainers:
> + - Marcelo Schmitt <marcelo.schmitt@analog.com>
> +
> +description: |
> + Analog Devices AD4170 series of Sigma-delta Analog to Digital Converters.
> + Specifications can be found at:
> + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4170-4.pdf
> + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4190-4.pdf
> + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4195-4.pdf
> +
> +$ref: /schemas/spi/spi-peripheral-props.yaml#
> +
> +$defs:
> + reference-buffer:
> + description: |
> + Enable precharge buffer, full buffer, or skip reference buffering of
> + the positive/negative voltage reference. Because the output impedance
> + of the source driving the voltage reference inputs may be dynamic,
> + resistive/capacitive combinations of those inputs can cause DC gain
> + errors if the reference inputs go unbuffered into the ADC. Enable
> + reference buffering if the provided reference source has dynamic high
> + impedance output. Note the absolute voltage allowed on REFINn+ and REFINn-
> + inputs is from AVSS - 50 mV to AVDD + 50 mV when the reference buffers are
> + disabled but narrows to AVSS to AVDD when reference buffering is enabled
> + or in precharge mode. The valid options for this property are:
> + 0: Reference precharge buffer.
> + 1: Full reference buffering.
> + 2: Bypass reference buffers (buffering disabled).
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1, 2]
> + default: 1
Why make this property a uint32, rather than a string where you can use
something like "precharge", "full" and "bypass" (or "disabled")? The
next similar device could use something slightly different then the
binding becomes pretty clunky.
Can you explain why this is a dt property rather than something
adjustable at runtime?
Otherwise, what you have here looks sane enough to me - but I'd like to
see some comments from Jonathan or David etc about your approach to the
excitation properties.
Cheers,
Conor.
> +
> +properties:
> + compatible:
> + enum:
> + - adi,ad4170
> + - adi,ad4190
> + - adi,ad4195
> +
> + avss-supply:
> + description:
> + Reference voltage supply for AVSS. If provided, describes the magnitude
> + (absolute value) of the negative voltage supplied to the AVSS pin. Since
> + AVSS must be −2.625V minimum and 0V maximum, the declared supply voltage
> + must be between 0 and 2.65V. If not provided, AVSS is assumed to be at
> + system ground (0V).
> +
> + avdd-supply:
> + description:
> + A supply of 4.75V to 5.25V relative to AVSS that powers the chip (AVDD).
> +
> + iovdd-supply:
> + description: 1.7V to 5.25V reference supply to the serial interface (IOVDD).
> +
> + refin1p-supply:
> + description: REFIN+ supply that can be used as reference for conversion.
> +
> + refin1n-supply:
> + description: REFIN- supply that can be used as reference for conversion. If
> + provided, describes the magnitude (absolute value) of the negative voltage
> + supplied to the REFIN- pin.
> +
> + refin2p-supply:
> + description: REFIN2+ supply that can be used as reference for conversion.
> +
> + refin2n-supply:
> + description: REFIN2- supply that can be used as reference for conversion. If
> + provided, describes the magnitude (absolute value) of the negative voltage
> + supplied to the REFIN2- pin.
> +
> + spi-cpol: true
> +
> + spi-cpha: true
> +
> + interrupts:
> + description:
> + Interrupt for signaling the completion of conversion results. The data
> + ready signal (RDY) used as interrupt is by default provided on the SDO
> + pin. Alternatively, it can be provided on the DIG_AUX1 pin in which case
> + the chip disables the RDY function on SDO. Thus, there can be only one
> + data ready interrupt enabled at a time.
> +
> + interrupt-names:
> + description:
> + Specify which pin should be configured as Data Ready interrupt.
> + enum:
> + - sdo
> + - dig_aux1
> +
> + clocks:
> + maxItems: 1
> + description:
> + Optional external clock source. Can specify either an external clock or
> + external crystal.
> +
> + clock-names:
> + enum:
> + - ext-clk
> + - xtal
> + default: ext-clk
> +
> + '#clock-cells':
> + const: 0
> +
> + clock-output-names:
> + maxItems: 1
> +
> + gpio-controller: true
> +
> + "#gpio-cells":
> + const: 2
> + description: |
> + The first cell is for the GPIO number: 0 to 3.
> + The second cell takes standard GPIO flags.
> +
> + ldac-gpios:
> + description:
> + GPIO connected to DIG_AUX2 pin to be used as LDAC toggle to control the
> + transfer of data from the DAC_INPUT_A register to the DAC.
> + maxItems: 1
> +
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 0
> +
> + adi,vbias-pins:
> + description: Analog inputs to apply a voltage bias of (AVDD − AVSS) / 2 to.
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + minItems: 1
> + maxItems: 9
> + items:
> + minimum: 0
> + maximum: 8
> +
> +allOf:
> + # Some devices don't have integrated DAC
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - adi,ad4190
> + - adi,ad4195
> + then:
> + properties:
> + ldac-gpios: false
> +
> + # Require to specify the interrupt pin when using interrupts
> + - if:
> + required:
> + - interrupts
> + then:
> + required:
> + - interrupt-names
> +
> + # If an external clock is set, the internal clock cannot go out and vice versa
> + - oneOf:
> + - required: [clocks]
> + properties:
> + '#clock-cells': false
> + - required: ['#clock-cells']
> + properties:
> + clocks: false
> +
> +patternProperties:
> + "^channel@[0-9a-f]$":
> + $ref: /schemas/iio/adc/adc.yaml#
> + unevaluatedProperties: false
> + description:
> + Represents the external channels which are connected to the ADC.
> +
> + properties:
> + reg:
> + description:
> + The channel number.
> + minimum: 0
> + maximum: 15
> +
> + diff-channels:
> + description: |
> + This property is used for defining the inputs of a differential
> + voltage channel. The first value is the positive input and the second
> + value is the negative input of the channel.
> +
> + Besides the analog input pins AIN0 to AIN8, there are special inputs
> + that can be selected with the following values:
> + 17: Internal temperature sensor
> + 18: (AVDD-AVSS)/5
> + 19: (IOVDD-DGND)/5
> + 20: DAC output
> + 21: ALDO
> + 22: DLDO
> + 23: AVSS
> + 24: DGND
> + 25: REFIN+
> + 26: REFIN-
> + 27: REFIN2+
> + 28: REFIN2-
> + 29: REFOUT
> + For the internal temperature sensor, use the input number for both
> + inputs (i.e. diff-channels = <17 17>).
> + items:
> + enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 17, 18, 19, 20, 21, 22, 23, 24, 25,
> + 26, 27, 28, 29]
> +
> + adi,reference-select:
> + description: |
> + Select the reference source to use when converting on the
> + specific channel. Valid values are:
> + 0: REFIN+/REFIN-
> + 1: REFIN2+/REFIN2−
> + 2: REFOUT/AVSS (internal reference)
> + 3: AVDD/AVSS
> + If not specified, REFOUT/AVSS is used.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1, 2, 3]
> + default: 1
> +
> + adi,positive-reference-buffer:
> + $ref: '#/$defs/reference-buffer'
> +
> + adi,negative-reference-buffer:
> + $ref: '#/$defs/reference-buffer'
> +
> + adi,sensor-type:
> + description:
> + The AD4170 and similar designs have features to aid interfacing with
> + load cell weigh scale, RTD, and thermocouple sensors. Each of those
> + sensor types requires either distinct wiring configuration or
> + external circuitry for proper sensor operation and can use different
> + ADC chip functionality on their setups. A key characteristic of those
> + external sensors is that they must be excited either by voltage supply
> + or by ADC chip excitation signals. The sensor can then be read through
> + a pair of analog inputs. This property specifies which particular
> + sensor type is connected to the ADC so it can be properly setup and
> + handled. Omit this property for conventional (not weigh scale, RTD, or
> + thermocouple) ADC channel setups.
> + $ref: /schemas/types.yaml#/definitions/string
> + enum: [ weighscale, rtd, thermocouple ]
> +
> + adi,excitation-pin-0:
> + description:
> + Analog input to apply excitation current to while the channel
> + is active.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 20
> + default: 0
> +
> + adi,excitation-pin-1:
> + description:
> + Analog input to apply excitation current to while the channel
> + is active.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 20
> + default: 0
> +
> + adi,excitation-pin-2:
> + description:
> + Analog input to apply excitation current to while the channel
> + is active.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 20
> + default: 0
> +
> + adi,excitation-pin-3:
> + description:
> + Analog input to apply excitation current to while the channel
> + is active.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 20
> + default: 0
> +
> + adi,excitation-current-0-microamp:
> + description:
> + Excitation current in microamperes to be applied to pin specified in
> + adi,excitation-pin-0 while this channel is active.
> + enum: [0, 10, 50, 100, 250, 500, 1000, 1500]
> + default: 0
> +
> + adi,excitation-current-1-microamp:
> + description:
> + Excitation current in microamperes to be applied to pin specified in
> + adi,excitation-pin-1 while this channel is active.
> + enum: [0, 10, 50, 100, 250, 500, 1000, 1500]
> + default: 0
> +
> + adi,excitation-current-2-microamp:
> + description:
> + Excitation current in microamperes to be applied to pin specified in
> + adi,excitation-pin-2 while this channel is active.
> + enum: [0, 10, 50, 100, 250, 500, 1000, 1500]
> + default: 0
> +
> + adi,excitation-current-3-microamp:
> + description:
> + Excitation current in microamperes to be applied to pin specified in
> + adi,excitation-pin-3 while this channel is active.
> + enum: [0, 10, 50, 100, 250, 500, 1000, 1500]
> + default: 0
> +
> + adi,excitation-ac:
> + type: boolean
> + description:
> + Whether the external sensor has to be AC or DC excited. When omitted,
> + it is DC excited.
> +
> + allOf:
> + - oneOf:
> + - required: [single-channel, common-mode-channel]
> + properties:
> + diff-channels: false
> + - required: [diff-channels]
> + properties:
> + single-channel: false
> + common-mode-channel: false
> + # Usual ADC channels don't need external circuitry excitation.
> + - if:
> + not:
> + required:
> + - adi,sensor-type
> + then:
> + properties:
> + adi,excitation-pin-0: false
> + adi,excitation-pin-1: false
> + adi,excitation-pin-2: false
> + adi,excitation-pin-3: false
> + adi,excitation-current-0-microamp: false
> + adi,excitation-current-1-microamp: false
> + adi,excitation-current-2-microamp: false
> + adi,excitation-current-3-microamp: false
> + adi,excitation-ac: false
> + # Weigh scale bridge AC excited with one pair of predefined signals.
> + - if:
> + allOf:
> + - properties:
> + adi,sensor-type:
> + contains:
> + const: weighscale
> + - required:
> + - adi,excitation-ac
> + - adi,excitation-pin-2
> + - adi,excitation-pin-3
> + - not:
> + required:
> + - adi,excitation-current-2-microamp
> + - adi,excitation-current-3-microamp
> + then:
> + properties:
> + adi,excitation-pin-2:
> + const: 19
> + adi,excitation-pin-3:
> + const: 20
> + # Weigh scale bridge AC excited with two pairs of predefined signals.
> + - if:
> + allOf:
> + - properties:
> + adi,sensor-type:
> + contains:
> + const: weighscale
> + - required:
> + - adi,excitation-ac
> + - adi,excitation-pin-0
> + - adi,excitation-pin-1
> + - adi,excitation-pin-2
> + - adi,excitation-pin-3
> + - not:
> + required:
> + - adi,excitation-current-0-microamp
> + - adi,excitation-current-1-microamp
> + - adi,excitation-current-2-microamp
> + - adi,excitation-current-3-microamp
> + then:
> + properties:
> + adi,excitation-pin-0:
> + const: 17
> + adi,excitation-pin-1:
> + const: 18
> + adi,excitation-pin-2:
> + const: 19
> + adi,excitation-pin-3:
> + const: 20
> +
> +required:
> + - compatible
> + - reg
> + - avdd-supply
> + - iovdd-supply
> + - spi-cpol
> + - spi-cpha
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + spi {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + adc@0 {
> + compatible = "adi,ad4170";
> + reg = <0>;
> + spi-max-frequency = <20000000>;
> + spi-cpol;
> + spi-cpha;
> + avdd-supply = <&avdd>;
> + iovdd-supply = <&iovdd>;
> + clocks = <&clk>;
> + clock-names = "xtal";
> + interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
> + interrupt-names = "dig_aux1";
> + adi,vbias-pins = <7>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + // Sample AIN0 with respect to DGND throughout AVDD/DGND input range
> + // Pseudo-differential unipolar
> + channel@0 {
> + reg = <0>;
> + single-channel = <0>;
> + common-mode-channel = <24>;
> + adi,reference-select = <3>;
> + };
> + // Weigh scale sensor
> + channel@1 {
> + reg = <1>;
> + bipolar;
> + diff-channels = <1 2>;
> + adi,reference-select = <0>;
> + adi,positive-reference-buffer = <0>;
> + adi,negative-reference-buffer = <0>;
> + adi,sensor-type = "weighscale";
> + adi,excitation-pin-2 = <19>;
> + adi,excitation-pin-3 = <20>;
> + adi,excitation-ac;
> + };
> + // RTD sensor
> + channel@2 {
> + reg = <2>;
> + bipolar;
> + diff-channels = <3 4>;
> + adi,reference-select = <0>;
> + adi,sensor-type = "rtd";
> + adi,excitation-pin-0 = <5>;
> + adi,excitation-pin-1 = <6>;
> + adi,excitation-current-0-microamp = <500>;
> + adi,excitation-current-1-microamp = <500>;
> + adi,excitation-ac;
> + };
> + // Thermocouple sensor
> + channel@3 {
> + reg = <3>;
> + bipolar;
> + diff-channels = <7 8>;
> + adi,reference-select = <0>;
> + adi,sensor-type = "thermocouple";
> + adi,excitation-pin-0 = <18>;
> + adi,excitation-current-0-microamp = <500>;
> + };
> + };
> + };
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + spi {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + adc@0 {
> + compatible = "adi,ad4170";
> + reg = <0>;
> + spi-max-frequency = <20000000>;
> + spi-cpol;
> + spi-cpha;
> + avdd-supply = <&avdd>;
> + iovdd-supply = <&iovdd>;
> + #clock-cells = <0>;
> + clock-output-names = "ad4170-clk16mhz";
> + interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
> + interrupt-names = "dig_aux1";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + // Sample AIN0 with respect to AIN1 throughout AVDD/AVSS input range
> + // Differential bipolar. If AVSS < 0V, differential true bipolar
> + channel@0 {
> + reg = <0>;
> + bipolar;
> + diff-channels = <0 1>;
> + adi,reference-select = <3>;
> + };
> + // Sample AIN2 with respect to DGND throughout AVDD/DGND input range
> + // Pseudo-differential unipolar
> + channel@1 {
> + reg = <1>;
> + single-channel = <2>;
> + common-mode-channel = <24>;
> + adi,reference-select = <3>;
> + };
> + // Sample AIN3 with respect to 2.5V throughout AVDD/AVSS input range
> + // Pseudo-differential bipolar
> + channel@2 {
> + reg = <2>;
> + bipolar;
> + single-channel = <3>;
> + common-mode-channel = <29>;
> + adi,reference-select = <3>;
> + };
> + // Sample AIN4 with respect to DGND throughout AVDD/AVSS input range
> + // Pseudo-differential bipolar
> + channel@3 {
> + reg = <3>;
> + bipolar;
> + single-channel = <4>;
> + common-mode-channel = <24>;
> + adi,reference-select = <3>;
> + };
> + // Sample AIN5 with respect to 2.5V throughout AVDD/AVSS input range
> + // Pseudo-differential unipolar (AD4170 datasheet page 46 example)
> + channel@4 {
> + reg = <4>;
> + single-channel = <5>;
> + common-mode-channel = <29>;
> + adi,reference-select = <3>;
> + };
> + // Sample AIN6 with respect to 2.5V throughout REFIN+/REFIN- input range
> + // Pseudo-differential bipolar
> + channel@5 {
> + reg = <5>;
> + bipolar;
> + single-channel = <6>;
> + common-mode-channel = <29>;
> + adi,reference-select = <0>;
> + };
> + // Weigh scale sensor
> + channel@6 {
> + reg = <6>;
> + bipolar;
> + diff-channels = <7 8>;
> + adi,reference-select = <0>;
> + adi,sensor-type = "weighscale";
> + adi,excitation-pin-0 = <17>;
> + adi,excitation-pin-1 = <18>;
> + adi,excitation-pin-2 = <19>;
> + adi,excitation-pin-3 = <20>;
> + adi,excitation-ac;
> + };
> + };
> + };
> +...
> +
> diff --git a/MAINTAINERS b/MAINTAINERS
> index abfd5ded8735..44735314a43e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1392,6 +1392,13 @@ F: Documentation/ABI/testing/sysfs-bus-iio-adc-ad4130
> F: Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml
> F: drivers/iio/adc/ad4130.c
>
> +ANALOG DEVICES INC AD4170 DRIVER
> +M: Marcelo Schmitt <marcelo.schmitt@analog.com>
> +L: linux-iio@vger.kernel.org
> +S: Supported
> +W: https://ez.analog.com/linux-software-drivers
> +F: Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml
> +
> ANALOG DEVICES INC AD4695 DRIVER
> M: Michael Hennerich <michael.hennerich@analog.com>
> M: Nuno Sá <nuno.sa@analog.com>
> --
> 2.47.2
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v5 01/11] dt-bindings: iio: adc: Add AD4170
2025-06-16 15:41 ` Conor Dooley
@ 2025-06-16 17:58 ` Marcelo Schmitt
2025-06-16 20:41 ` David Lechner
2025-06-21 16:37 ` Jonathan Cameron
2 siblings, 0 replies; 35+ messages in thread
From: Marcelo Schmitt @ 2025-06-16 17:58 UTC (permalink / raw)
To: Conor Dooley
Cc: Marcelo Schmitt, linux-iio, devicetree, linux-gpio, linux-kernel,
jic23, lars, Michael.Hennerich, dlechner, nuno.sa, andy, robh,
krzk+dt, conor+dt, linus.walleij, brgl
On 06/16, Conor Dooley wrote:
> On Tue, Jun 10, 2025 at 05:31:04PM -0300, Marcelo Schmitt wrote:
> > Add device tree documentation for AD4170 and similar sigma-delta ADCs.
> > The AD4170 is a 24-bit, multichannel, sigma-delta ADC.
> >
> > Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
> > ---
...
> > +
> > +$defs:
> > + reference-buffer:
> > + description: |
> > + Enable precharge buffer, full buffer, or skip reference buffering of
> > + the positive/negative voltage reference. Because the output impedance
> > + of the source driving the voltage reference inputs may be dynamic,
> > + resistive/capacitive combinations of those inputs can cause DC gain
> > + errors if the reference inputs go unbuffered into the ADC. Enable
> > + reference buffering if the provided reference source has dynamic high
> > + impedance output. Note the absolute voltage allowed on REFINn+ and REFINn-
> > + inputs is from AVSS - 50 mV to AVDD + 50 mV when the reference buffers are
> > + disabled but narrows to AVSS to AVDD when reference buffering is enabled
> > + or in precharge mode. The valid options for this property are:
> > + 0: Reference precharge buffer.
> > + 1: Full reference buffering.
> > + 2: Bypass reference buffers (buffering disabled).
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + enum: [0, 1, 2]
> > + default: 1
>
> Why make this property a uint32, rather than a string where you can use
> something like "precharge", "full" and "bypass" (or "disabled")? The
> next similar device could use something slightly different then the
> binding becomes pretty clunky.
Oh, good point. Will make it string type (if going to keep the property).
> Can you explain why this is a dt property rather than something
> adjustable at runtime?
The reference buffer configuration affects the allowed absolute maximum input
ratings of voltage reference supplies. Some bindings (adi,ad7192, adi,ad4130,
adi,ad7124) have dt properties for buffering of analog inputs and adi,max11410
has a prop for reference buffering. It looked like adi,ad4170 having a dt prop
for reference buf would make it more consistent with other bindings. Though, I'm
fine with dropping ad4170 reference buffer props if that would be better.
Thanks,
Marcelo
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v5 01/11] dt-bindings: iio: adc: Add AD4170
2025-06-16 15:41 ` Conor Dooley
2025-06-16 17:58 ` Marcelo Schmitt
@ 2025-06-16 20:41 ` David Lechner
2025-06-21 16:28 ` Jonathan Cameron
2025-06-21 16:37 ` Jonathan Cameron
2 siblings, 1 reply; 35+ messages in thread
From: David Lechner @ 2025-06-16 20:41 UTC (permalink / raw)
To: Conor Dooley, Marcelo Schmitt
Cc: linux-iio, devicetree, linux-gpio, linux-kernel, jic23, lars,
Michael.Hennerich, nuno.sa, andy, robh, krzk+dt, conor+dt,
linus.walleij, brgl, marcelo.schmitt1
On 6/16/25 10:41 AM, Conor Dooley wrote:
> On Tue, Jun 10, 2025 at 05:31:04PM -0300, Marcelo Schmitt wrote:
>> Add device tree documentation for AD4170 and similar sigma-delta ADCs.
>> The AD4170 is a 24-bit, multichannel, sigma-delta ADC.
>>
>> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
>> ---
>> Change log v4 -> v5
>> - Dropped interrupt maxItems constraint.
>> - Spelled out RC acronym in reference-buffer description.
>> - Require to specify interrupt-names when using interrupts.
>> - Added interrupt-names to the examples.
>> - Made adi,excitation-pin properties identical to adi,ad4130.
>> - Removed interrupt-parent props from the examples.
>>
>> Proposing new types and ways of describing hardware for weigh scale load cells
>> and related sensors external to ADCs can lead to potential better description of
>> how those components connect to the ADC. However, we must use what already
>> exists for properties documenting features that are the same across different
>> devices.
>>
>> Maybe, we could use generic defs to define adi,excitation-current-n-microamp and
>> adi,excitation-pin and avoid repetition with those. Though, that triggers a
>> dt_binding_check warning. Also, having mixed notation (some prop declarations
>> using defines and others not) seems to not be desirable.
>>
>> It looks like the only option left is making adi,excitation-pin properties
>> identical to adi,ad4130.
>>
>> On one hand, dropping adi,excitation-pin defs and making those properties
>> identical to adi,ad4130 preserves their syntax and semantics accross
>> dt-bindings. OTOH, we end up with more text repetition in the doc.
>>
>>
>> .../bindings/iio/adc/adi,ad4170.yaml | 564 ++++++++++++++++++
>> MAINTAINERS | 7 +
>> 2 files changed, 571 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml
>> new file mode 100644
>> index 000000000000..e3249ec56a14
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml
>> @@ -0,0 +1,564 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/iio/adc/adi,ad4170.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Analog Devices AD4170 and similar Analog to Digital Converters
>> +
>> +maintainers:
>> + - Marcelo Schmitt <marcelo.schmitt@analog.com>
>> +
>> +description: |
>> + Analog Devices AD4170 series of Sigma-delta Analog to Digital Converters.
>> + Specifications can be found at:
>> + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4170-4.pdf
>> + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4190-4.pdf
>> + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4195-4.pdf
>> +
>> +$ref: /schemas/spi/spi-peripheral-props.yaml#
>> +
>> +$defs:
>> + reference-buffer:
>> + description: |
>> + Enable precharge buffer, full buffer, or skip reference buffering of
>> + the positive/negative voltage reference. Because the output impedance
>> + of the source driving the voltage reference inputs may be dynamic,
>> + resistive/capacitive combinations of those inputs can cause DC gain
>> + errors if the reference inputs go unbuffered into the ADC. Enable
>> + reference buffering if the provided reference source has dynamic high
>> + impedance output. Note the absolute voltage allowed on REFINn+ and REFINn-
>> + inputs is from AVSS - 50 mV to AVDD + 50 mV when the reference buffers are
>> + disabled but narrows to AVSS to AVDD when reference buffering is enabled
>> + or in precharge mode. The valid options for this property are:
>> + 0: Reference precharge buffer.
>> + 1: Full reference buffering.
>> + 2: Bypass reference buffers (buffering disabled).
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + enum: [0, 1, 2]
>> + default: 1
>
> Why make this property a uint32, rather than a string where you can use
> something like "precharge", "full" and "bypass" (or "disabled")? The
> next similar device could use something slightly different then the
> binding becomes pretty clunky.
> Can you explain why this is a dt property rather than something
> adjustable at runtime?
>
> Otherwise, what you have here looks sane enough to me - but I'd like to
> see some comments from Jonathan or David etc about your approach to the
> excitation properties.
This looks like something that should be in the devicetree to me. For example
if the external reference supply is high impedance, buffering is pretty
much required. And using precharge is an application design choice to
reduce THD at the expense of other limitations.
>
> Cheers,
> Conor.
>
>> +
>> +properties:
...
>> +allOf:
>> + # Some devices don't have integrated DAC
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - adi,ad4190
>> + - adi,ad4195
>> + then:
>> + properties:
>> + ldac-gpios: false
>> +
>> + # Require to specify the interrupt pin when using interrupts
>> + - if:
>> + required:
>> + - interrupts
>> + then:
>> + required:
>> + - interrupt-names
>> +
>> + # If an external clock is set, the internal clock cannot go out and vice versa
>> + - oneOf:
>> + - required: [clocks]
>> + properties:
>> + '#clock-cells': false
>> + - required: ['#clock-cells']
>> + properties:
>> + clocks: false
>> +
>> +patternProperties:
...
>> +required:
>> + - compatible
>> + - reg
>> + - avdd-supply
>> + - iovdd-supply
>> + - spi-cpol
>> + - spi-cpha
>> +
>> +unevaluatedProperties: false
>> +
It would be more logical to place these before patternProperties (actually
really before allOf) so that they are close to the properties that they are
referencing.
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v5 02/11] iio: adc: Add basic support for AD4170
2025-06-10 20:31 ` [PATCH v5 02/11] iio: adc: Add basic support for AD4170 Marcelo Schmitt
2025-06-10 21:10 ` Andy Shevchenko
@ 2025-06-16 20:41 ` David Lechner
2025-06-17 18:54 ` Marcelo Schmitt
2025-06-18 17:37 ` Dan Carpenter
2 siblings, 1 reply; 35+ messages in thread
From: David Lechner @ 2025-06-16 20:41 UTC (permalink / raw)
To: Marcelo Schmitt, linux-iio, devicetree, linux-gpio, linux-kernel
Cc: Ana-Maria Cusco, jic23, lars, Michael.Hennerich, nuno.sa, andy,
robh, krzk+dt, conor+dt, linus.walleij, brgl, marcelo.schmitt1
On 6/10/25 3:31 PM, Marcelo Schmitt wrote:
> From: Ana-Maria Cusco <ana-maria.cusco@analog.com>
>
> The AD4170 is a multichannel, low noise, 24-bit precision sigma-delta
> analog to digital converter. The AD4170 design offers a flexible data
> acquisition solution with crosspoint multiplexed analog inputs,
> configurable ADC voltage reference inputs, ultra-low noise integrated PGA,
> digital filtering, wide range of configurable output data rates, internal
> oscillator and temperature sensor, four GPIOs, and integrated features for
> interfacing with load cell weigh scales, RTD, and thermocouple sensors.
>
> Add basic support for the AD4170 ADC with the following features:
> - Single-shot read.
> - Analog front end PGA configuration.
> - Differential and pseudo-differential input configuration.
>
...
> +static int ad4170_fill_scale_tbl(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan)
> +{
> + struct ad4170_state *st = iio_priv(indio_dev);
> + struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
> + struct device *dev = &st->spi->dev;
> + int bipolar = chan->scan_type.sign == 's' ? 1 : 0;
> + int precision_bits = chan->scan_type.realbits;
> + int pga, ainm_voltage, ret;
> + unsigned long long offset;
> +
> + ainm_voltage = 0;
> + ret = ad4170_get_ain_voltage_uv(st, chan->channel2, &ainm_voltage);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "Failed to fill scale table\n");
> +
> + for (pga = 0; pga < AD4170_NUM_PGA_OPTIONS; pga++) {
From what I read in the datasheet, it sounds like if adi,reference-buffer is
precharge, then the PGA is bypassed, so there would only be 1 option in that
case (gain = 1).
> + u64 nv;
> + unsigned int lshift, rshift;
> +
> + /*
> + * The PGA options are numbered from 0 to 9, with option 0 being
> + * a gain of 2^0 (no actual gain), and 7 meaning a gain of 2^7.
> + * Option 8, though, sets a gain of 0.5, so the input signal can
> + * be attenuated by 2 rather than amplified. Option 9, allows
> + * the signal to bypass the PGA circuitry (no gain).
> + *
> + * The scale factor to get ADC output codes to values in mV
> + * units is given by:
> + * _scale = (input_range / gain) / 2^precision
> + * AD4170 gain is a power of 2 so the above can be written as
> + * _scale = input_range / 2^(precision + gain)
> + * Keep the input range in µV to avoid truncating the less
> + * significan bits when right shifting it so to preserve scale
> + * precision.
> + */
> + nv = (u64)chan_info->input_range_uv * NANO;
> + lshift = !!(pga & BIT(3)); /* handle options 8 and 9 */
> + rshift = precision_bits - bipolar + (pga & GENMASK(2, 0)) - lshift;
> + chan_info->scale_tbl[pga][0] = 0;
> + chan_info->scale_tbl[pga][1] = div_u64(nv >> rshift, MILLI);
> +
> + /*
> + * If the negative input is not at GND, the conversion result
> + * (which is relative to IN-) will be offset by the level at IN-.
> + * Use the scale factor the other way around to go from a known
> + * voltage to the corresponding ADC output code.
> + * With that, we are able to get to what would be the output
> + * code for the voltage at the negative input.
> + * If the negative input is not fixed, there is no offset.
> + */
> + offset = ((unsigned long long)abs(ainm_voltage)) * MICRO;
> + offset = DIV_ROUND_CLOSEST_ULL(offset, chan_info->scale_tbl[pga][1]);
> +
> + /*
> + * After divided by the scale, offset will always fit into 31
> + * bits. For _raw + _offset to be relative to GND, the value
> + * provided as _offset is of opposite sign than the real offset.
> + */
> + if (ainm_voltage > 0)
> + chan_info->offset_tbl[pga] = -(int)(offset);
> + else
> + chan_info->offset_tbl[pga] = (int)(offset);
> + }
> + return 0;
> +}
> +
> +static int ad4170_read_avail(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan,
> + const int **vals, int *type, int *length,
> + long info)
> +{
> + struct ad4170_state *st = iio_priv(indio_dev);
> + struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
> +
> + switch (info) {
> + case IIO_CHAN_INFO_SCALE:
> + *vals = (int *)chan_info->scale_tbl;
> + *length = ARRAY_SIZE(chan_info->scale_tbl) * 2;
> + *type = IIO_VAL_INT_PLUS_NANO;
> + return IIO_AVAIL_LIST;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static int ad4170_set_pga(struct ad4170_state *st,
> + struct iio_chan_spec const *chan, int val, int val2)
> +{
> + struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
> + struct ad4170_setup *setup = &chan_info->setup;
> + unsigned int pga;
Likewise, here would also need to check for precharge and only allow
gain = 1 in in that case.
> +
> + for (pga = 0; pga < AD4170_NUM_PGA_OPTIONS; pga++) {
> + if (val == chan_info->scale_tbl[pga][0] &&
> + val2 == chan_info->scale_tbl[pga][1])
> + break;
> + }
> +
> + if (pga == AD4170_NUM_PGA_OPTIONS)
> + return -EINVAL;
> +
> + guard(mutex)(&st->lock);
> + setup->afe &= ~AD4170_AFE_PGA_GAIN_MSK;
> + setup->afe |= FIELD_PREP(AD4170_AFE_PGA_GAIN_MSK, pga);
> +
> + return ad4170_write_channel_setup(st, chan->address, false);
> +}
> +
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v5 05/11] iio: adc: ad4170: Add digital filter and sample frequency config support
2025-06-10 20:32 ` [PATCH v5 05/11] iio: adc: ad4170: Add digital filter and sample frequency config support Marcelo Schmitt
@ 2025-06-16 20:53 ` David Lechner
0 siblings, 0 replies; 35+ messages in thread
From: David Lechner @ 2025-06-16 20:53 UTC (permalink / raw)
To: Marcelo Schmitt, linux-iio, devicetree, linux-gpio, linux-kernel
Cc: jic23, lars, Michael.Hennerich, nuno.sa, andy, robh, krzk+dt,
conor+dt, linus.walleij, brgl, marcelo.schmitt1
On 6/10/25 3:32 PM, Marcelo Schmitt wrote:
> Add support for sinc3, sinc5, and averaged sinc5 digital filters along with
> sample frequency configuration.
Wouldn't mind having a sentence here explaining why post filter control
was omitted.
>
> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
> ---
...
>
> +static const char * const ad4170_filt_names[] = {
> + [AD4170_SINC5_AVG] = "sinc5+avg",
Do we need to document this as possible type in
Documentation/ABI/testing/sysfs-bus-iio?
> + [AD4170_SINC5] = "sinc5",
> + [AD4170_SINC3] = "sinc3",
> +};
> +
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v5 07/11] iio: adc: ad4170: Add clock provider support
2025-06-10 20:33 ` [PATCH v5 07/11] iio: adc: ad4170: Add clock provider support Marcelo Schmitt
@ 2025-06-16 21:11 ` David Lechner
2025-06-17 6:24 ` Andy Shevchenko
0 siblings, 1 reply; 35+ messages in thread
From: David Lechner @ 2025-06-16 21:11 UTC (permalink / raw)
To: Marcelo Schmitt, linux-iio, devicetree, linux-gpio, linux-kernel
Cc: jic23, lars, Michael.Hennerich, nuno.sa, andy, robh, krzk+dt,
conor+dt, linus.walleij, brgl, marcelo.schmitt1
On 6/10/25 3:33 PM, Marcelo Schmitt wrote:
> The AD4170 chip can use an externally supplied clock at the XTAL2 pin, or
> an external crystal connected to the XTAL1 and XTAL2 pins. Alternatively,
> the AD4170 can provide its 16 MHz internal clock at the XTAL2 pin. In
> addition, the chip has a programmable clock divider that allows dividing
> the external or internal clock frequency, however, control for that is not
> provided in this patch. Extend the AD4170 driver so it effectively uses the
> provided external clock, if any, or supplies its own clock as a clock
> provider.
>
...
> +static int ad4170_clock_select(struct iio_dev *indio_dev)
> +{
> + struct ad4170_state *st = iio_priv(indio_dev);
> + struct device *dev = &st->spi->dev;
> + struct clk *ext_clk;
> + int ret;
> +
> + ext_clk = devm_clk_get_optional_enabled(dev, NULL);
> + if (IS_ERR(ext_clk))
> + return dev_err_probe(dev, PTR_ERR(ext_clk),
> + "Failed to get external clock\n");
> +
> + if (!ext_clk) {
> + /* Use internal clock reference */
> + st->mclk_hz = AD4170_INT_CLOCK_16MHZ;
> + st->clock_ctrl |= FIELD_PREP(AD4170_CLOCK_CTRL_CLOCKSEL_MSK,
> + AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT);
> +
> + if (!device_property_read_bool(&st->spi->dev, "#clock-cells"))
This isn't a flag, so device_property_present() is probably more correct.
> + return 0;
> +
> + return ad4170_register_clk_provider(indio_dev);
> + }
> +
> + /* Read optional clock-names prop to specify the external clock type */
> + ret = device_property_match_property_string(dev, "clock-names",
> + ad4170_clk_sel,
> + ARRAY_SIZE(ad4170_clk_sel));
> +
> + ret = ret < 0 ? 0 : ret; /* Default to external clock if no clock-names */
> + st->clock_ctrl |= FIELD_PREP(AD4170_CLOCK_CTRL_CLOCKSEL_MSK,
> + AD4170_CLOCK_CTRL_CLOCKSEL_EXT + ret);
> +
> + st->mclk_hz = clk_get_rate(ext_clk);
> + if (st->mclk_hz < AD4170_EXT_CLOCK_MHZ_MIN ||
> + st->mclk_hz > AD4170_EXT_CLOCK_MHZ_MAX) {
> + return dev_err_probe(dev, -EINVAL,
> + "Invalid external clock frequency %u\n",
> + st->mclk_hz);
> + }
> +
> + return 0;
> +}
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v5 07/11] iio: adc: ad4170: Add clock provider support
2025-06-16 21:11 ` David Lechner
@ 2025-06-17 6:24 ` Andy Shevchenko
0 siblings, 0 replies; 35+ messages in thread
From: Andy Shevchenko @ 2025-06-17 6:24 UTC (permalink / raw)
To: David Lechner
Cc: Marcelo Schmitt, linux-iio, devicetree, linux-gpio, linux-kernel,
jic23, lars, Michael.Hennerich, nuno.sa, andy, robh, krzk+dt,
conor+dt, linus.walleij, brgl, marcelo.schmitt1
On Tue, Jun 17, 2025 at 12:11 AM David Lechner <dlechner@baylibre.com> wrote:
> On 6/10/25 3:33 PM, Marcelo Schmitt wrote:
...
> > + if (!device_property_read_bool(&st->spi->dev, "#clock-cells"))
>
> This isn't a flag, so device_property_present() is probably more correct.
>
> > + return 0;
Good catch! +1 to this, it must not be read_bool as it's not a boolean property.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v5 02/11] iio: adc: Add basic support for AD4170
2025-06-16 20:41 ` David Lechner
@ 2025-06-17 18:54 ` Marcelo Schmitt
0 siblings, 0 replies; 35+ messages in thread
From: Marcelo Schmitt @ 2025-06-17 18:54 UTC (permalink / raw)
To: David Lechner
Cc: Marcelo Schmitt, linux-iio, devicetree, linux-gpio, linux-kernel,
Ana-Maria Cusco, jic23, lars, Michael.Hennerich, nuno.sa, andy,
robh, krzk+dt, conor+dt, linus.walleij, brgl
On 06/16, David Lechner wrote:
> On 6/10/25 3:31 PM, Marcelo Schmitt wrote:
> > From: Ana-Maria Cusco <ana-maria.cusco@analog.com>
> >
> > The AD4170 is a multichannel, low noise, 24-bit precision sigma-delta
> > analog to digital converter. The AD4170 design offers a flexible data
> > acquisition solution with crosspoint multiplexed analog inputs,
> > configurable ADC voltage reference inputs, ultra-low noise integrated PGA,
> > digital filtering, wide range of configurable output data rates, internal
> > oscillator and temperature sensor, four GPIOs, and integrated features for
> > interfacing with load cell weigh scales, RTD, and thermocouple sensors.
> >
> > Add basic support for the AD4170 ADC with the following features:
> > - Single-shot read.
> > - Analog front end PGA configuration.
> > - Differential and pseudo-differential input configuration.
> >
>
> ...
>
> > +static int ad4170_fill_scale_tbl(struct iio_dev *indio_dev,
> > + struct iio_chan_spec const *chan)
> > +{
> > + struct ad4170_state *st = iio_priv(indio_dev);
> > + struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];
> > + struct device *dev = &st->spi->dev;
> > + int bipolar = chan->scan_type.sign == 's' ? 1 : 0;
> > + int precision_bits = chan->scan_type.realbits;
> > + int pga, ainm_voltage, ret;
> > + unsigned long long offset;
> > +
> > + ainm_voltage = 0;
> > + ret = ad4170_get_ain_voltage_uv(st, chan->channel2, &ainm_voltage);
> > + if (ret < 0)
> > + return dev_err_probe(dev, ret, "Failed to fill scale table\n");
> > +
> > + for (pga = 0; pga < AD4170_NUM_PGA_OPTIONS; pga++) {
>
> From what I read in the datasheet, it sounds like if adi,reference-buffer is
> precharge, then the PGA is bypassed, so there would only be 1 option in that
> case (gain = 1).
>
Although not explicit in the datasheet, looks like there are two precharge
buffers. One precharge buffer is used with the voltage reference inputs and is
associated with the adi,positive/negative-reference-buffer dt properties. The
configuration of that buffer is set through the REF_BUF_P/M fields of AFE
registers. The datasheet doesn't mention the PGA on the section dedicated to
describing reference and reference buffering features.
The other places a precharge buffer is mentioned refer to it as 'gain = 1 precharge'.
My understanding is that the PGA bypass precharge buffer is a different buffer
that is only used when PGA option 9 is set in the PGA_GAIN filed of AFE reg.
The PGA bypass precharge buffer would be used in the analog input path while
the reference buffers would be used in the reference input path.
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v5 08/11] iio: adc: ad4170: Add GPIO controller support
2025-06-10 20:33 ` [PATCH v5 08/11] iio: adc: ad4170: Add GPIO controller support Marcelo Schmitt
@ 2025-06-18 10:15 ` Linus Walleij
0 siblings, 0 replies; 35+ messages in thread
From: Linus Walleij @ 2025-06-18 10:15 UTC (permalink / raw)
To: Marcelo Schmitt
Cc: linux-iio, devicetree, linux-gpio, linux-kernel, jic23, lars,
Michael.Hennerich, dlechner, nuno.sa, andy, robh, krzk+dt,
conor+dt, brgl, marcelo.schmitt1, Bartosz Golaszewski
On Tue, Jun 10, 2025 at 10:33 PM Marcelo Schmitt
<marcelo.schmitt@analog.com> wrote:
> The AD4170 has four multifunctional pins that can be used as GPIOs. The
> GPIO functionality can be accessed when the AD4170 chip is not busy
> performing continuous data capture or handling any other register
> read/write request. Also, the AD4170 does not provide any interrupt based
> on GPIO pin states so AD4170 GPIOs can't be used as interrupt sources.
>
> Implement gpio_chip callbacks to make AD4170 GPIO pins controllable through
> the gpiochip interface.
>
> Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Looks good to me!
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v5 02/11] iio: adc: Add basic support for AD4170
2025-06-10 20:31 ` [PATCH v5 02/11] iio: adc: Add basic support for AD4170 Marcelo Schmitt
2025-06-10 21:10 ` Andy Shevchenko
2025-06-16 20:41 ` David Lechner
@ 2025-06-18 17:37 ` Dan Carpenter
2025-06-18 17:59 ` Andy Shevchenko
2 siblings, 1 reply; 35+ messages in thread
From: Dan Carpenter @ 2025-06-18 17:37 UTC (permalink / raw)
To: oe-kbuild, Marcelo Schmitt, linux-iio, devicetree, linux-gpio,
linux-kernel
Cc: lkp, oe-kbuild-all, Ana-Maria Cusco, jic23, lars,
Michael.Hennerich, dlechner, nuno.sa, andy, robh, krzk+dt,
conor+dt, linus.walleij, brgl, marcelo.schmitt1
Hi Marcelo,
kernel test robot noticed the following build warnings:
url: https://github.com/intel-lab-lkp/linux/commits/Marcelo-Schmitt/dt-bindings-iio-adc-Add-AD4170/20250611-101842
base: 4c6073fec2fee4827fa0dd8a4ab4e6f7bbc05ee6
patch link: https://lore.kernel.org/r/48598c0753cccf515addbe85acba3f883ff8f036.1749582679.git.marcelo.schmitt%40analog.com
patch subject: [PATCH v5 02/11] iio: adc: Add basic support for AD4170
config: powerpc-randconfig-r072-20250613 (https://download.01.org/0day-ci/archive/20250614/202506140009.GdV0BtKr-lkp@intel.com/config)
compiler: clang version 21.0.0git (https://github.com/llvm/llvm-project f819f46284f2a79790038e1f6649172789734ae8)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
| Closes: https://lore.kernel.org/r/202506140009.GdV0BtKr-lkp@intel.com/
smatch warnings:
drivers/iio/adc/ad4170.c:1181 ad4170_parse_adc_channel_type() warn: passing zero to 'dev_err_probe'
vim +/dev_err_probe +1181 drivers/iio/adc/ad4170.c
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1170 static int ad4170_parse_adc_channel_type(struct device *dev,
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1171 struct fwnode_handle *child,
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1172 struct iio_chan_spec *chan)
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1173 {
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1174 int ret, ret2;
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1175 u32 pins[2];
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1176
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1177 /* Parse pseudo-differential channel configuration */
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1178 ret = fwnode_property_read_u32(child, "single-channel", &pins[0]);
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1179 ret2 = fwnode_property_read_u32(child, "common-mode-channel", &pins[1]);
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1180 if (!ret && ret2)
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 @1181 return dev_err_probe(dev, ret,
^^^
ret is zero, so this returns success. s/ret/ret2/.
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1182 "single-ended channels must define common-mode-channel\n");
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1183
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1184 if (!ret && !ret2) {
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1185 chan->differential = false;
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1186 chan->channel = pins[0];
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1187 chan->channel2 = pins[1];
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1188 return 0;
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1189 }
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1190 /* Failed to parse pseudo-diff chan props so try diff chan */
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1191
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1192 /* Parse differential channel configuration */
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1193 ret = fwnode_property_read_u32_array(child, "diff-channels", pins,
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1194 ARRAY_SIZE(pins));
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1195 if (!ret) {
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1196 chan->differential = true;
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1197 chan->channel = pins[0];
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1198 chan->channel2 = pins[1];
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1199 return 0;
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1200 }
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1201 return dev_err_probe(dev, ret,
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1202 "Channel must define one of diff-channels or single-channel.\n");
dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1203 }
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v5 02/11] iio: adc: Add basic support for AD4170
2025-06-18 17:37 ` Dan Carpenter
@ 2025-06-18 17:59 ` Andy Shevchenko
0 siblings, 0 replies; 35+ messages in thread
From: Andy Shevchenko @ 2025-06-18 17:59 UTC (permalink / raw)
To: Dan Carpenter
Cc: oe-kbuild, Marcelo Schmitt, linux-iio, devicetree, linux-gpio,
linux-kernel, lkp, oe-kbuild-all, Ana-Maria Cusco, jic23, lars,
Michael.Hennerich, dlechner, nuno.sa, andy, robh, krzk+dt,
conor+dt, linus.walleij, brgl, marcelo.schmitt1
On Wed, Jun 18, 2025 at 08:37:53PM +0300, Dan Carpenter wrote:
> Hi Marcelo,
>
> kernel test robot noticed the following build warnings:
>
> url: https://github.com/intel-lab-lkp/linux/commits/Marcelo-Schmitt/dt-bindings-iio-adc-Add-AD4170/20250611-101842
> base: 4c6073fec2fee4827fa0dd8a4ab4e6f7bbc05ee6
> patch link: https://lore.kernel.org/r/48598c0753cccf515addbe85acba3f883ff8f036.1749582679.git.marcelo.schmitt%40analog.com
> patch subject: [PATCH v5 02/11] iio: adc: Add basic support for AD4170
> config: powerpc-randconfig-r072-20250613 (https://download.01.org/0day-ci/archive/20250614/202506140009.GdV0BtKr-lkp@intel.com/config)
> compiler: clang version 21.0.0git (https://github.com/llvm/llvm-project f819f46284f2a79790038e1f6649172789734ae8)
>
> If you fix the issue in a separate patch/commit (i.e. not just a new version of
> the same patch/commit), kindly add following tags
> | Reported-by: kernel test robot <lkp@intel.com>
> | Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
> | Closes: https://lore.kernel.org/r/202506140009.GdV0BtKr-lkp@intel.com/
>
> smatch warnings:
> drivers/iio/adc/ad4170.c:1181 ad4170_parse_adc_channel_type() warn: passing zero to 'dev_err_probe'
>
> vim +/dev_err_probe +1181 drivers/iio/adc/ad4170.c
>
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1170 static int ad4170_parse_adc_channel_type(struct device *dev,
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1171 struct fwnode_handle *child,
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1172 struct iio_chan_spec *chan)
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1173 {
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1174 int ret, ret2;
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1175 u32 pins[2];
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1176
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1177 /* Parse pseudo-differential channel configuration */
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1178 ret = fwnode_property_read_u32(child, "single-channel", &pins[0]);
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1179 ret2 = fwnode_property_read_u32(child, "common-mode-channel", &pins[1]);
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1180 if (!ret && ret2)
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 @1181 return dev_err_probe(dev, ret,
> ^^^
> ret is zero, so this returns success. s/ret/ret2/.
>
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1182 "single-ended channels must define common-mode-channel\n");
Instead of ret and ret2 this code should be refactored to use
_preperty_present() beforehands and return an error to the caller if it's
present but failed to be read or not optional at all.
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1184 if (!ret && !ret2) {
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1185 chan->differential = false;
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1186 chan->channel = pins[0];
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1187 chan->channel2 = pins[1];
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1188 return 0;
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1189 }
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1190 /* Failed to parse pseudo-diff chan props so try diff chan */
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1191
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1192 /* Parse differential channel configuration */
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1193 ret = fwnode_property_read_u32_array(child, "diff-channels", pins,
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1194 ARRAY_SIZE(pins));
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1195 if (!ret) {
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1196 chan->differential = true;
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1197 chan->channel = pins[0];
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1198 chan->channel2 = pins[1];
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1199 return 0;
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1200 }
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1201 return dev_err_probe(dev, ret,
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1202 "Channel must define one of diff-channels or single-channel.\n");
> dfefd2b2405829 Ana-Maria Cusco 2025-06-10 1203 }
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v5 01/11] dt-bindings: iio: adc: Add AD4170
2025-06-16 20:41 ` David Lechner
@ 2025-06-21 16:28 ` Jonathan Cameron
2025-06-23 16:03 ` Conor Dooley
0 siblings, 1 reply; 35+ messages in thread
From: Jonathan Cameron @ 2025-06-21 16:28 UTC (permalink / raw)
To: David Lechner
Cc: Conor Dooley, Marcelo Schmitt, linux-iio, devicetree, linux-gpio,
linux-kernel, lars, Michael.Hennerich, nuno.sa, andy, robh,
krzk+dt, conor+dt, linus.walleij, brgl, marcelo.schmitt1
> >> +
> >> +$defs:
> >> + reference-buffer:
> >> + description: |
> >> + Enable precharge buffer, full buffer, or skip reference buffering of
> >> + the positive/negative voltage reference. Because the output impedance
> >> + of the source driving the voltage reference inputs may be dynamic,
> >> + resistive/capacitive combinations of those inputs can cause DC gain
> >> + errors if the reference inputs go unbuffered into the ADC. Enable
> >> + reference buffering if the provided reference source has dynamic high
> >> + impedance output. Note the absolute voltage allowed on REFINn+ and REFINn-
> >> + inputs is from AVSS - 50 mV to AVDD + 50 mV when the reference buffers are
> >> + disabled but narrows to AVSS to AVDD when reference buffering is enabled
> >> + or in precharge mode. The valid options for this property are:
> >> + 0: Reference precharge buffer.
> >> + 1: Full reference buffering.
> >> + 2: Bypass reference buffers (buffering disabled).
> >> + $ref: /schemas/types.yaml#/definitions/uint32
> >> + enum: [0, 1, 2]
> >> + default: 1
> >
> > Why make this property a uint32, rather than a string where you can use
> > something like "precharge", "full" and "bypass" (or "disabled")? The
> > next similar device could use something slightly different then the
> > binding becomes pretty clunky.
> > Can you explain why this is a dt property rather than something
> > adjustable at runtime?
> >
> > Otherwise, what you have here looks sane enough to me - but I'd like to
> > see some comments from Jonathan or David etc about your approach to the
> > excitation properties.
>
> This looks like something that should be in the devicetree to me. For example
> if the external reference supply is high impedance, buffering is pretty
> much required. And using precharge is an application design choice to
> reduce THD at the expense of other limitations.
>
Agreed that this pretty much only makes sense in DT.
In the ideal world we would have firm rules on when to enable buffering
etc and then the DT would describe the impedance of the circuit connected
and any other relevant properties and then we'd have the driver enable it
only when those rigid rules dictated that we should.
Sadly no such simple rules exist (as far as I know) so we just expose the thing
that gets set dependent on someone's judgement of the suitability of
the buffering choice given the circuit being connected to the input.
If we pushed it to userspace we'd just end up with a per device blob
that dictated the mode to pick on boot and left it like that. So effectively
another bit of firmware :(
J
<cropping other comments>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v5 01/11] dt-bindings: iio: adc: Add AD4170
2025-06-16 15:41 ` Conor Dooley
2025-06-16 17:58 ` Marcelo Schmitt
2025-06-16 20:41 ` David Lechner
@ 2025-06-21 16:37 ` Jonathan Cameron
2 siblings, 0 replies; 35+ messages in thread
From: Jonathan Cameron @ 2025-06-21 16:37 UTC (permalink / raw)
To: Conor Dooley
Cc: Marcelo Schmitt, linux-iio, devicetree, linux-gpio, linux-kernel,
lars, Michael.Hennerich, dlechner, nuno.sa, andy, robh, krzk+dt,
conor+dt, linus.walleij, brgl, marcelo.schmitt1
>
> Otherwise, what you have here looks sane enough to me - but I'd like to
> see some comments from Jonathan or David etc about your approach to the
> excitation properties.
They look sane to me. The complexity of devices that handle weigh cells and
similar are always a pain. In theory we could have a go at describing
the weigh-cell in DT and then try to derive the 'right' settings but that
seems like a very complex thing to do. Long time since I did anything with
weigh cells, but I think you mostly read the settings to use of a datasheet rather
than deriving them from first principles. Thermocouples are similar (I'm not
that familiar with RTDs)
As to the handling of the different sensor types - that seems like a sensible
way to constrain the binding and end up with sane readable combinations rather
than a bunch of excitation settings with no info on what is connected.
Not sure this is the perfect solution, but to me it looks good enough and
flexible / general enough to cover a wide range of other devices.
Jonathan
>
> Cheers,
> Conor.
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v5 01/11] dt-bindings: iio: adc: Add AD4170
2025-06-21 16:28 ` Jonathan Cameron
@ 2025-06-23 16:03 ` Conor Dooley
0 siblings, 0 replies; 35+ messages in thread
From: Conor Dooley @ 2025-06-23 16:03 UTC (permalink / raw)
To: Jonathan Cameron
Cc: David Lechner, Marcelo Schmitt, linux-iio, devicetree, linux-gpio,
linux-kernel, lars, Michael.Hennerich, nuno.sa, andy, robh,
krzk+dt, conor+dt, linus.walleij, brgl, marcelo.schmitt1
[-- Attachment #1: Type: text/plain, Size: 3360 bytes --]
On Sat, Jun 21, 2025 at 05:28:08PM +0100, Jonathan Cameron wrote:
>
> > >> +
> > >> +$defs:
> > >> + reference-buffer:
> > >> + description: |
> > >> + Enable precharge buffer, full buffer, or skip reference buffering of
> > >> + the positive/negative voltage reference. Because the output impedance
> > >> + of the source driving the voltage reference inputs may be dynamic,
> > >> + resistive/capacitive combinations of those inputs can cause DC gain
> > >> + errors if the reference inputs go unbuffered into the ADC. Enable
> > >> + reference buffering if the provided reference source has dynamic high
> > >> + impedance output. Note the absolute voltage allowed on REFINn+ and REFINn-
> > >> + inputs is from AVSS - 50 mV to AVDD + 50 mV when the reference buffers are
> > >> + disabled but narrows to AVSS to AVDD when reference buffering is enabled
> > >> + or in precharge mode. The valid options for this property are:
> > >> + 0: Reference precharge buffer.
> > >> + 1: Full reference buffering.
> > >> + 2: Bypass reference buffers (buffering disabled).
> > >> + $ref: /schemas/types.yaml#/definitions/uint32
> > >> + enum: [0, 1, 2]
> > >> + default: 1
> > >
> > > Why make this property a uint32, rather than a string where you can use
> > > something like "precharge", "full" and "bypass" (or "disabled")? The
> > > next similar device could use something slightly different then the
> > > binding becomes pretty clunky.
> > > Can you explain why this is a dt property rather than something
> > > adjustable at runtime?
> > >
> > > Otherwise, what you have here looks sane enough to me - but I'd like to
> > > see some comments from Jonathan or David etc about your approach to the
> > > excitation properties.
> >
> > This looks like something that should be in the devicetree to me. For example
> > if the external reference supply is high impedance, buffering is pretty
> > much required. And using precharge is an application design choice to
> > reduce THD at the expense of other limitations.
> >
>
> Agreed that this pretty much only makes sense in DT.
>
> In the ideal world we would have firm rules on when to enable buffering
> etc and then the DT would describe the impedance of the circuit connected
> and any other relevant properties and then we'd have the driver enable it
> only when those rigid rules dictated that we should.
>
> Sadly no such simple rules exist (as far as I know) so we just expose the thing
> that gets set dependent on someone's judgement of the suitability of
> the buffering choice given the circuit being connected to the input.
>
> If we pushed it to userspace we'd just end up with a per device blob
> that dictated the mode to pick on boot and left it like that. So effectively
> another bit of firmware :(
Can't remember if I replied to David's mail here or not, I pretty much
just asked the question because I didn't understand why the usecase and
wanted an explanation for my benefit. Probably makes no sense to explain
why a knob exists in the binding when anyone using the device will not
need one, but that does mean that at times with these devices that are
unfamiliar to me I have to have it explained to me why something is set
in stone.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 35+ messages in thread
end of thread, other threads:[~2025-06-23 16:03 UTC | newest]
Thread overview: 35+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-06-10 20:30 [PATCH v5 00/11] iio: adc: Add support for AD4170 series of ADCs Marcelo Schmitt
2025-06-10 20:31 ` [PATCH v5 01/11] dt-bindings: iio: adc: Add AD4170 Marcelo Schmitt
2025-06-16 15:41 ` Conor Dooley
2025-06-16 17:58 ` Marcelo Schmitt
2025-06-16 20:41 ` David Lechner
2025-06-21 16:28 ` Jonathan Cameron
2025-06-23 16:03 ` Conor Dooley
2025-06-21 16:37 ` Jonathan Cameron
2025-06-10 20:31 ` [PATCH v5 02/11] iio: adc: Add basic support for AD4170 Marcelo Schmitt
2025-06-10 21:10 ` Andy Shevchenko
2025-06-11 21:04 ` Marcelo Schmitt
2025-06-12 12:48 ` Andy Shevchenko
2025-06-12 14:03 ` Marcelo Schmitt
2025-06-12 18:48 ` Andy Shevchenko
2025-06-14 10:51 ` Jonathan Cameron
2025-06-14 10:52 ` Jonathan Cameron
2025-06-16 20:41 ` David Lechner
2025-06-17 18:54 ` Marcelo Schmitt
2025-06-18 17:37 ` Dan Carpenter
2025-06-18 17:59 ` Andy Shevchenko
2025-06-10 20:31 ` [PATCH v5 03/11] iio: adc: ad4170: Add support for calibration gain Marcelo Schmitt
2025-06-10 20:32 ` [PATCH v5 04/11] iio: adc: ad4170: Add support for calibration bias Marcelo Schmitt
2025-06-10 20:32 ` [PATCH v5 05/11] iio: adc: ad4170: Add digital filter and sample frequency config support Marcelo Schmitt
2025-06-16 20:53 ` David Lechner
2025-06-10 20:32 ` [PATCH v5 06/11] iio: adc: ad4170: Add support for buffered data capture Marcelo Schmitt
2025-06-10 21:17 ` Andy Shevchenko
2025-06-10 20:33 ` [PATCH v5 07/11] iio: adc: ad4170: Add clock provider support Marcelo Schmitt
2025-06-16 21:11 ` David Lechner
2025-06-17 6:24 ` Andy Shevchenko
2025-06-10 20:33 ` [PATCH v5 08/11] iio: adc: ad4170: Add GPIO controller support Marcelo Schmitt
2025-06-18 10:15 ` Linus Walleij
2025-06-10 20:33 ` [PATCH v5 09/11] iio: adc: ad4170: Add support for internal temperature sensor Marcelo Schmitt
2025-06-10 20:33 ` [PATCH v5 10/11] iio: adc: ad4170: Add support for weigh scale and RTD sensors Marcelo Schmitt
2025-06-10 20:34 ` [PATCH v5 11/11] iio: adc: ad4170: Add timestamp channel Marcelo Schmitt
2025-06-14 11:04 ` [PATCH v5 00/11] iio: adc: Add support for AD4170 series of ADCs Jonathan Cameron
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).